blob: 386f9deb701f8dc50922c57e7ca15ec31b7ecbf9 [file] [log] [blame]
Stefan Roese779e9752007-08-14 14:44:41 +02001/*
2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese779e9752007-08-14 14:44:41 +02006 */
7
8/************************************************************************
9 * zeus.h - configuration for Zeus board
10 ***********************************************************************/
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14/*-----------------------------------------------------------------------
15 * High Level Configuration Options
16 *----------------------------------------------------------------------*/
17#define CONFIG_ZEUS 1 /* Board is Zeus */
18#define CONFIG_4xx 1 /* ... PPC4xx family */
19#define CONFIG_405EP 1 /* Specifc 405EP support*/
20
Wolfgang Denk2ae18242010-10-06 09:05:45 +020021#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
22
Stefan Roese779e9752007-08-14 14:44:41 +020023#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
24
25#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
26#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
27
28#define PLLMR0_DEFAULT PLLMR0_333_111_55_111
29#define PLLMR1_DEFAULT PLLMR1_333_111_55_111
30
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020031#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Stefan Roese779e9752007-08-14 14:44:41 +020032
33#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
34
Ben Warren96e21f82008-10-27 23:50:15 -070035#define CONFIG_PPC4xx_EMAC
Stefan Roese779e9752007-08-14 14:44:41 +020036#define CONFIG_MII 1 /* MII PHY management */
37#define CONFIG_PHY_ADDR 0x01 /* PHY address */
38#define CONFIG_HAS_ETH1 1
39#define CONFIG_PHY1_ADDR 0x11 /* EMAC1 PHY address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020040#define CONFIG_SYS_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
Stefan Roese779e9752007-08-14 14:44:41 +020041#define CONFIG_PHY_RESET 1
42#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
43
Stefan Roese3b3bff42007-08-14 16:36:29 +020044/*
45 * BOOTP options
46 */
47#define CONFIG_BOOTP_BOOTFILESIZE
48#define CONFIG_BOOTP_BOOTPATH
49#define CONFIG_BOOTP_GATEWAY
50#define CONFIG_BOOTP_HOSTNAME
51
52/*
53 * Command line configuration.
54 */
55#include <config_cmd_default.h>
56
57#define CONFIG_CMD_ASKENV
58#define CONFIG_CMD_CACHE
59#define CONFIG_CMD_DHCP
60#define CONFIG_CMD_DIAG
61#define CONFIG_CMD_EEPROM
62#define CONFIG_CMD_ELF
63#define CONFIG_CMD_I2C
64#define CONFIG_CMD_IRQ
Stefan Roese3b3bff42007-08-14 16:36:29 +020065#define CONFIG_CMD_MII
66#define CONFIG_CMD_NET
67#define CONFIG_CMD_NFS
68#define CONFIG_CMD_PING
69#define CONFIG_CMD_REGINFO
Stefan Roese779e9752007-08-14 14:44:41 +020070
71/* POST support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
73 CONFIG_SYS_POST_CPU | \
74 CONFIG_SYS_POST_CACHE | \
75 CONFIG_SYS_POST_UART | \
76 CONFIG_SYS_POST_ETHER)
Stefan Roese779e9752007-08-14 14:44:41 +020077
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_POST_ETHER_EXT_LOOPBACK /* eth POST using ext loopack connector */
Stefan Roese779e9752007-08-14 14:44:41 +020079
80/* Define here the base-addresses of the UARTs to test in POST */
Stefan Roese5d7c73e2010-09-29 16:58:38 +020081#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1 }
Stefan Roese779e9752007-08-14 14:44:41 +020082
83#define CONFIG_LOGBUFFER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */
Stefan Roese779e9752007-08-14 14:44:41 +020085
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
Stefan Roese779e9752007-08-14 14:44:41 +020087
Stefan Roese779e9752007-08-14 14:44:41 +020088#undef CONFIG_WATCHDOG /* watchdog disabled */
89
90/*-----------------------------------------------------------------------
91 * SDRAM
92 *----------------------------------------------------------------------*/
93/*
94 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
95 */
96#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
97#define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */
98
99/* SDRAM timings used in datasheet */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
101#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
102#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
103#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
104#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
Stefan Roese779e9752007-08-14 14:44:41 +0200105
106/*-----------------------------------------------------------------------
107 * Serial Port
108 *----------------------------------------------------------------------*/
Stefan Roese550650d2010-09-20 16:05:31 +0200109#define CONFIG_CONS_INDEX 1
110#define CONFIG_SYS_NS16550
111#define CONFIG_SYS_NS16550_SERIAL
112#define CONFIG_SYS_NS16550_REG_SIZE 1
113#define CONFIG_SYS_NS16550_CLK get_serial_clock()
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
Stefan Roese550650d2010-09-20 16:05:31 +0200115#define CONFIG_SYS_BASE_BAUD 691200
Stefan Roese779e9752007-08-14 14:44:41 +0200116#define CONFIG_BAUDRATE 115200
Stefan Roese779e9752007-08-14 14:44:41 +0200117
Stefan Roese550650d2010-09-20 16:05:31 +0200118#define CONFIG_SYS_BAUDRATE_TABLE \
119 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
Stefan Roese779e9752007-08-14 14:44:41 +0200120
121/*-----------------------------------------------------------------------
122 * Miscellaneous configurable options
123 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_LONGHELP /* undef to save memory */
125#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Stefan Roese3b3bff42007-08-14 16:36:29 +0200126#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Stefan Roese779e9752007-08-14 14:44:41 +0200128#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Stefan Roese779e9752007-08-14 14:44:41 +0200130#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
132#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
133#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Stefan Roese779e9752007-08-14 14:44:41 +0200134
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
136#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
Stefan Roese779e9752007-08-14 14:44:41 +0200137
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
139#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
Stefan Roese779e9752007-08-14 14:44:41 +0200140
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Stefan Roese779e9752007-08-14 14:44:41 +0200142
143#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Stefan Roese779e9752007-08-14 14:44:41 +0200145
146#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
147#define CONFIG_LOOPW 1 /* enable loopw command */
148#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
149#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
150#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
151
152/*-----------------------------------------------------------------------
153 * I2C
154 *----------------------------------------------------------------------*/
Dirk Eibach880540d2013-04-25 02:40:01 +0000155#define CONFIG_SYS_I2C
156#define CONFIG_SYS_I2C_PPC4XX
157#define CONFIG_SYS_I2C_PPC4XX_CH0
158#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
159#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
Stefan Roese779e9752007-08-14 14:44:41 +0200160
161/* these are for the ST M24C02 2kbit serial i2c eeprom */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
163#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
Stefan Roese779e9752007-08-14 14:44:41 +0200164/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
Stefan Roese779e9752007-08-14 14:44:41 +0200166
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* 8 byte write page size */
168#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
Stefan Roese779e9752007-08-14 14:44:41 +0200169
170/*
171 * The layout of the I2C EEPROM, used for bootstrap setup and for board-
172 * specific values, like ethaddr... that can be restored via the sw-reset
173 * button
174 */
175#define FACTORY_RESET_I2C_EEPROM 0x50
176#define FACTORY_RESET_ENV_OFFS 0x80
177#define FACTORY_RESET_ENV_SIZE 0x80
178
179/*-----------------------------------------------------------------------
180 * Start addresses for the final memory configuration
181 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
Stefan Roese779e9752007-08-14 14:44:41 +0200183 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_SDRAM_BASE 0x00000000
185#define CONFIG_SYS_FLASH_BASE 0xFF000000
186#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
187#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
188#define CONFIG_SYS_MONITOR_BASE (-CONFIG_SYS_MONITOR_LEN)
Stefan Roese779e9752007-08-14 14:44:41 +0200189
190/*
191 * For booting Linux, the board info and command line data
192 * have to be in the first 8 MB of memory, since this is
193 * the maximum mapped by the Linux kernel during initialization.
194 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Stefan Roese779e9752007-08-14 14:44:41 +0200196
197/*-----------------------------------------------------------------------
198 * FLASH organization
199 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200201#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Stefan Roese779e9752007-08-14 14:44:41 +0200202
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
Stefan Roese779e9752007-08-14 14:44:41 +0200204
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
206#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
Stefan Roese779e9752007-08-14 14:44:41 +0200207
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
209#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Stefan Roese779e9752007-08-14 14:44:41 +0200210
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
212#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
Stefan Roese779e9752007-08-14 14:44:41 +0200213
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
215#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
Stefan Roese779e9752007-08-14 14:44:41 +0200216
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200217#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200218#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200220#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
Stefan Roese779e9752007-08-14 14:44:41 +0200221
222/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200223#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
224#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Stefan Roese779e9752007-08-14 14:44:41 +0200225#endif
226
227/*-----------------------------------------------------------------------
Stefan Roese779e9752007-08-14 14:44:41 +0200228 * Definitions for initial stack pointer and data area (in data cache)
229 */
230/* use on chip memory (OCM) for temperary stack until sdram is tested */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_TEMP_STACK_OCM 1
Stefan Roese779e9752007-08-14 14:44:41 +0200232
233/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
235#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
236#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of OCM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200237#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
Stefan Roese779e9752007-08-14 14:44:41 +0200238
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200239#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Stefan Roese779e9752007-08-14 14:44:41 +0200240/* reserve some memory for POST and BOOT limit info */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 16)
Stefan Roese779e9752007-08-14 14:44:41 +0200242
243/* extra data in OCM */
Michael Zaidman800eb092010-09-20 08:51:53 +0200244#define CONFIG_SYS_POST_MAGIC \
245 (CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_GBL_DATA_OFFSET - 8)
246#define CONFIG_SYS_POST_VAL \
247 (CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_GBL_DATA_OFFSET - 12)
Stefan Roese779e9752007-08-14 14:44:41 +0200248
249/*-----------------------------------------------------------------------
250 * External Bus Controller (EBC) Setup
251 */
252
253/* Memory Bank 0 (Flash 16M) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_EBC_PB0AP 0x05815600
255#define CONFIG_SYS_EBC_PB0CR 0xFF09A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit */
Stefan Roese779e9752007-08-14 14:44:41 +0200256
257/*-----------------------------------------------------------------------
258 * Definitions for GPIO setup (PPC405EP specific)
259 *
260 * GPIO0[0] - External Bus Controller BLAST output
261 * GPIO0[1-9] - Instruction trace outputs
262 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
263 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
264 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
265 * GPIO0[24-27] - UART0 control signal inputs/outputs
266 * GPIO0[28-29] - UART1 data signal input/output
267 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
268 */
Stefan Roeseafabb492010-09-12 06:21:37 +0200269#define CONFIG_SYS_GPIO0_OSRL 0x15555550 /* Chip selects */
270#define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* UART_DTR-pin 27 alt out */
271#define CONFIG_SYS_GPIO0_ISR1L 0x10000041 /* Pin 2, 12 is input */
272#define CONFIG_SYS_GPIO0_ISR1H 0x15505440 /* OUT: LEDs 22/23; IN: pin12,2, NVALID# */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_GPIO0_TSRL 0x00000000
Stefan Roeseafabb492010-09-12 06:21:37 +0200274#define CONFIG_SYS_GPIO0_TSRH 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_GPIO0_TCR 0xBFF68317 /* 3-state OUT: 22/23/29; 12,2 is not 3-state */
276#define CONFIG_SYS_GPIO0_ODR 0x00000000
Stefan Roese779e9752007-08-14 14:44:41 +0200277
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_GPIO_SW_RESET 1
279#define CONFIG_SYS_GPIO_ZEUS_PE 12
280#define CONFIG_SYS_GPIO_LED_RED 22
281#define CONFIG_SYS_GPIO_LED_GREEN 23
Stefan Roese779e9752007-08-14 14:44:41 +0200282
283/* Time in milli-seconds */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284#define CONFIG_SYS_TIME_POST 5000
285#define CONFIG_SYS_TIME_FACTORY_RESET 10000
Stefan Roese779e9752007-08-14 14:44:41 +0200286
Stefan Roese3b3bff42007-08-14 16:36:29 +0200287#if defined(CONFIG_CMD_KGDB)
Stefan Roese779e9752007-08-14 14:44:41 +0200288#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
289#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
290#endif
291
Stefan Roeseb18410e2008-09-11 13:05:56 +0200292/*
293 * Pass open firmware flat tree
294 */
295#define CONFIG_OF_LIBFDT
296#define CONFIG_OF_BOARD_SETUP
297
Stefan Roese779e9752007-08-14 14:44:41 +0200298/* ENVIRONMENT VARS */
299
300#define CONFIG_PREBOOT "echo;echo Welcome to Bulletendpoints board v1.1;echo"
301#define CONFIG_IPADDR 192.168.1.10
302#define CONFIG_SERVERIP 192.168.1.100
303#define CONFIG_GATEWAYIP 192.168.1.100
304#define CONFIG_ETHADDR 50:00:00:00:06:00
305#define CONFIG_ETH1ADDR 50:00:00:00:06:01
306#if 0
307#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
308#else
309#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
310#endif
311
312#define CONFIG_EXTRA_ENV_SETTINGS \
313 "logversion=2\0" \
314 "hostname=zeus\0" \
315 "netdev=eth0\0" \
316 "ethact=ppc_4xx_eth0\0" \
317 "netmask=255.255.255.0\0" \
318 "ramdisk_size=50000\0" \
319 "nfsargs=setenv bootargs root=/dev/nfs rw" \
320 " nfsroot=${serverip}:${rootpath}\0" \
321 "ramargs=setenv bootargs root=/dev/ram rw" \
Detlev Zundele5084af2008-02-22 17:21:32 +0100322 " ramdisk_size=${ramdisk_size}\0" \
Stefan Roese779e9752007-08-14 14:44:41 +0200323 "addip=setenv bootargs ${bootargs} " \
324 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
325 ":${hostname}:${netdev}:off panic=1\0" \
326 "addtty=setenv bootargs ${bootargs} console=ttyS0," \
327 "${baudrate}\0" \
328 "net_nfs=tftp ${kernel_mem_addr} ${file_kernel};" \
329 "run nfsargs addip addtty;bootm\0" \
330 "net_ram=tftp ${kernel_mem_addr} ${file_kernel};" \
331 "tftp ${ramdisk_mem_addr} ${file_fs};" \
332 "run ramargs addip addtty;" \
333 "bootm ${kernel_mem_addr} ${ramdisk_mem_addr}\0" \
334 "rootpath=/target_fs/zeus\0" \
335 "kernel_fl_addr=ff000000\0" \
336 "kernel_mem_addr=200000\0" \
337 "ramdisk_fl_addr=ff300000\0" \
338 "ramdisk_mem_addr=4000000\0" \
339 "uboot_fl_addr=fffc0000\0" \
340 "uboot_mem_addr=100000\0" \
341 "file_uboot=/zeus/u-boot.bin\0" \
342 "tftp_uboot=tftp 100000 ${file_uboot}\0" \
343 "update_uboot=protect off fffc0000 ffffffff;" \
344 "era fffc0000 ffffffff;cp.b 100000 fffc0000 40000;" \
345 "protect on fffc0000 ffffffff\0" \
346 "upd_uboot=run tftp_uboot;run update_uboot\0" \
347 "file_kernel=/zeus/uImage_ba\0" \
348 "tftp_kernel=tftp 100000 ${file_kernel}\0" \
349 "update_kernel=protect off ff000000 ff17ffff;" \
350 "era ff000000 ff17ffff;cp.b 100000 ff000000 180000\0" \
351 "upd_kernel=run tftp_kernel;run update_kernel\0" \
352 "file_fs=/zeus/rootfs_ba.img\0" \
353 "tftp_fs=tftp 100000 ${file_fs}\0" \
354 "update_fs=protect off ff300000 ff87ffff;era ff300000 ff87ffff;"\
355 "cp.b 100000 ff300000 580000\0" \
356 "upd_fs=run tftp_fs;run update_fs\0" \
357 "bootcmd=chkreset;run ramargs addip addtty addmisc;" \
358 "bootm ${kernel_fl_addr} ${ramdisk_fl_addr}\0" \
359 ""
360
361#endif /* __CONFIG_H */