John Schmoller | bfe1881 | 2010-10-22 00:20:34 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2010 Extreme Engineering Solutions, Inc. |
| 3 | * Copyright 2007-2008 Freescale Semiconductor, Inc. |
| 4 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
John Schmoller | bfe1881 | 2010-10-22 00:20:34 -0500 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | /* |
| 9 | * xpedite550x board configuration file |
| 10 | */ |
| 11 | #ifndef __CONFIG_H |
| 12 | #define __CONFIG_H |
| 13 | |
| 14 | /* |
| 15 | * High Level Configuration Options |
| 16 | */ |
| 17 | #define CONFIG_BOOKE 1 /* BOOKE */ |
| 18 | #define CONFIG_E500 1 /* BOOKE e500 family */ |
| 19 | #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ |
| 20 | #define CONFIG_P2020 1 |
| 21 | #define CONFIG_XPEDITE550X 1 |
| 22 | #define CONFIG_SYS_BOARD_NAME "XPedite5500" |
| 23 | #define CONFIG_SYS_FORM_PMC_XMC 1 |
| 24 | #define CONFIG_PRPMC_PCI_ALIAS "pci0" /* Processor PMC interface on pci0 */ |
| 25 | #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ |
| 26 | |
| 27 | #ifndef CONFIG_SYS_TEXT_BASE |
| 28 | #define CONFIG_SYS_TEXT_BASE 0xfff80000 |
| 29 | #endif |
| 30 | |
| 31 | #define CONFIG_PCI 1 /* Enable PCI/PCIE */ |
| 32 | #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ |
| 33 | #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ |
| 34 | #define CONFIG_PCIE1 1 /* PCIE controler 1 (PEX8112 or XMC) */ |
| 35 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ |
Gabor Juhos | 842033e | 2013-05-30 07:06:12 +0000 | [diff] [blame] | 36 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
John Schmoller | bfe1881 | 2010-10-22 00:20:34 -0500 | [diff] [blame] | 37 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
| 38 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ |
| 39 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
| 40 | #define CONFIG_FSL_ELBC 1 |
| 41 | |
| 42 | /* |
| 43 | * Multicore config |
| 44 | */ |
| 45 | #define CONFIG_MP |
| 46 | #define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */ |
| 47 | #define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */ |
| 48 | |
| 49 | /* |
| 50 | * DDR config |
| 51 | */ |
| 52 | #define CONFIG_FSL_DDR3 |
| 53 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ |
| 54 | #define CONFIG_DDR_SPD |
| 55 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef |
Kumar Gala | c39f44d | 2011-01-31 22:18:47 -0600 | [diff] [blame] | 56 | #define SPD_EEPROM_ADDRESS 0x54 |
John Schmoller | bfe1881 | 2010-10-22 00:20:34 -0500 | [diff] [blame] | 57 | #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ |
| 58 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
| 59 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
| 60 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 |
| 61 | #define CONFIG_DDR_ECC |
| 62 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER |
| 63 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
| 64 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
| 65 | #define CONFIG_VERY_BIG_RAM |
| 66 | |
| 67 | #ifndef __ASSEMBLY__ |
| 68 | extern unsigned long get_board_sys_clk(unsigned long dummy); |
| 69 | extern unsigned long get_board_ddr_clk(unsigned long dummy); |
| 70 | #endif |
| 71 | |
| 72 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ |
| 73 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */ |
| 74 | |
| 75 | /* |
| 76 | * These can be toggled for performance analysis, otherwise use default. |
| 77 | */ |
| 78 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
| 79 | #define CONFIG_BTB /* toggle branch predition */ |
| 80 | #define CONFIG_ENABLE_36BIT_PHYS 1 |
| 81 | |
Timur Tabi | e46fedf | 2011-08-04 18:03:41 -0500 | [diff] [blame] | 82 | #define CONFIG_SYS_CCSRBAR 0xef000000 |
| 83 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR |
John Schmoller | bfe1881 | 2010-10-22 00:20:34 -0500 | [diff] [blame] | 84 | |
| 85 | /* |
| 86 | * Diagnostics |
| 87 | */ |
| 88 | #define CONFIG_SYS_ALT_MEMTEST |
| 89 | #define CONFIG_SYS_MEMTEST_START 0x10000000 |
| 90 | #define CONFIG_SYS_MEMTEST_END 0x20000000 |
| 91 | #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ |
| 92 | CONFIG_SYS_POST_I2C) |
| 93 | #define I2C_ADDR_LIST {CONFIG_SYS_I2C_EEPROM_ADDR, \ |
| 94 | CONFIG_SYS_I2C_LM75_ADDR, \ |
| 95 | CONFIG_SYS_I2C_LM90_ADDR, \ |
| 96 | CONFIG_SYS_I2C_PCA953X_ADDR0, \ |
| 97 | CONFIG_SYS_I2C_PCA953X_ADDR2, \ |
| 98 | CONFIG_SYS_I2C_PCA953X_ADDR3, \ |
| 99 | CONFIG_SYS_I2C_RTC_ADDR} |
| 100 | |
| 101 | /* |
| 102 | * Memory map |
| 103 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable |
| 104 | * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable |
| 105 | * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable |
| 106 | * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable |
| 107 | * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable |
| 108 | * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable |
| 109 | * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable |
| 110 | * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable |
| 111 | * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable |
| 112 | */ |
| 113 | |
| 114 | #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) |
| 115 | |
| 116 | /* |
| 117 | * NAND flash configuration |
| 118 | */ |
| 119 | #define CONFIG_SYS_NAND_BASE 0xef800000 |
| 120 | #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ |
| 121 | #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \ |
| 122 | CONFIG_SYS_NAND_BASE2} |
| 123 | #define CONFIG_SYS_MAX_NAND_DEVICE 2 |
| 124 | #define CONFIG_MTD_NAND_VERIFY_WRITE |
| 125 | #define CONFIG_SYS_NAND_QUIET_TEST /* 2nd NAND flash not always populated */ |
| 126 | #define CONFIG_NAND_FSL_ELBC |
| 127 | |
| 128 | /* |
| 129 | * NOR flash configuration |
| 130 | */ |
| 131 | #define CONFIG_SYS_FLASH_BASE 0xf8000000 |
| 132 | #define CONFIG_SYS_FLASH_BASE2 0xf0000000 |
| 133 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} |
| 134 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
| 135 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ |
| 136 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 137 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
| 138 | #define CONFIG_FLASH_CFI_DRIVER |
| 139 | #define CONFIG_SYS_FLASH_CFI |
| 140 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
| 141 | #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \ |
| 142 | {0xf7f40000, 0xc0000} } |
| 143 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
| 144 | |
| 145 | /* |
| 146 | * Chip select configuration |
| 147 | */ |
| 148 | /* NOR Flash 0 on CS0 */ |
| 149 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ |
| 150 | BR_PS_16 | \ |
| 151 | BR_V) |
| 152 | #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \ |
| 153 | OR_GPCM_CSNT | \ |
| 154 | OR_GPCM_XACS | \ |
| 155 | OR_GPCM_ACS_DIV2 | \ |
| 156 | OR_GPCM_SCY_8 | \ |
| 157 | OR_GPCM_TRLX | \ |
| 158 | OR_GPCM_EHTR | \ |
| 159 | OR_GPCM_EAD) |
| 160 | |
| 161 | /* NOR Flash 1 on CS1 */ |
| 162 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \ |
| 163 | BR_PS_16 | \ |
| 164 | BR_V) |
| 165 | #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM |
| 166 | |
| 167 | /* NAND flash on CS2 */ |
| 168 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \ |
| 169 | (2<<BR_DECC_SHIFT) | \ |
| 170 | BR_PS_8 | \ |
| 171 | BR_MS_FCM | \ |
| 172 | BR_V) |
| 173 | |
| 174 | /* NAND flash on CS2 */ |
| 175 | #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \ |
| 176 | OR_FCM_PGS | \ |
| 177 | OR_FCM_CSCT | \ |
| 178 | OR_FCM_CST | \ |
| 179 | OR_FCM_CHT | \ |
| 180 | OR_FCM_SCY_1 | \ |
| 181 | OR_FCM_TRLX | \ |
| 182 | OR_FCM_EHTR) |
| 183 | |
| 184 | /* NAND flash on CS3 */ |
| 185 | #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \ |
| 186 | (2<<BR_DECC_SHIFT) | \ |
| 187 | BR_PS_8 | \ |
| 188 | BR_MS_FCM | \ |
| 189 | BR_V) |
| 190 | #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM |
| 191 | |
| 192 | /* |
| 193 | * Use L1 as initial stack |
| 194 | */ |
| 195 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 196 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 |
Wolfgang Denk | 553f098 | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 197 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 |
John Schmoller | bfe1881 | 2010-10-22 00:20:34 -0500 | [diff] [blame] | 198 | |
Wolfgang Denk | 25ddd1f | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 199 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
John Schmoller | bfe1881 | 2010-10-22 00:20:34 -0500 | [diff] [blame] | 200 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| 201 | |
| 202 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ |
| 203 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ |
| 204 | |
| 205 | /* |
| 206 | * Serial Port |
| 207 | */ |
| 208 | #define CONFIG_CONS_INDEX 1 |
| 209 | #define CONFIG_SYS_NS16550 |
| 210 | #define CONFIG_SYS_NS16550_SERIAL |
| 211 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 212 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) |
| 213 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
| 214 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) |
| 215 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| 216 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
| 217 | #define CONFIG_BAUDRATE 115200 |
| 218 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
| 219 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
| 220 | |
| 221 | /* |
| 222 | * Use the HUSH parser |
| 223 | */ |
| 224 | #define CONFIG_SYS_HUSH_PARSER |
John Schmoller | bfe1881 | 2010-10-22 00:20:34 -0500 | [diff] [blame] | 225 | |
| 226 | /* |
| 227 | * Pass open firmware flat tree |
| 228 | */ |
| 229 | #define CONFIG_OF_LIBFDT 1 |
| 230 | #define CONFIG_OF_BOARD_SETUP 1 |
| 231 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
| 232 | #define CONFIG_FDT_FIXUP_PCI_IRQ 1 |
| 233 | |
| 234 | /* |
| 235 | * I2C |
| 236 | */ |
Heiko Schocher | 00f792e | 2012-10-24 13:48:22 +0200 | [diff] [blame] | 237 | #define CONFIG_SYS_I2C |
| 238 | #define CONFIG_SYS_I2C_FSL |
| 239 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 |
| 240 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
| 241 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 |
| 242 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 |
| 243 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F |
| 244 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 |
John Schmoller | bfe1881 | 2010-10-22 00:20:34 -0500 | [diff] [blame] | 245 | |
| 246 | /* I2C DS7505 temperature sensor */ |
| 247 | #define CONFIG_DTT_LM75 |
| 248 | #define CONFIG_DTT_SENSORS { 0 } |
| 249 | #define CONFIG_SYS_I2C_LM75_ADDR 0x48 |
| 250 | |
| 251 | /* I2C ADT7461 temperature sensor */ |
| 252 | #define CONFIG_SYS_I2C_LM90_ADDR 0x4C |
| 253 | |
| 254 | /* I2C EEPROM - AT24C128B */ |
| 255 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 |
| 256 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 |
| 257 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ |
| 258 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ |
| 259 | |
| 260 | /* I2C RTC */ |
| 261 | #define CONFIG_RTC_M41T11 1 |
| 262 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
| 263 | #define CONFIG_SYS_M41T11_BASE_YEAR 2000 |
| 264 | |
| 265 | /* GPIO */ |
| 266 | #define CONFIG_PCA953X |
| 267 | #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 |
| 268 | #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c |
| 269 | #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e |
| 270 | #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f |
| 271 | #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 |
| 272 | |
| 273 | /* |
| 274 | * GPIO pin definitions, PU = pulled high, PD = pulled low |
| 275 | */ |
| 276 | /* PCA9557 @ 0x18*/ |
| 277 | #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */ |
| 278 | #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select (1: RS-485, 0: RS-232) */ |
| 279 | #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */ |
| 280 | #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select (1: RS-485, 0: RS-232) */ |
| 281 | #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */ |
| 282 | #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Write protection (0: disabled, 1: enabled) */ |
| 283 | |
| 284 | /* PCA9557 @ 0x1e*/ |
| 285 | #define CONFIG_SYS_PCA953X_XMC_GA0 0x01 /* PU; */ |
| 286 | #define CONFIG_SYS_PCA953X_XMC_GA1 0x02 /* PU; */ |
| 287 | #define CONFIG_SYS_PCA953X_XMC_GA2 0x04 /* PU; */ |
| 288 | #define CONFIG_SYS_PCA953X_XMC_WAKE 0x10 /* PU; */ |
| 289 | #define CONFIG_SYS_PCA953X_XMC_BIST 0x20 /* Enable XMC BIST */ |
| 290 | #define CONFIG_SYS_PCA953X_PMC_EREADY 0x40 /* PU; PMC PCI eready */ |
| 291 | #define CONFIG_SYS_PCA953X_PMC_MONARCH 0x80 /* PMC monarch mode enable */ |
| 292 | |
| 293 | /* PCA9557 @ 0x1f */ |
| 294 | #define CONFIG_SYS_PCA953X_MC_GPIO0 0x01 /* PU; */ |
| 295 | #define CONFIG_SYS_PCA953X_MC_GPIO1 0x02 /* PU; */ |
| 296 | #define CONFIG_SYS_PCA953X_MC_GPIO2 0x04 /* PU; */ |
| 297 | #define CONFIG_SYS_PCA953X_MC_GPIO3 0x08 /* PU; */ |
| 298 | #define CONFIG_SYS_PCA953X_MC_GPIO4 0x10 /* PU; */ |
| 299 | #define CONFIG_SYS_PCA953X_MC_GPIO5 0x20 /* PU; */ |
| 300 | #define CONFIG_SYS_PCA953X_MC_GPIO6 0x40 /* PU; */ |
| 301 | #define CONFIG_SYS_PCA953X_MC_GPIO7 0x80 /* PU; */ |
| 302 | |
| 303 | /* |
| 304 | * General PCI |
| 305 | * Memory space is mapped 1-1, but I/O space must start from 0. |
| 306 | */ |
| 307 | |
| 308 | /* controller 1 - PEX8112 or XMC, depending on build option */ |
| 309 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 |
| 310 | #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS |
| 311 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */ |
| 312 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
| 313 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000 |
| 314 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ |
| 315 | |
| 316 | |
| 317 | /* |
| 318 | * Networking options |
| 319 | */ |
| 320 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
| 321 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
John Schmoller | bfe1881 | 2010-10-22 00:20:34 -0500 | [diff] [blame] | 322 | #define CONFIG_TSEC_TBI |
| 323 | #define CONFIG_MII 1 /* MII PHY management */ |
| 324 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ |
| 325 | #define CONFIG_ETHPRIME "eTSEC2" |
| 326 | |
Kumar Gala | 72c96a6 | 2010-12-01 22:55:54 -0600 | [diff] [blame] | 327 | /* |
| 328 | * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force |
| 329 | * 1000mbps SGMII link |
| 330 | */ |
| 331 | #define CONFIG_TSEC_TBICR_SETTINGS ( \ |
| 332 | TBICR_PHY_RESET \ |
| 333 | | TBICR_FULL_DUPLEX \ |
| 334 | | TBICR_SPEED1_SET \ |
| 335 | ) |
| 336 | |
John Schmoller | bfe1881 | 2010-10-22 00:20:34 -0500 | [diff] [blame] | 337 | #define CONFIG_TSEC1 1 |
| 338 | #define CONFIG_TSEC1_NAME "eTSEC1" |
| 339 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 340 | #define TSEC1_PHY_ADDR 1 |
| 341 | #define TSEC1_PHYIDX 0 |
| 342 | #define CONFIG_HAS_ETH0 |
| 343 | |
| 344 | #define CONFIG_TSEC2 1 |
| 345 | #define CONFIG_TSEC2_NAME "eTSEC2" |
| 346 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 347 | #define TSEC2_PHY_ADDR 2 |
| 348 | #define TSEC2_PHYIDX 0 |
| 349 | #define CONFIG_HAS_ETH1 |
| 350 | |
| 351 | #define CONFIG_TSEC3 1 |
| 352 | #define CONFIG_TSEC3_NAME "eTSEC3" |
| 353 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 354 | #define TSEC3_PHY_ADDR 3 |
| 355 | #define TSEC3_PHYIDX 0 |
| 356 | #define CONFIG_HAS_ETH2 |
| 357 | |
| 358 | /* |
| 359 | * USB |
| 360 | */ |
| 361 | #define CONFIG_USB_STORAGE |
| 362 | #define CONFIG_USB_EHCI |
| 363 | #define CONFIG_USB_EHCI_FSL |
| 364 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
| 365 | #define CONFIG_DOS_PARTITION |
| 366 | |
| 367 | /* |
| 368 | * Command configuration. |
| 369 | */ |
| 370 | #include <config_cmd_default.h> |
| 371 | |
| 372 | #define CONFIG_CMD_ASKENV |
| 373 | #define CONFIG_CMD_DATE |
| 374 | #define CONFIG_CMD_DHCP |
| 375 | #define CONFIG_CMD_DTT |
| 376 | #define CONFIG_CMD_EEPROM |
| 377 | #define CONFIG_CMD_ELF |
| 378 | #define CONFIG_CMD_FLASH |
| 379 | #define CONFIG_CMD_I2C |
| 380 | #define CONFIG_CMD_JFFS2 |
| 381 | #define CONFIG_CMD_MII |
| 382 | #define CONFIG_CMD_NAND |
| 383 | #define CONFIG_CMD_NET |
| 384 | #define CONFIG_CMD_PCA953X |
| 385 | #define CONFIG_CMD_PCA953X_INFO |
| 386 | #define CONFIG_CMD_PCI |
| 387 | #define CONFIG_CMD_PCI_ENUM |
| 388 | #define CONFIG_CMD_PING |
| 389 | #define CONFIG_CMD_REGINFO |
| 390 | #define CONFIG_CMD_SAVEENV |
| 391 | #define CONFIG_CMD_SNTP |
| 392 | #define CONFIG_CMD_USB |
| 393 | |
| 394 | /* |
| 395 | * Miscellaneous configurable options |
| 396 | */ |
| 397 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 398 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
| 399 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
| 400 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 401 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 402 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 403 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
| 404 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ |
| 405 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
| 406 | #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ |
| 407 | #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ |
| 408 | #define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ |
| 409 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ |
| 410 | #define CONFIG_PREBOOT /* enable preboot variable */ |
| 411 | #define CONFIG_FIT 1 |
| 412 | #define CONFIG_FIT_VERBOSE 1 |
| 413 | #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ |
| 414 | |
| 415 | /* |
| 416 | * For booting Linux, the board info and command line data |
| 417 | * have to be in the first 16 MB of memory, since this is |
| 418 | * the maximum mapped by the Linux kernel during initialization. |
| 419 | */ |
| 420 | #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ |
| 421 | #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ |
| 422 | |
| 423 | /* |
John Schmoller | bfe1881 | 2010-10-22 00:20:34 -0500 | [diff] [blame] | 424 | * Environment Configuration |
| 425 | */ |
| 426 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 427 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ |
| 428 | #define CONFIG_ENV_SIZE 0x8000 |
| 429 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) |
| 430 | |
| 431 | /* |
| 432 | * Flash memory map: |
| 433 | * fff80000 - ffffffff Pri U-Boot (512 KB) |
| 434 | * fff40000 - fff7ffff Pri U-Boot Environment (256 KB) |
| 435 | * fff00000 - fff3ffff Pri FDT (256KB) |
| 436 | * fef00000 - ffefffff Pri OS image (16MB) |
| 437 | * f8000000 - feefffff Pri OS Use/Filesystem (111MB) |
| 438 | * |
| 439 | * f7f80000 - f7ffffff Sec U-Boot (512 KB) |
| 440 | * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB) |
| 441 | * f7f00000 - f7f3ffff Sec FDT (256KB) |
| 442 | * f6f00000 - f7efffff Sec OS image (16MB) |
| 443 | * f0000000 - f6efffff Sec OS Use/Filesystem (111MB) |
| 444 | */ |
Marek Vasut | 5368c55 | 2012-09-23 17:41:24 +0200 | [diff] [blame] | 445 | #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000) |
| 446 | #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000) |
| 447 | #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000) |
| 448 | #define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000) |
| 449 | #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000) |
| 450 | #define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000) |
John Schmoller | bfe1881 | 2010-10-22 00:20:34 -0500 | [diff] [blame] | 451 | |
| 452 | #define CONFIG_PROG_UBOOT1 \ |
| 453 | "$download_cmd $loadaddr $ubootfile; " \ |
| 454 | "if test $? -eq 0; then " \ |
| 455 | "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ |
| 456 | "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ |
| 457 | "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ |
| 458 | "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ |
| 459 | "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ |
| 460 | "if test $? -ne 0; then " \ |
| 461 | "echo PROGRAM FAILED; " \ |
| 462 | "else; " \ |
| 463 | "echo PROGRAM SUCCEEDED; " \ |
| 464 | "fi; " \ |
| 465 | "else; " \ |
| 466 | "echo DOWNLOAD FAILED; " \ |
| 467 | "fi;" |
| 468 | |
| 469 | #define CONFIG_PROG_UBOOT2 \ |
| 470 | "$download_cmd $loadaddr $ubootfile; " \ |
| 471 | "if test $? -eq 0; then " \ |
| 472 | "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ |
| 473 | "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ |
| 474 | "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ |
| 475 | "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ |
| 476 | "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ |
| 477 | "if test $? -ne 0; then " \ |
| 478 | "echo PROGRAM FAILED; " \ |
| 479 | "else; " \ |
| 480 | "echo PROGRAM SUCCEEDED; " \ |
| 481 | "fi; " \ |
| 482 | "else; " \ |
| 483 | "echo DOWNLOAD FAILED; " \ |
| 484 | "fi;" |
| 485 | |
| 486 | #define CONFIG_BOOT_OS_NET \ |
| 487 | "$download_cmd $osaddr $osfile; " \ |
| 488 | "if test $? -eq 0; then " \ |
| 489 | "if test -n $fdtaddr; then " \ |
| 490 | "$download_cmd $fdtaddr $fdtfile; " \ |
| 491 | "if test $? -eq 0; then " \ |
| 492 | "bootm $osaddr - $fdtaddr; " \ |
| 493 | "else; " \ |
| 494 | "echo FDT DOWNLOAD FAILED; " \ |
| 495 | "fi; " \ |
| 496 | "else; " \ |
| 497 | "bootm $osaddr; " \ |
| 498 | "fi; " \ |
| 499 | "else; " \ |
| 500 | "echo OS DOWNLOAD FAILED; " \ |
| 501 | "fi;" |
| 502 | |
| 503 | #define CONFIG_PROG_OS1 \ |
| 504 | "$download_cmd $osaddr $osfile; " \ |
| 505 | "if test $? -eq 0; then " \ |
| 506 | "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ |
| 507 | "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ |
| 508 | "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ |
| 509 | "if test $? -ne 0; then " \ |
| 510 | "echo OS PROGRAM FAILED; " \ |
| 511 | "else; " \ |
| 512 | "echo OS PROGRAM SUCCEEDED; " \ |
| 513 | "fi; " \ |
| 514 | "else; " \ |
| 515 | "echo OS DOWNLOAD FAILED; " \ |
| 516 | "fi;" |
| 517 | |
| 518 | #define CONFIG_PROG_OS2 \ |
| 519 | "$download_cmd $osaddr $osfile; " \ |
| 520 | "if test $? -eq 0; then " \ |
| 521 | "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ |
| 522 | "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ |
| 523 | "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ |
| 524 | "if test $? -ne 0; then " \ |
| 525 | "echo OS PROGRAM FAILED; " \ |
| 526 | "else; " \ |
| 527 | "echo OS PROGRAM SUCCEEDED; " \ |
| 528 | "fi; " \ |
| 529 | "else; " \ |
| 530 | "echo OS DOWNLOAD FAILED; " \ |
| 531 | "fi;" |
| 532 | |
| 533 | #define CONFIG_PROG_FDT1 \ |
| 534 | "$download_cmd $fdtaddr $fdtfile; " \ |
| 535 | "if test $? -eq 0; then " \ |
| 536 | "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ |
| 537 | "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ |
| 538 | "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ |
| 539 | "if test $? -ne 0; then " \ |
| 540 | "echo FDT PROGRAM FAILED; " \ |
| 541 | "else; " \ |
| 542 | "echo FDT PROGRAM SUCCEEDED; " \ |
| 543 | "fi; " \ |
| 544 | "else; " \ |
| 545 | "echo FDT DOWNLOAD FAILED; " \ |
| 546 | "fi;" |
| 547 | |
| 548 | #define CONFIG_PROG_FDT2 \ |
| 549 | "$download_cmd $fdtaddr $fdtfile; " \ |
| 550 | "if test $? -eq 0; then " \ |
| 551 | "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ |
| 552 | "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ |
| 553 | "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ |
| 554 | "if test $? -ne 0; then " \ |
| 555 | "echo FDT PROGRAM FAILED; " \ |
| 556 | "else; " \ |
| 557 | "echo FDT PROGRAM SUCCEEDED; " \ |
| 558 | "fi; " \ |
| 559 | "else; " \ |
| 560 | "echo FDT DOWNLOAD FAILED; " \ |
| 561 | "fi;" |
| 562 | |
| 563 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 564 | "autoload=yes\0" \ |
| 565 | "download_cmd=tftp\0" \ |
| 566 | "console_args=console=ttyS0,115200\0" \ |
| 567 | "root_args=root=/dev/nfs rw\0" \ |
| 568 | "misc_args=ip=on\0" \ |
| 569 | "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ |
| 570 | "bootfile=/home/user/file\0" \ |
| 571 | "osfile=/home/user/board.uImage\0" \ |
| 572 | "fdtfile=/home/user/board.dtb\0" \ |
| 573 | "ubootfile=/home/user/u-boot.bin\0" \ |
| 574 | "fdtaddr=c00000\0" \ |
| 575 | "osaddr=0x1000000\0" \ |
| 576 | "loadaddr=0x1000000\0" \ |
| 577 | "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ |
| 578 | "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ |
| 579 | "prog_os1="CONFIG_PROG_OS1"\0" \ |
| 580 | "prog_os2="CONFIG_PROG_OS2"\0" \ |
| 581 | "prog_fdt1="CONFIG_PROG_FDT1"\0" \ |
| 582 | "prog_fdt2="CONFIG_PROG_FDT2"\0" \ |
| 583 | "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ |
| 584 | "bootcmd_flash1=run set_bootargs; " \ |
| 585 | "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ |
| 586 | "bootcmd_flash2=run set_bootargs; " \ |
| 587 | "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ |
| 588 | "bootcmd=run bootcmd_flash1\0" |
| 589 | #endif /* __CONFIG_H */ |