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Michael Jones84d7a012011-11-04 13:53:44 -04001/*
2 * MATRIX VISION GmbH mvBlueLYNX-X
3 *
4 * Derived from omap3_beagle.h:
5 * (C) Copyright 2006-2008
6 * Texas Instruments.
7 * Richard Woodruff <r-woodruff2@ti.com>
8 * Syed Mohammed Khasim <x0khasim@ti.com>
9 *
10 * Configuration settings for the TI OMAP3530 Beagle board.
11 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020012 * SPDX-License-Identifier: GPL-2.0+
Michael Jones84d7a012011-11-04 13:53:44 -040013 */
14
15#ifndef __CONFIG_H
16#define __CONFIG_H
17
18/*
19 * High Level Configuration Options
20 */
21#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
22#define CONFIG_OMAP 1 /* in a TI OMAP core */
23#define CONFIG_OMAP34XX 1 /* which is a 34XX */
Michael Jones84d7a012011-11-04 13:53:44 -040024#define CONFIG_MVBLX 1 /* working with mvBlueLYNX-X */
25#define CONFIG_MACH_TYPE MACH_TYPE_MVBLX
Marek Vasut308252a2012-07-21 05:02:23 +000026#define CONFIG_OMAP_GPIO
Michael Jones84d7a012011-11-04 13:53:44 -040027
28#define CONFIG_SDRC /* The chip has SDRC controller */
29
30#include <asm/arch/cpu.h> /* get chip and board defs */
31#include <asm/arch/omap3.h>
32
33/*
34 * Display CPU and Board information
35 */
36#define CONFIG_DISPLAY_CPUINFO 1
37#define CONFIG_DISPLAY_BOARDINFO 1
38
39/* Clock Defines */
40#define V_OSCK 26000000 /* Clock output from T2 */
41#define V_SCLK (V_OSCK >> 1)
42
Michael Jones84d7a012011-11-04 13:53:44 -040043#define CONFIG_MISC_INIT_R
44
45#define CONFIG_OF_LIBFDT 1
46
47#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
48#define CONFIG_SETUP_MEMORY_TAGS 1
49#define CONFIG_INITRD_TAG 1
50#define CONFIG_REVISION_TAG 1
51#define CONFIG_SERIAL_TAG 1
52
53/*
54 * Size of malloc() pool
55 */
56#define CONFIG_ENV_SIZE (2 << 10) /* 2 KiB */
57 /* Sector */
58#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
59
60/*
61 * Hardware drivers
62 */
63
64/*
65 * NS16550 Configuration
66 */
67#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
68
69#define CONFIG_SYS_NS16550
70#define CONFIG_SYS_NS16550_SERIAL
71#define CONFIG_SYS_NS16550_REG_SIZE (-4)
72#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
73
74/*
75 * select serial console configuration
76 */
Howard Gray661bb0f2013-02-07 23:53:35 +000077#define CONFIG_CONS_INDEX 1
78#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
79#define CONFIG_SERIAL1 1 /* UART1 */
Michael Jones84d7a012011-11-04 13:53:44 -040080
81#define CONFIG_BAUDRATE 115200
82#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
83 115200}
84#define CONFIG_GENERIC_MMC 1
85#define CONFIG_MMC 1
86#define CONFIG_OMAP_HSMMC 1
87#define CONFIG_DOS_PARTITION 1
88
Howard Gray661bb0f2013-02-07 23:53:35 +000089/* silent console by default */
90#define CONFIG_SYS_DEVICE_NULLDEV 1
91#define CONFIG_SILENT_CONSOLE 1
92
Michael Jones84d7a012011-11-04 13:53:44 -040093/* USB */
94#define CONFIG_MUSB_UDC 1
95#define CONFIG_USB_OMAP3 1
96#define CONFIG_TWL4030_USB 1
97
98/* USB device configuration */
99#define CONFIG_USB_DEVICE 1
100#define CONFIG_USB_TTY 1
101#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
102#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1
103#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1
104#define CONFIG_USBD_VENDORID 0x164c
105#define CONFIG_USBD_PRODUCTID_GSERIAL 0x0201
106#define CONFIG_USBD_PRODUCTID_CDCACM 0x0201
107#define CONFIG_USBD_MANUFACTURER "MATRIX VISION GmbH"
108#define CONFIG_USBD_PRODUCT_NAME "mvBlueLYNX-X"
109
110/* no FLASH available */
111#define CONFIG_SYS_NO_FLASH
112
113/* commands to include */
114#include <config_cmd_default.h>
115
116#define CONFIG_CMD_CACHE
117#define CONFIG_CMD_EXT2 /* EXT2 Support */
118#define CONFIG_CMD_FAT /* FAT support */
119#define CONFIG_CMD_I2C /* I2C serial bus support */
120#define CONFIG_CMD_MMC /* MMC support */
121#define CONFIG_CMD_EEPROM
122#define CONFIG_CMD_IMI /* iminfo */
123#undef CONFIG_CMD_IMLS /* List all found images */
124#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
125#define CONFIG_CMD_NFS /* NFS support */
126#define CONFIG_CMD_DHCP
127#define CONFIG_CMD_PING
128#define CONFIG_CMD_FPGA
129
130#define CONFIG_HARD_I2C 1
131#define CONFIG_SYS_I2C_SPEED 100000
132#define CONFIG_SYS_I2C_SLAVE 0
Michael Jones84d7a012011-11-04 13:53:44 -0400133#define CONFIG_DRIVER_OMAP34XX_I2C 1
134#define CONFIG_I2C_MULTI_BUS 1
135
136/*
137 * TWL4030
138 */
139#define CONFIG_TWL4030_POWER 1
140
141/* Environment information */
142#undef CONFIG_ENV_OVERWRITE /* disallow overwriting serial# and ethaddr */
Howard Gray661bb0f2013-02-07 23:53:35 +0000143#define CONFIG_BOOTDELAY 0
144#define CONFIG_ZERO_BOOTDELAY_CHECK
145#define CONFIG_AUTOBOOT_KEYED
146#define CONFIG_AUTOBOOT_STOP_STR "S"
Michael Jones84d7a012011-11-04 13:53:44 -0400147
148#define CONFIG_EXTRA_ENV_SETTINGS \
Howard Gray661bb0f2013-02-07 23:53:35 +0000149 "silent=true\0" \
Michael Jones84d7a012011-11-04 13:53:44 -0400150 "loadaddr=0x82000000\0" \
151 "usbtty=cdc_acm\0" \
Howard Gray661bb0f2013-02-07 23:53:35 +0000152 "console=ttyO0,115200n8\0" \
Michael Jones84d7a012011-11-04 13:53:44 -0400153 "mpurate=600\0" \
154 "vram=12M\0" \
155 "dvimode=1024x768-24@60\0" \
156 "defaultdisplay=dvi\0" \
Michael Jones71c4ae32013-02-07 23:53:36 +0000157 "loadfpga=if ext2load mmc ${mmcdev}:2 ${loadaddr} "\
158 "/lib/firmware/mvblx/${fpgafilename}; then " \
159 "fpga load 0 ${loadaddr} ${filesize}; " \
Michael Jones84d7a012011-11-04 13:53:44 -0400160 "fi;\0" \
161 "mmcdev=0\0" \
162 "mmcroot=/dev/mmcblk0p2 rw\0" \
163 "mmcrootfstype=ext3 rootwait\0" \
164 "mmcargs=setenv bootargs console=${console} " \
165 "mpurate=${mpurate} " \
166 "vram=${vram} " \
167 "omapfb.mode=dvi:${dvimode} " \
168 "omapfb.debug=y " \
169 "omapdss.def_disp=${defaultdisplay} " \
170 "root=${mmcroot} " \
171 "rootfstype=${mmcrootfstype} " \
Michael Jonesbb4d4642013-02-07 23:53:37 +0000172 "mvfw.fpgavers=${fpgavers} " \
Michael Jones84d7a012011-11-04 13:53:44 -0400173 "${cmdline_suffix}\0" \
174 "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
175 "importbootenv=echo Importing environment from mmc ...; " \
176 "env import -t $loadaddr $filesize\0" \
177 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
178 "mmcboot=echo Booting from mmc ...; " \
179 "run mmcargs; " \
180 "bootm ${loadaddr}\0" \
181 "mmcbootcmd= " \
182 "echo Trying mmc${mmcdev}; " \
183 "mmc dev ${mmcdev}; " \
184 "if mmc rescan; then " \
185 "setenv mmcroot /dev/mmcblk${mmcdev}p2 rw; " \
186 "echo SD/MMC found on device ${mmcdev};" \
187 "if run loadbootenv; then " \
188 "echo Loading boot environment from mmc${mmcdev}; " \
189 "run importbootenv; " \
190 "fi;" \
191 "run loadfpga; " \
192 "if test -n $uenvcmd; then " \
193 "echo Running uenvcmd ...;" \
194 "run uenvcmd;" \
195 "fi;" \
196 "if run loaduimage; then " \
197 "run mmcboot; " \
198 "fi;" \
199 "fi\0"
200
201#define CONFIG_BOOTCOMMAND \
202 "setenv mmcdev 1;" \
203 "run mmcbootcmd || " \
204 "setenv mmcdev 0;" \
205 "run mmcbootcmd"
206
207
208#define CONFIG_AUTO_COMPLETE 1
209/*
210 * Miscellaneous configurable options
211 */
212#define CONFIG_SYS_LONGHELP /* undef to save memory */
213#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
Michael Jones84d7a012011-11-04 13:53:44 -0400214#define CONFIG_SYS_PROMPT "mvblx # "
215#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
216/* Print Buffer Size */
217#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
218 sizeof(CONFIG_SYS_PROMPT) + 16)
219#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
220/* Boot Argument Buffer Size */
221#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
222
223#define CONFIG_SYS_ALT_MEMTEST 1 /* alternative memtest with looping */
224#define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest works on */
225#define CONFIG_SYS_MEMTEST_END (0x9dffffff) /* end = 448 MB */
226#define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */
227
228/* default load address */
229#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
230
231/*
232 * OMAP3 has 12 GP timers, they can be driven by the system clock
233 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
234 * This rate is divided by a local divisor.
235 */
236#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
237#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
238#define CONFIG_SYS_HZ 1000
239
240/*-----------------------------------------------------------------------
Michael Jones84d7a012011-11-04 13:53:44 -0400241 * Physical Memory Map
242 */
243#define CONFIG_NR_DRAM_BANKS 1
244#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
Michael Jones84d7a012011-11-04 13:53:44 -0400245#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
246
Michael Jones84d7a012011-11-04 13:53:44 -0400247#define CONFIG_ENV_IS_NOWHERE 1
248
249/*----------------------------------------------------------------------------
250 * Network Subsystem (SMSC9211 Ethernet from SMSC9118 family)
251 *----------------------------------------------------------------------------
252 */
253#if defined(CONFIG_CMD_NET)
Michael Jones84d7a012011-11-04 13:53:44 -0400254 #define CONFIG_SMC911X 1
255 #define CONFIG_SMC911X_32_BIT
256 #define CONFIG_SMC911X_BASE 0x2C000000
257#endif /* (CONFIG_CMD_NET) */
258
259#define CONFIG_FPGA_COUNT 1
Michal Simekb03b25c2013-05-01 18:05:56 +0200260#define CONFIG_FPGA
Michael Jones84d7a012011-11-04 13:53:44 -0400261#define CONFIG_FPGA_ALTERA
262#define CONFIG_FPGA_CYCLON2
263#define CONFIG_SYS_FPGA_PROG_FEEDBACK
264#define CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
265
266#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 0xA0>>1 */
267#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
268#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 2^4 = 16-byte pages */
269#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
270#define CONFIG_SYS_EEPROM_SIZE 256 /* Bytes */
271#define CONFIG_ID_EEPROM
272#define CONFIG_SYS_EEPROM_BUS_NUM 2
273
274#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
275#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
276#define CONFIG_SYS_INIT_RAM_SIZE 0x800
277#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
278 CONFIG_SYS_INIT_RAM_SIZE - \
279 GENERATED_GBL_DATA_SIZE)
280
281#define CONFIG_OMAP3_SPI
282
Aneesh V8e408522011-11-21 23:38:59 +0000283#define CONFIG_SYS_CACHELINE_SIZE 64
284
Michael Jones84d7a012011-11-04 13:53:44 -0400285#endif /* __CONFIG_H */