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wdenka562e1b2005-01-09 18:21:42 +00001/*
2 * Configuation settings for the Sentec Cobra Board.
3 *
4 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
wdenka562e1b2005-01-09 18:21:42 +00007 */
8
9/* ---
10 * Version: U-boot 1.0.0 - initial release for Sentec COBRA5272 board
11 * Date: 2004-03-29
12 * Author: Florian Schlote
13 *
14 * For a description of configuration options please refer also to the
15 * general u-boot-1.x.x/README file
16 * ---
17 */
18
19/* ---
20 * board/config.h - configuration options, board specific
21 * ---
22 */
23
24#ifndef _CONFIG_COBRA5272_H
25#define _CONFIG_COBRA5272_H
26
27/* ---
28 * Define processor
29 * possible values for Sentec board: only Coldfire M5272 processor supported
30 * (please do not change)
31 * ---
32 */
33
34#define CONFIG_MCF52x2 /* define processor family */
35#define CONFIG_M5272 /* define processor type */
36
37/* ---
38 * Defines processor clock - important for correct timings concerning serial
39 * interface etc.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020040 * CONFIG_SYS_HZ gives unit: 1000 -> 1 Hz ^= 1000 ms
wdenka562e1b2005-01-09 18:21:42 +000041 * ---
42 */
43
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020044#define CONFIG_SYS_HZ 1000
45#define CONFIG_SYS_CLK 66000000
46#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
wdenka562e1b2005-01-09 18:21:42 +000047
48/* ---
49 * Enable use of Ethernet
50 * ---
51 */
TsiChungLiew67064242007-08-15 19:41:06 -050052#define CONFIG_MCFFEC
wdenka562e1b2005-01-09 18:21:42 +000053
TsiChungLiew67064242007-08-15 19:41:06 -050054/* Enable Dma Timer */
55#define CONFIG_MCFTMR
wdenka562e1b2005-01-09 18:21:42 +000056
57/* ---
58 * Define baudrate for UART1 (console output, tftp, ...)
59 * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060 * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command
wdenka562e1b2005-01-09 18:21:42 +000061 * interface
62 * ---
63 */
64
TsiChungLiew67064242007-08-15 19:41:06 -050065#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#define CONFIG_SYS_UART_PORT (0)
wdenka562e1b2005-01-09 18:21:42 +000067#define CONFIG_BAUDRATE 19200
wdenka562e1b2005-01-09 18:21:42 +000068
69/* ---
70 * set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change
71 * timeout acc. to your needs
72 * #define CONFIG_WATCHDOG_TIMEOUT x , x is timeout in milliseconds, e. g. 10000
73 * for 10 sec
74 * ---
75 */
76
77#if 0
78#define CONFIG_WATCHDOG
79#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
80#endif
81
82/* ---
83 * CONFIG_MONITOR_IS_IN_RAM defines if u-boot is started from a different
84 * bootloader residing in flash ('chainloading'); if you want to use
85 * chainloading or want to compile a u-boot binary that can be loaded into
86 * RAM via BDM set
Wolfgang Denk53677ef2008-05-20 16:00:29 +020087 * "#if 0" to "#if 1"
wdenka562e1b2005-01-09 18:21:42 +000088 * You will need a first stage bootloader then, e. g. colilo or a working BDM
89 * cable (Background Debug Mode)
90 *
91 * Setting #if 0: u-boot will start from flash and relocate itself to RAM
92 *
Wolfgang Denk14d0a022010-10-07 21:51:12 +020093 * Please do not forget to modify the setting of CONFIG_SYS_TEXT_BASE
wdenka562e1b2005-01-09 18:21:42 +000094 * in board/cobra5272/config.mk accordingly (#if 0: 0xffe00000; #if 1: 0x20000)
95 *
96 * ---
97 */
98
99#if 0
100#define CONFIG_MONITOR_IS_IN_RAM /* monitor is started from a preloader */
101#endif
102
103/* ---
104 * Configuration for environment
105 * Environment is embedded in u-boot in the second sector of the flash
106 * ---
107 */
108
109#ifndef CONFIG_MONITOR_IS_IN_RAM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200110#define CONFIG_ENV_OFFSET 0x4000
111#define CONFIG_ENV_SECT_SIZE 0x2000
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200112#define CONFIG_ENV_IS_IN_FLASH 1
wdenka562e1b2005-01-09 18:21:42 +0000113#else
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200114#define CONFIG_ENV_ADDR 0xffe04000
115#define CONFIG_ENV_SECT_SIZE 0x2000
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200116#define CONFIG_ENV_IS_IN_FLASH 1
wdenka562e1b2005-01-09 18:21:42 +0000117#endif
118
Jon Loeliger37e4f242007-07-04 22:31:56 -0500119
120/*
Jon Loeliger80ff4f92007-07-10 09:29:01 -0500121 * BOOTP options
122 */
123#define CONFIG_BOOTP_BOOTFILESIZE
124#define CONFIG_BOOTP_BOOTPATH
125#define CONFIG_BOOTP_GATEWAY
126#define CONFIG_BOOTP_HOSTNAME
127
128
129/*
Jon Loeliger37e4f242007-07-04 22:31:56 -0500130 * Command line configuration.
wdenka562e1b2005-01-09 18:21:42 +0000131 */
Jon Loeliger37e4f242007-07-04 22:31:56 -0500132#include <config_cmd_default.h>
wdenka562e1b2005-01-09 18:21:42 +0000133
Jon Loeliger37e4f242007-07-04 22:31:56 -0500134#define CONFIG_CMD_PING
wdenka562e1b2005-01-09 18:21:42 +0000135
Jon Loeliger37e4f242007-07-04 22:31:56 -0500136#undef CONFIG_CMD_LOADS
137#undef CONFIG_CMD_LOADB
138#undef CONFIG_CMD_MII
139
TsiChungLiew67064242007-08-15 19:41:06 -0500140#ifdef CONFIG_MCFFEC
TsiChungLiew67064242007-08-15 19:41:06 -0500141# define CONFIG_MII 1
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -0500142# define CONFIG_MII_INIT 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143# define CONFIG_SYS_DISCOVER_PHY
144# define CONFIG_SYS_RX_ETH_BUFFER 8
145# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiew67064242007-08-15 19:41:06 -0500146
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147# define CONFIG_SYS_FEC0_PINMUX 0
148# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200149# define MCFFEC_TOUT_LOOP 50000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
151# ifndef CONFIG_SYS_DISCOVER_PHY
TsiChungLiew67064242007-08-15 19:41:06 -0500152# define FECDUPLEX FULL
153# define FECSPEED _100BASET
154# else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
156# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiew67064242007-08-15 19:41:06 -0500157# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158# endif /* CONFIG_SYS_DISCOVER_PHY */
TsiChungLiew67064242007-08-15 19:41:06 -0500159#endif
wdenka562e1b2005-01-09 18:21:42 +0000160
161/*
162 *-----------------------------------------------------------------------------
163 * Define user parameters that have to be customized most likely
164 *-----------------------------------------------------------------------------
165 */
166
167/*AUTOBOOT settings - booting images automatically by u-boot after power on*/
168
169#define CONFIG_BOOTDELAY 5 /* used for autoboot, delay in
170seconds u-boot will wait before starting defined (auto-)boot command, setting
171to -1 disables delay, setting to 0 will too prevent access to u-boot command
172interface: u-boot then has to reflashed */
173
174
175/* The following settings will be contained in the environment block ; if you
176want to use a neutral environment all those settings can be manually set in
177u-boot: 'set' command */
178
179#if 0
180
181#define CONFIG_BOOTCOMMAND "bootm 0xffe80000" /*Autoboto command, please
182enter a valid image address in flash */
183
184#define CONFIG_BOOTARGS " " /* default bootargs that are
185considered during boot */
186
187/* User network settings */
188
189#define CONFIG_ETHADDR 00:00:00:00:00:09 /* default ethernet MAC addr. */
190#define CONFIG_IPADDR 192.168.100.2 /* default board IP address */
191#define CONFIG_SERVERIP 192.168.100.1 /* default tftp server IP address */
192
193#endif
194
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_PROMPT "COBRA > " /* Layout of u-boot prompt*/
wdenka562e1b2005-01-09 18:21:42 +0000196
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_LOAD_ADDR 0x20000 /*Defines default RAM address
wdenka562e1b2005-01-09 18:21:42 +0000198from which user programs will be started */
199
200/*---*/
201
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenka562e1b2005-01-09 18:21:42 +0000203
Jon Loeliger37e4f242007-07-04 22:31:56 -0500204#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenka562e1b2005-01-09 18:21:42 +0000206#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenka562e1b2005-01-09 18:21:42 +0000208#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
210#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
211#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenka562e1b2005-01-09 18:21:42 +0000212
213/*
214 *-----------------------------------------------------------------------------
215 * End of user parameters to be customized
216 *-----------------------------------------------------------------------------
217 */
218
219/* ---
220 * Defines memory range for test
221 * ---
222 */
223
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_MEMTEST_START 0x400
225#define CONFIG_SYS_MEMTEST_END 0x380000
wdenka562e1b2005-01-09 18:21:42 +0000226
227/* ---
228 * Low Level Configuration Settings
229 * (address mappings, register initial values, etc.)
230 * You should know what you are doing if you make changes here.
231 * ---
232 */
233
234/* ---
235 * Base register address
236 * ---
237 */
238
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
wdenka562e1b2005-01-09 18:21:42 +0000240
241/* ---
242 * System Conf. Reg. & System Protection Reg.
243 * ---
244 */
245
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_SCR 0x0003
247#define CONFIG_SYS_SPR 0xffff
wdenka562e1b2005-01-09 18:21:42 +0000248
249/* ---
250 * Ethernet settings
251 * ---
252 */
253
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_DISCOVER_PHY
255#define CONFIG_SYS_ENET_BD_BASE 0x780000
wdenka562e1b2005-01-09 18:21:42 +0000256
257/*-----------------------------------------------------------------------
258 * Definitions for initial stack pointer and data area (in internal SRAM)
259 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200261#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200262#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenka562e1b2005-01-09 18:21:42 +0000264
265/*-----------------------------------------------------------------------
266 * Start addresses for the final memory configuration
267 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenka562e1b2005-01-09 18:21:42 +0000269 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_SDRAM_BASE 0x00000000
wdenka562e1b2005-01-09 18:21:42 +0000271
272/*
273 *-------------------------------------------------------------------------
274 * RAM SIZE (is defined above)
275 *-----------------------------------------------------------------------
276 */
277
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278/* #define CONFIG_SYS_SDRAM_SIZE 16 */
wdenka562e1b2005-01-09 18:21:42 +0000279
280/*
281 *-----------------------------------------------------------------------
282 */
283
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284#define CONFIG_SYS_FLASH_BASE 0xffe00000
wdenka562e1b2005-01-09 18:21:42 +0000285
286#ifdef CONFIG_MONITOR_IS_IN_RAM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#define CONFIG_SYS_MONITOR_BASE 0x20000
wdenka562e1b2005-01-09 18:21:42 +0000288#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
wdenka562e1b2005-01-09 18:21:42 +0000290#endif
291
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292#define CONFIG_SYS_MONITOR_LEN 0x20000
293#define CONFIG_SYS_MALLOC_LEN (256 << 10)
294#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
wdenka562e1b2005-01-09 18:21:42 +0000295
296/*
297 * For booting Linux, the board info and command line data
298 * have to be in the first 8 MB of memory, since this is
299 * the maximum mapped by the Linux kernel during initialization ??
300 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenka562e1b2005-01-09 18:21:42 +0000302
303/*-----------------------------------------------------------------------
304 * FLASH organization
305 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
307#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
308#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 /* flash timeout */
wdenka562e1b2005-01-09 18:21:42 +0000309
310/*-----------------------------------------------------------------------
311 * Cache Configuration
312 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_CACHELINE_SIZE 16
wdenka562e1b2005-01-09 18:21:42 +0000314
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600315#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200316 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600317#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200318 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600319#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
320#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
321 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
322 CF_ACR_EN | CF_ACR_SM_ALL)
323#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
324 CF_CACR_DISD | CF_CACR_INVI | \
325 CF_CACR_CEIB | CF_CACR_DCM | \
326 CF_CACR_EUSP)
327
wdenka562e1b2005-01-09 18:21:42 +0000328/*-----------------------------------------------------------------------
329 * Memory bank definitions
330 *
331 * Please refer also to Motorola Coldfire user manual - Chapter XXX
332 * <http://e-www.motorola.com/files/dsp/doc/ref_manual/MCF5272UM.pdf>
333 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_BR0_PRELIM 0xFFE00201
335#define CONFIG_SYS_OR0_PRELIM 0xFFE00014
wdenka562e1b2005-01-09 18:21:42 +0000336
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337#define CONFIG_SYS_BR1_PRELIM 0
338#define CONFIG_SYS_OR1_PRELIM 0
wdenka562e1b2005-01-09 18:21:42 +0000339
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_BR2_PRELIM 0
341#define CONFIG_SYS_OR2_PRELIM 0
wdenka562e1b2005-01-09 18:21:42 +0000342
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343#define CONFIG_SYS_BR3_PRELIM 0
344#define CONFIG_SYS_OR3_PRELIM 0
wdenka562e1b2005-01-09 18:21:42 +0000345
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346#define CONFIG_SYS_BR4_PRELIM 0
347#define CONFIG_SYS_OR4_PRELIM 0
wdenka562e1b2005-01-09 18:21:42 +0000348
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349#define CONFIG_SYS_BR5_PRELIM 0
350#define CONFIG_SYS_OR5_PRELIM 0
wdenka562e1b2005-01-09 18:21:42 +0000351
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352#define CONFIG_SYS_BR6_PRELIM 0
353#define CONFIG_SYS_OR6_PRELIM 0
wdenka562e1b2005-01-09 18:21:42 +0000354
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355#define CONFIG_SYS_BR7_PRELIM 0x00000701
356#define CONFIG_SYS_OR7_PRELIM 0xFF00007C
wdenka562e1b2005-01-09 18:21:42 +0000357
358/*-----------------------------------------------------------------------
359 * LED config
360 */
361#define LED_STAT_0 0xffff /*all LEDs off*/
362#define LED_STAT_1 0xfffe
363#define LED_STAT_2 0xfffd
364#define LED_STAT_3 0xfffb
365#define LED_STAT_4 0xfff7
366#define LED_STAT_5 0xffef
367#define LED_STAT_6 0xffdf
368#define LED_STAT_7 0xff00 /*all LEDs on*/
369
370/*-----------------------------------------------------------------------
371 * Port configuration (GPIO)
372 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200373#define CONFIG_SYS_PACNT 0x00000000 /* PortA control reg.: All pins are external
wdenka562e1b2005-01-09 18:21:42 +0000374GPIO*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375#define CONFIG_SYS_PADDR 0x00FF /* PortA direction reg.: PA7 to PA0 are outputs
wdenka562e1b2005-01-09 18:21:42 +0000376(1^=output, 0^=input) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200377#define CONFIG_SYS_PADAT LED_STAT_0 /* PortA value reg.: Turn all LED off */
378#define CONFIG_SYS_PBCNT 0x55554155 /* PortB control reg.: Ethernet/UART
wdenka562e1b2005-01-09 18:21:42 +0000379configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200380#define CONFIG_SYS_PBDDR 0x0000 /* PortB direction: All pins configured as inputs */
381#define CONFIG_SYS_PBDAT 0x0000 /* PortB value reg. */
382#define CONFIG_SYS_PDCNT 0x00000000 /* PortD control reg. */
wdenka562e1b2005-01-09 18:21:42 +0000383
384#endif /* _CONFIG_COBRA5272_H */