| Simon Glass | 3eafce0 | 2014-11-12 22:42:27 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Taken from the Coreboot file of the same name |
| 3 | * |
| 4 | * (C) Copyright 2014 Google, Inc |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0 |
| 7 | */ |
| 8 | |
| 9 | #ifndef _ASM_LAPIC_DEF_H |
| 10 | #define _ASM_LAPIC_DEF_H |
| 11 | |
| 12 | #define LAPIC_BASE_MSR 0x1B |
| 13 | #define LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR (1 << 8) |
| 14 | #define LAPIC_BASE_MSR_ENABLE (1 << 11) |
| 15 | #define LAPIC_BASE_MSR_ADDR_MASK 0xFFFFF000 |
| 16 | |
| 17 | #define LOCAL_APIC_ADDR 0xfee00000 |
| 18 | #define LAPIC_DEFAULT_BASE LOCAL_APIC_ADDR |
| 19 | |
| 20 | #define LAPIC_ID 0x020 |
| 21 | #define LAPIC_LVR 0x030 |
| 22 | #define LAPIC_TASKPRI 0x80 |
| 23 | #define LAPIC_TPRI_MASK 0xFF |
| 24 | #define LAPIC_ARBID 0x090 |
| 25 | #define LAPIC_RRR 0x0C0 |
| 26 | #define LAPIC_SVR 0x0f0 |
| 27 | #define LAPIC_SPIV 0x0f0 |
| 28 | #define LAPIC_SPIV_ENABLE 0x100 |
| 29 | #define LAPIC_ESR 0x280 |
| 30 | #define LAPIC_ESR_SEND_CS 0x00001 |
| 31 | #define LAPIC_ESR_RECV_CS 0x00002 |
| 32 | #define LAPIC_ESR_SEND_ACC 0x00004 |
| 33 | #define LAPIC_ESR_RECV_ACC 0x00008 |
| 34 | #define LAPIC_ESR_SENDILL 0x00020 |
| 35 | #define LAPIC_ESR_RECVILL 0x00040 |
| 36 | #define LAPIC_ESR_ILLREGA 0x00080 |
| 37 | #define LAPIC_ICR 0x300 |
| 38 | #define LAPIC_DEST_SELF 0x40000 |
| 39 | #define LAPIC_DEST_ALLINC 0x80000 |
| 40 | #define LAPIC_DEST_ALLBUT 0xC0000 |
| 41 | #define LAPIC_ICR_RR_MASK 0x30000 |
| 42 | #define LAPIC_ICR_RR_INVALID 0x00000 |
| 43 | #define LAPIC_ICR_RR_INPROG 0x10000 |
| 44 | #define LAPIC_ICR_RR_VALID 0x20000 |
| 45 | #define LAPIC_INT_LEVELTRIG 0x08000 |
| 46 | #define LAPIC_INT_ASSERT 0x04000 |
| 47 | #define LAPIC_ICR_BUSY 0x01000 |
| 48 | #define LAPIC_DEST_LOGICAL 0x00800 |
| 49 | #define LAPIC_DM_FIXED 0x00000 |
| 50 | #define LAPIC_DM_LOWEST 0x00100 |
| 51 | #define LAPIC_DM_SMI 0x00200 |
| 52 | #define LAPIC_DM_REMRD 0x00300 |
| 53 | #define LAPIC_DM_NMI 0x00400 |
| 54 | #define LAPIC_DM_INIT 0x00500 |
| 55 | #define LAPIC_DM_STARTUP 0x00600 |
| 56 | #define LAPIC_DM_EXTINT 0x00700 |
| 57 | #define LAPIC_VECTOR_MASK 0x000FF |
| 58 | #define LAPIC_ICR2 0x310 |
| 59 | #define GET_LAPIC_DEST_FIELD(x) (((x) >> 24) & 0xFF) |
| 60 | #define SET_LAPIC_DEST_FIELD(x) ((x) << 24) |
| 61 | #define LAPIC_LVTT 0x320 |
| 62 | #define LAPIC_LVTPC 0x340 |
| 63 | #define LAPIC_LVT0 0x350 |
| 64 | #define LAPIC_LVT_TIMER_BASE_MASK (0x3 << 18) |
| 65 | #define GET_LAPIC_TIMER_BASE(x) (((x) >> 18) & 0x3) |
| 66 | #define SET_LAPIC_TIMER_BASE(x) (((x) << 18)) |
| 67 | #define LAPIC_TIMER_BASE_CLKIN 0x0 |
| 68 | #define LAPIC_TIMER_BASE_TMBASE 0x1 |
| 69 | #define LAPIC_TIMER_BASE_DIV 0x2 |
| 70 | #define LAPIC_LVT_TIMER_PERIODIC (1 << 17) |
| 71 | #define LAPIC_LVT_MASKED (1 << 16) |
| 72 | #define LAPIC_LVT_LEVEL_TRIGGER (1 << 15) |
| 73 | #define LAPIC_LVT_REMOTE_IRR (1 << 14) |
| 74 | #define LAPIC_INPUT_POLARITY (1 << 13) |
| 75 | #define LAPIC_SEND_PENDING (1 << 12) |
| 76 | #define LAPIC_LVT_RESERVED_1 (1 << 11) |
| 77 | #define LAPIC_DELIVERY_MODE_MASK (7 << 8) |
| 78 | #define LAPIC_DELIVERY_MODE_FIXED (0 << 8) |
| 79 | #define LAPIC_DELIVERY_MODE_NMI (4 << 8) |
| 80 | #define LAPIC_DELIVERY_MODE_EXTINT (7 << 8) |
| 81 | #define GET_LAPIC_DELIVERY_MODE(x) (((x) >> 8) & 0x7) |
| 82 | #define SET_LAPIC_DELIVERY_MODE(x, y) (((x) & ~0x700)|((y) << 8)) |
| 83 | #define LAPIC_MODE_FIXED 0x0 |
| 84 | #define LAPIC_MODE_NMI 0x4 |
| 85 | #define LAPIC_MODE_EXINT 0x7 |
| 86 | #define LAPIC_LVT1 0x360 |
| 87 | #define LAPIC_LVTERR 0x370 |
| 88 | #define LAPIC_TMICT 0x380 |
| 89 | #define LAPIC_TMCCT 0x390 |
| 90 | #define LAPIC_TDCR 0x3E0 |
| 91 | #define LAPIC_TDR_DIV_TMBASE (1 << 2) |
| 92 | #define LAPIC_TDR_DIV_1 0xB |
| 93 | #define LAPIC_TDR_DIV_2 0x0 |
| 94 | #define LAPIC_TDR_DIV_4 0x1 |
| 95 | #define LAPIC_TDR_DIV_8 0x2 |
| 96 | #define LAPIC_TDR_DIV_16 0x3 |
| 97 | #define LAPIC_TDR_DIV_32 0x8 |
| 98 | #define LAPIC_TDR_DIV_64 0x9 |
| 99 | #define LAPIC_TDR_DIV_128 0xA |
| 100 | |
| 101 | #endif |