blob: df017dbd2e572028f2c98b66b065d1d2b5325b3a [file] [log] [blame]
Neil Armstrong78a08012018-09-05 15:56:52 +02001// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
4 */
5
6#include <dt-bindings/clock/axg-aoclkc.h>
7#include <dt-bindings/clock/axg-audio-clkc.h>
8#include <dt-bindings/clock/axg-clkc.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/gpio/meson-axg-gpio.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
14#include <dt-bindings/reset/amlogic,meson-axg-reset.h>
15
16/ {
17 compatible = "amlogic,meson-axg";
18
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
22
23 tdmif_a: audio-controller@0 {
24 compatible = "amlogic,axg-tdm-iface";
25 #sound-dai-cells = <0>;
26 sound-name-prefix = "TDM_A";
27 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
28 <&clkc_audio AUD_CLKID_MST_A_SCLK>,
29 <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
30 clock-names = "mclk", "sclk", "lrclk";
31 status = "disabled";
32 };
33
34 tdmif_b: audio-controller@1 {
35 compatible = "amlogic,axg-tdm-iface";
36 #sound-dai-cells = <0>;
37 sound-name-prefix = "TDM_B";
38 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
39 <&clkc_audio AUD_CLKID_MST_B_SCLK>,
40 <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
41 clock-names = "mclk", "sclk", "lrclk";
42 status = "disabled";
43 };
44
45 tdmif_c: audio-controller@2 {
46 compatible = "amlogic,axg-tdm-iface";
47 #sound-dai-cells = <0>;
48 sound-name-prefix = "TDM_C";
49 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
50 <&clkc_audio AUD_CLKID_MST_C_SCLK>,
51 <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
52 clock-names = "mclk", "sclk", "lrclk";
53 status = "disabled";
54 };
55
56 ao_alt_xtal: ao_alt_xtal-clk {
57 compatible = "fixed-clock";
58 clock-frequency = <32000000>;
59 clock-output-names = "ao_alt_xtal";
60 #clock-cells = <0>;
61 };
62
63 arm-pmu {
64 compatible = "arm,cortex-a53-pmu";
65 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
66 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
68 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
69 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
70 };
71
72 cpus {
73 #address-cells = <0x2>;
74 #size-cells = <0x0>;
75
76 cpu0: cpu@0 {
77 device_type = "cpu";
78 compatible = "arm,cortex-a53", "arm,armv8";
79 reg = <0x0 0x0>;
80 enable-method = "psci";
81 next-level-cache = <&l2>;
82 };
83
84 cpu1: cpu@1 {
85 device_type = "cpu";
86 compatible = "arm,cortex-a53", "arm,armv8";
87 reg = <0x0 0x1>;
88 enable-method = "psci";
89 next-level-cache = <&l2>;
90 };
91
92 cpu2: cpu@2 {
93 device_type = "cpu";
94 compatible = "arm,cortex-a53", "arm,armv8";
95 reg = <0x0 0x2>;
96 enable-method = "psci";
97 next-level-cache = <&l2>;
98 };
99
100 cpu3: cpu@3 {
101 device_type = "cpu";
102 compatible = "arm,cortex-a53", "arm,armv8";
103 reg = <0x0 0x3>;
104 enable-method = "psci";
105 next-level-cache = <&l2>;
106 };
107
108 l2: l2-cache0 {
109 compatible = "cache";
110 };
111 };
112
113 psci {
114 compatible = "arm,psci-1.0";
115 method = "smc";
116 };
117
118 reserved-memory {
119 #address-cells = <2>;
120 #size-cells = <2>;
121 ranges;
122
123 /* 16 MiB reserved for Hardware ROM Firmware */
124 hwrom_reserved: hwrom@0 {
125 reg = <0x0 0x0 0x0 0x1000000>;
126 no-map;
127 };
128
129 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
130 secmon_reserved: secmon@5000000 {
131 reg = <0x0 0x05000000 0x0 0x300000>;
132 no-map;
133 };
134 };
135
136 soc {
137 compatible = "simple-bus";
138 #address-cells = <2>;
139 #size-cells = <2>;
140 ranges;
141
142 ethmac: ethernet@ff3f0000 {
143 compatible = "amlogic,meson-axg-dwmac", "snps,dwmac";
144 reg = <0x0 0xff3f0000 0x0 0x10000
145 0x0 0xff634540 0x0 0x8>;
146 interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
147 interrupt-names = "macirq";
148 clocks = <&clkc CLKID_ETH>,
149 <&clkc CLKID_FCLK_DIV2>,
150 <&clkc CLKID_MPLL2>;
151 clock-names = "stmmaceth", "clkin0", "clkin1";
152 status = "disabled";
153 };
154
155 pdm: audio-controller@ff632000 {
156 compatible = "amlogic,axg-pdm";
157 reg = <0x0 0xff632000 0x0 0x34>;
158 #sound-dai-cells = <0>;
159 sound-name-prefix = "PDM";
160 clocks = <&clkc_audio AUD_CLKID_PDM>,
161 <&clkc_audio AUD_CLKID_PDM_DCLK>,
162 <&clkc_audio AUD_CLKID_PDM_SYSCLK>;
163 clock-names = "pclk", "dclk", "sysclk";
164 status = "disabled";
165 };
166
167 periphs: bus@ff634000 {
168 compatible = "simple-bus";
169 reg = <0x0 0xff634000 0x0 0x2000>;
170 #address-cells = <2>;
171 #size-cells = <2>;
172 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
173
174 hwrng: rng@18 {
175 compatible = "amlogic,meson-rng";
176 reg = <0x0 0x18 0x0 0x4>;
177 clocks = <&clkc CLKID_RNG0>;
178 clock-names = "core";
179 };
180
181 pinctrl_periphs: pinctrl@480 {
182 compatible = "amlogic,meson-axg-periphs-pinctrl";
183 #address-cells = <2>;
184 #size-cells = <2>;
185 ranges;
186
187 gpio: bank@480 {
188 reg = <0x0 0x00480 0x0 0x40>,
189 <0x0 0x004e8 0x0 0x14>,
190 <0x0 0x00520 0x0 0x14>,
191 <0x0 0x00430 0x0 0x3c>;
192 reg-names = "mux", "pull", "pull-enable", "gpio";
193 gpio-controller;
194 #gpio-cells = <2>;
195 gpio-ranges = <&pinctrl_periphs 0 0 86>;
196 };
197
198 i2c0_pins: i2c0 {
199 mux {
200 groups = "i2c0_sck",
201 "i2c0_sda";
202 function = "i2c0";
203 };
204 };
205
206 i2c1_x_pins: i2c1_x {
207 mux {
208 groups = "i2c1_sck_x",
209 "i2c1_sda_x";
210 function = "i2c1";
211 };
212 };
213
214 i2c1_z_pins: i2c1_z {
215 mux {
216 groups = "i2c1_sck_z",
217 "i2c1_sda_z";
218 function = "i2c1";
219 };
220 };
221
222 i2c2_a_pins: i2c2_a {
223 mux {
224 groups = "i2c2_sck_a",
225 "i2c2_sda_a";
226 function = "i2c2";
227 };
228 };
229
230 i2c2_x_pins: i2c2_x {
231 mux {
232 groups = "i2c2_sck_x",
233 "i2c2_sda_x";
234 function = "i2c2";
235 };
236 };
237
238 i2c3_a6_pins: i2c3_a6 {
239 mux {
240 groups = "i2c3_sda_a6",
241 "i2c3_sck_a7";
242 function = "i2c3";
243 };
244 };
245
246 i2c3_a12_pins: i2c3_a12 {
247 mux {
248 groups = "i2c3_sda_a12",
249 "i2c3_sck_a13";
250 function = "i2c3";
251 };
252 };
253
254 i2c3_a19_pins: i2c3_a19 {
255 mux {
256 groups = "i2c3_sda_a19",
257 "i2c3_sck_a20";
258 function = "i2c3";
259 };
260 };
261
262 emmc_pins: emmc {
263 mux {
264 groups = "emmc_nand_d0",
265 "emmc_nand_d1",
266 "emmc_nand_d2",
267 "emmc_nand_d3",
268 "emmc_nand_d4",
269 "emmc_nand_d5",
270 "emmc_nand_d6",
271 "emmc_nand_d7",
272 "emmc_clk",
273 "emmc_cmd",
274 "emmc_ds";
275 function = "emmc";
276 };
277 };
278
279 emmc_clk_gate_pins: emmc_clk_gate {
280 mux {
281 groups = "BOOT_8";
282 function = "gpio_periphs";
283 };
284 cfg-pull-down {
285 pins = "BOOT_8";
286 bias-pull-down;
287 };
288 };
289
290 eth_rgmii_x_pins: eth-x-rgmii {
291 mux {
292 groups = "eth_mdio_x",
293 "eth_mdc_x",
294 "eth_rgmii_rx_clk_x",
295 "eth_rx_dv_x",
296 "eth_rxd0_x",
297 "eth_rxd1_x",
298 "eth_rxd2_rgmii",
299 "eth_rxd3_rgmii",
300 "eth_rgmii_tx_clk",
301 "eth_txen_x",
302 "eth_txd0_x",
303 "eth_txd1_x",
304 "eth_txd2_rgmii",
305 "eth_txd3_rgmii";
306 function = "eth";
307 };
308 };
309
310 eth_rgmii_y_pins: eth-y-rgmii {
311 mux {
312 groups = "eth_mdio_y",
313 "eth_mdc_y",
314 "eth_rgmii_rx_clk_y",
315 "eth_rx_dv_y",
316 "eth_rxd0_y",
317 "eth_rxd1_y",
318 "eth_rxd2_rgmii",
319 "eth_rxd3_rgmii",
320 "eth_rgmii_tx_clk",
321 "eth_txen_y",
322 "eth_txd0_y",
323 "eth_txd1_y",
324 "eth_txd2_rgmii",
325 "eth_txd3_rgmii";
326 function = "eth";
327 };
328 };
329
330 eth_rmii_x_pins: eth-x-rmii {
331 mux {
332 groups = "eth_mdio_x",
333 "eth_mdc_x",
334 "eth_rgmii_rx_clk_x",
335 "eth_rx_dv_x",
336 "eth_rxd0_x",
337 "eth_rxd1_x",
338 "eth_txen_x",
339 "eth_txd0_x",
340 "eth_txd1_x";
341 function = "eth";
342 };
343 };
344
345 eth_rmii_y_pins: eth-y-rmii {
346 mux {
347 groups = "eth_mdio_y",
348 "eth_mdc_y",
349 "eth_rgmii_rx_clk_y",
350 "eth_rx_dv_y",
351 "eth_rxd0_y",
352 "eth_rxd1_y",
353 "eth_txen_y",
354 "eth_txd0_y",
355 "eth_txd1_y";
356 function = "eth";
357 };
358 };
359
360 mclk_b_pins: mclk_b {
361 mux {
362 groups = "mclk_b";
363 function = "mclk_b";
364 };
365 };
366
367 mclk_c_pins: mclk_c {
368 mux {
369 groups = "mclk_c";
370 function = "mclk_c";
371 };
372 };
373
374 pdm_dclk_a14_pins: pdm_dclk_a14 {
375 mux {
376 groups = "pdm_dclk_a14";
377 function = "pdm";
378 };
379 };
380
381 pdm_dclk_a19_pins: pdm_dclk_a19 {
382 mux {
383 groups = "pdm_dclk_a19";
384 function = "pdm";
385 };
386 };
387
388 pdm_din0_pins: pdm_din0 {
389 mux {
390 groups = "pdm_din0";
391 function = "pdm";
392 };
393 };
394
395 pdm_din1_pins: pdm_din1 {
396 mux {
397 groups = "pdm_din1";
398 function = "pdm";
399 };
400 };
401
402 pdm_din2_pins: pdm_din2 {
403 mux {
404 groups = "pdm_din2";
405 function = "pdm";
406 };
407 };
408
409 pdm_din3_pins: pdm_din3 {
410 mux {
411 groups = "pdm_din3";
412 function = "pdm";
413 };
414 };
415
416 pwm_a_a_pins: pwm_a_a {
417 mux {
418 groups = "pwm_a_a";
419 function = "pwm_a";
420 };
421 };
422
423 pwm_a_x18_pins: pwm_a_x18 {
424 mux {
425 groups = "pwm_a_x18";
426 function = "pwm_a";
427 };
428 };
429
430 pwm_a_x20_pins: pwm_a_x20 {
431 mux {
432 groups = "pwm_a_x20";
433 function = "pwm_a";
434 };
435 };
436
437 pwm_a_z_pins: pwm_a_z {
438 mux {
439 groups = "pwm_a_z";
440 function = "pwm_a";
441 };
442 };
443
444 pwm_b_a_pins: pwm_b_a {
445 mux {
446 groups = "pwm_b_a";
447 function = "pwm_b";
448 };
449 };
450
451 pwm_b_x_pins: pwm_b_x {
452 mux {
453 groups = "pwm_b_x";
454 function = "pwm_b";
455 };
456 };
457
458 pwm_b_z_pins: pwm_b_z {
459 mux {
460 groups = "pwm_b_z";
461 function = "pwm_b";
462 };
463 };
464
465 pwm_c_a_pins: pwm_c_a {
466 mux {
467 groups = "pwm_c_a";
468 function = "pwm_c";
469 };
470 };
471
472 pwm_c_x10_pins: pwm_c_x10 {
473 mux {
474 groups = "pwm_c_x10";
475 function = "pwm_c";
476 };
477 };
478
479 pwm_c_x17_pins: pwm_c_x17 {
480 mux {
481 groups = "pwm_c_x17";
482 function = "pwm_c";
483 };
484 };
485
486 pwm_d_x11_pins: pwm_d_x11 {
487 mux {
488 groups = "pwm_d_x11";
489 function = "pwm_d";
490 };
491 };
492
493 pwm_d_x16_pins: pwm_d_x16 {
494 mux {
495 groups = "pwm_d_x16";
496 function = "pwm_d";
497 };
498 };
499
500 sdio_pins: sdio {
501 mux {
502 groups = "sdio_d0",
503 "sdio_d1",
504 "sdio_d2",
505 "sdio_d3",
506 "sdio_cmd",
507 "sdio_clk";
508 function = "sdio";
509 };
510 };
511
512 sdio_clk_gate_pins: sdio_clk_gate {
513 mux {
514 groups = "GPIOX_4";
515 function = "gpio_periphs";
516 };
517 cfg-pull-down {
518 pins = "GPIOX_4";
519 bias-pull-down;
520 };
521 };
522
523 spdif_in_z_pins: spdif_in_z {
524 mux {
525 groups = "spdif_in_z";
526 function = "spdif_in";
527 };
528 };
529
530 spdif_in_a1_pins: spdif_in_a1 {
531 mux {
532 groups = "spdif_in_a1";
533 function = "spdif_in";
534 };
535 };
536
537 spdif_in_a7_pins: spdif_in_a7 {
538 mux {
539 groups = "spdif_in_a7";
540 function = "spdif_in";
541 };
542 };
543
544 spdif_in_a19_pins: spdif_in_a19 {
545 mux {
546 groups = "spdif_in_a19";
547 function = "spdif_in";
548 };
549 };
550
551 spdif_in_a20_pins: spdif_in_a20 {
552 mux {
553 groups = "spdif_in_a20";
554 function = "spdif_in";
555 };
556 };
557
558 spdif_out_a1_pins: spdif_out_a1 {
559 mux {
560 groups = "spdif_out_a1";
561 function = "spdif_out";
562 };
563 };
564
565 spdif_out_a11_pins: spdif_out_a11 {
566 mux {
567 groups = "spdif_out_a11";
568 function = "spdif_out";
569 };
570 };
571
572 spdif_out_a19_pins: spdif_out_a19 {
573 mux {
574 groups = "spdif_out_a19";
575 function = "spdif_out";
576 };
577 };
578
579 spdif_out_a20_pins: spdif_out_a20 {
580 mux {
581 groups = "spdif_out_a20";
582 function = "spdif_out";
583 };
584 };
585
586 spdif_out_z_pins: spdif_out_z {
587 mux {
588 groups = "spdif_out_z";
589 function = "spdif_out";
590 };
591 };
592
593 spi0_pins: spi0 {
594 mux {
595 groups = "spi0_miso",
596 "spi0_mosi",
597 "spi0_clk";
598 function = "spi0";
599 };
600 };
601
602 spi0_ss0_pins: spi0_ss0 {
603 mux {
604 groups = "spi0_ss0";
605 function = "spi0";
606 };
607 };
608
609 spi0_ss1_pins: spi0_ss1 {
610 mux {
611 groups = "spi0_ss1";
612 function = "spi0";
613 };
614 };
615
616 spi0_ss2_pins: spi0_ss2 {
617 mux {
618 groups = "spi0_ss2";
619 function = "spi0";
620 };
621 };
622
623 spi1_a_pins: spi1_a {
624 mux {
625 groups = "spi1_miso_a",
626 "spi1_mosi_a",
627 "spi1_clk_a";
628 function = "spi1";
629 };
630 };
631
632 spi1_ss0_a_pins: spi1_ss0_a {
633 mux {
634 groups = "spi1_ss0_a";
635 function = "spi1";
636 };
637 };
638
639 spi1_ss1_pins: spi1_ss1 {
640 mux {
641 groups = "spi1_ss1";
642 function = "spi1";
643 };
644 };
645
646 spi1_x_pins: spi1_x {
647 mux {
648 groups = "spi1_miso_x",
649 "spi1_mosi_x",
650 "spi1_clk_x";
651 function = "spi1";
652 };
653 };
654
655 spi1_ss0_x_pins: spi1_ss0_x {
656 mux {
657 groups = "spi1_ss0_x";
658 function = "spi1";
659 };
660 };
661
662 tdma_din0_pins: tdma_din0 {
663 mux {
664 groups = "tdma_din0";
665 function = "tdma";
666 };
667 };
668
669 tdma_dout0_x14_pins: tdma_dout0_x14 {
670 mux {
671 groups = "tdma_dout0_x14";
672 function = "tdma";
673 };
674 };
675
676 tdma_dout0_x15_pins: tdma_dout0_x15 {
677 mux {
678 groups = "tdma_dout0_x15";
679 function = "tdma";
680 };
681 };
682
683 tdma_dout1_pins: tdma_dout1 {
684 mux {
685 groups = "tdma_dout1";
686 function = "tdma";
687 };
688 };
689
690 tdma_din1_pins: tdma_din1 {
691 mux {
692 groups = "tdma_din1";
693 function = "tdma";
694 };
695 };
696
697 tdma_fs_pins: tdma_fs {
698 mux {
699 groups = "tdma_fs";
700 function = "tdma";
701 };
702 };
703
704 tdma_fs_slv_pins: tdma_fs_slv {
705 mux {
706 groups = "tdma_fs_slv";
707 function = "tdma";
708 };
709 };
710
711 tdma_sclk_pins: tdma_sclk {
712 mux {
713 groups = "tdma_sclk";
714 function = "tdma";
715 };
716 };
717
718 tdma_sclk_slv_pins: tdma_sclk_slv {
719 mux {
720 groups = "tdma_sclk_slv";
721 function = "tdma";
722 };
723 };
724
725 tdmb_din0_pins: tdmb_din0 {
726 mux {
727 groups = "tdmb_din0";
728 function = "tdmb";
729 };
730 };
731
732 tdmb_din1_pins: tdmb_din1 {
733 mux {
734 groups = "tdmb_din1";
735 function = "tdmb";
736 };
737 };
738
739 tdmb_din2_pins: tdmb_din2 {
740 mux {
741 groups = "tdmb_din2";
742 function = "tdmb";
743 };
744 };
745
746 tdmb_din3_pins: tdmb_din3 {
747 mux {
748 groups = "tdmb_din3";
749 function = "tdmb";
750 };
751 };
752
753 tdmb_dout0_pins: tdmb_dout0 {
754 mux {
755 groups = "tdmb_dout0";
756 function = "tdmb";
757 };
758 };
759
760 tdmb_dout1_pins: tdmb_dout1 {
761 mux {
762 groups = "tdmb_dout1";
763 function = "tdmb";
764 };
765 };
766
767 tdmb_dout2_pins: tdmb_dout2 {
768 mux {
769 groups = "tdmb_dout2";
770 function = "tdmb";
771 };
772 };
773
774 tdmb_dout3_pins: tdmb_dout3 {
775 mux {
776 groups = "tdmb_dout3";
777 function = "tdmb";
778 };
779 };
780
781 tdmb_fs_pins: tdmb_fs {
782 mux {
783 groups = "tdmb_fs";
784 function = "tdmb";
785 };
786 };
787
788 tdmb_fs_slv_pins: tdmb_fs_slv {
789 mux {
790 groups = "tdmb_fs_slv";
791 function = "tdmb";
792 };
793 };
794
795 tdmb_sclk_pins: tdmb_sclk {
796 mux {
797 groups = "tdmb_sclk";
798 function = "tdmb";
799 };
800 };
801
802 tdmb_sclk_slv_pins: tdmb_sclk_slv {
803 mux {
804 groups = "tdmb_sclk_slv";
805 function = "tdmb";
806 };
807 };
808
809 tdmc_fs_pins: tdmc_fs {
810 mux {
811 groups = "tdmc_fs";
812 function = "tdmc";
813 };
814 };
815
816 tdmc_fs_slv_pins: tdmc_fs_slv {
817 mux {
818 groups = "tdmc_fs_slv";
819 function = "tdmc";
820 };
821 };
822
823 tdmc_sclk_pins: tdmc_sclk {
824 mux {
825 groups = "tdmc_sclk";
826 function = "tdmc";
827 };
828 };
829
830 tdmc_sclk_slv_pins: tdmc_sclk_slv {
831 mux {
832 groups = "tdmc_sclk_slv";
833 function = "tdmc";
834 };
835 };
836
837 tdmc_din0_pins: tdmc_din0 {
838 mux {
839 groups = "tdmc_din0";
840 function = "tdmc";
841 };
842 };
843
844 tdmc_din1_pins: tdmc_din1 {
845 mux {
846 groups = "tdmc_din1";
847 function = "tdmc";
848 };
849 };
850
851 tdmc_din2_pins: tdmc_din2 {
852 mux {
853 groups = "tdmc_din2";
854 function = "tdmc";
855 };
856 };
857
858 tdmc_din3_pins: tdmc_din3 {
859 mux {
860 groups = "tdmc_din3";
861 function = "tdmc";
862 };
863 };
864
865 tdmc_dout0_pins: tdmc_dout0 {
866 mux {
867 groups = "tdmc_dout0";
868 function = "tdmc";
869 };
870 };
871
872 tdmc_dout1_pins: tdmc_dout1 {
873 mux {
874 groups = "tdmc_dout1";
875 function = "tdmc";
876 };
877 };
878
879 tdmc_dout2_pins: tdmc_dout2 {
880 mux {
881 groups = "tdmc_dout2";
882 function = "tdmc";
883 };
884 };
885
886 tdmc_dout3_pins: tdmc_dout3 {
887 mux {
888 groups = "tdmc_dout3";
889 function = "tdmc";
890 };
891 };
892
893 uart_a_pins: uart_a {
894 mux {
895 groups = "uart_tx_a",
896 "uart_rx_a";
897 function = "uart_a";
898 };
899 };
900
901 uart_a_cts_rts_pins: uart_a_cts_rts {
902 mux {
903 groups = "uart_cts_a",
904 "uart_rts_a";
905 function = "uart_a";
906 };
907 };
908
909 uart_b_x_pins: uart_b_x {
910 mux {
911 groups = "uart_tx_b_x",
912 "uart_rx_b_x";
913 function = "uart_b";
914 };
915 };
916
917 uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
918 mux {
919 groups = "uart_cts_b_x",
920 "uart_rts_b_x";
921 function = "uart_b";
922 };
923 };
924
925 uart_b_z_pins: uart_b_z {
926 mux {
927 groups = "uart_tx_b_z",
928 "uart_rx_b_z";
929 function = "uart_b";
930 };
931 };
932
933 uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
934 mux {
935 groups = "uart_cts_b_z",
936 "uart_rts_b_z";
937 function = "uart_b";
938 };
939 };
940
941 uart_ao_b_z_pins: uart_ao_b_z {
942 mux {
943 groups = "uart_ao_tx_b_z",
944 "uart_ao_rx_b_z";
945 function = "uart_ao_b_z";
946 };
947 };
948
949 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
950 mux {
951 groups = "uart_ao_cts_b_z",
952 "uart_ao_rts_b_z";
953 function = "uart_ao_b_z";
954 };
955 };
956 };
957 };
958
959 hiubus: bus@ff63c000 {
960 compatible = "simple-bus";
961 reg = <0x0 0xff63c000 0x0 0x1c00>;
962 #address-cells = <2>;
963 #size-cells = <2>;
964 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
965
966 sysctrl: system-controller@0 {
967 compatible = "amlogic,meson-axg-hhi-sysctrl",
968 "simple-mfd", "syscon";
969 reg = <0 0 0 0x400>;
970
971 clkc: clock-controller {
972 compatible = "amlogic,axg-clkc";
973 #clock-cells = <1>;
974 };
975 };
976 };
977
978 mailbox: mailbox@ff63dc00 {
979 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
980 reg = <0 0xff63dc00 0 0x400>;
981 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
982 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
983 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
984 #mbox-cells = <1>;
985 };
986
987 audio: bus@ff642000 {
988 compatible = "simple-bus";
989 reg = <0x0 0xff642000 0x0 0x2000>;
990 #address-cells = <2>;
991 #size-cells = <2>;
992 ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
993
994 clkc_audio: clock-controller@0 {
995 compatible = "amlogic,axg-audio-clkc";
996 reg = <0x0 0x0 0x0 0xb4>;
997 #clock-cells = <1>;
998
999 clocks = <&clkc CLKID_AUDIO>,
1000 <&clkc CLKID_MPLL0>,
1001 <&clkc CLKID_MPLL1>,
1002 <&clkc CLKID_MPLL2>,
1003 <&clkc CLKID_MPLL3>,
1004 <&clkc CLKID_HIFI_PLL>,
1005 <&clkc CLKID_FCLK_DIV3>,
1006 <&clkc CLKID_FCLK_DIV4>,
1007 <&clkc CLKID_GP0_PLL>;
1008 clock-names = "pclk",
1009 "mst_in0",
1010 "mst_in1",
1011 "mst_in2",
1012 "mst_in3",
1013 "mst_in4",
1014 "mst_in5",
1015 "mst_in6",
1016 "mst_in7";
1017
1018 resets = <&reset RESET_AUDIO>;
1019 };
1020
1021 toddr_a: audio-controller@100 {
1022 compatible = "amlogic,axg-toddr";
1023 reg = <0x0 0x100 0x0 0x1c>;
1024 #sound-dai-cells = <0>;
1025 sound-name-prefix = "TODDR_A";
1026 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
1027 clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
1028 resets = <&arb AXG_ARB_TODDR_A>;
1029 status = "disabled";
1030 };
1031
1032 toddr_b: audio-controller@140 {
1033 compatible = "amlogic,axg-toddr";
1034 reg = <0x0 0x140 0x0 0x1c>;
1035 #sound-dai-cells = <0>;
1036 sound-name-prefix = "TODDR_B";
1037 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
1038 clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
1039 resets = <&arb AXG_ARB_TODDR_B>;
1040 status = "disabled";
1041 };
1042
1043 toddr_c: audio-controller@180 {
1044 compatible = "amlogic,axg-toddr";
1045 reg = <0x0 0x180 0x0 0x1c>;
1046 #sound-dai-cells = <0>;
1047 sound-name-prefix = "TODDR_C";
1048 interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
1049 clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
1050 resets = <&arb AXG_ARB_TODDR_C>;
1051 status = "disabled";
1052 };
1053
1054 frddr_a: audio-controller@1c0 {
1055 compatible = "amlogic,axg-frddr";
1056 reg = <0x0 0x1c0 0x0 0x1c>;
1057 #sound-dai-cells = <0>;
1058 sound-name-prefix = "FRDDR_A";
1059 interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
1060 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
1061 resets = <&arb AXG_ARB_FRDDR_A>;
1062 status = "disabled";
1063 };
1064
1065 frddr_b: audio-controller@200 {
1066 compatible = "amlogic,axg-frddr";
1067 reg = <0x0 0x200 0x0 0x1c>;
1068 #sound-dai-cells = <0>;
1069 sound-name-prefix = "FRDDR_B";
1070 interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
1071 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
1072 resets = <&arb AXG_ARB_FRDDR_B>;
1073 status = "disabled";
1074 };
1075
1076 frddr_c: audio-controller@240 {
1077 compatible = "amlogic,axg-frddr";
1078 reg = <0x0 0x240 0x0 0x1c>;
1079 #sound-dai-cells = <0>;
1080 sound-name-prefix = "FRDDR_C";
1081 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
1082 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
1083 resets = <&arb AXG_ARB_FRDDR_C>;
1084 status = "disabled";
1085 };
1086
1087 arb: reset-controller@280 {
1088 compatible = "amlogic,meson-axg-audio-arb";
1089 reg = <0x0 0x280 0x0 0x4>;
1090 #reset-cells = <1>;
1091 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
1092 };
1093
1094 tdmin_a: audio-controller@300 {
1095 compatible = "amlogic,axg-tdmin";
1096 reg = <0x0 0x300 0x0 0x40>;
1097 sound-name-prefix = "TDMIN_A";
1098 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
1099 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
1100 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
1101 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
1102 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
1103 clock-names = "pclk", "sclk", "sclk_sel",
1104 "lrclk", "lrclk_sel";
1105 status = "disabled";
1106 };
1107
1108 tdmin_b: audio-controller@340 {
1109 compatible = "amlogic,axg-tdmin";
1110 reg = <0x0 0x340 0x0 0x40>;
1111 sound-name-prefix = "TDMIN_B";
1112 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
1113 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
1114 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
1115 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
1116 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
1117 clock-names = "pclk", "sclk", "sclk_sel",
1118 "lrclk", "lrclk_sel";
1119 status = "disabled";
1120 };
1121
1122 tdmin_c: audio-controller@380 {
1123 compatible = "amlogic,axg-tdmin";
1124 reg = <0x0 0x380 0x0 0x40>;
1125 sound-name-prefix = "TDMIN_C";
1126 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
1127 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
1128 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
1129 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
1130 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
1131 clock-names = "pclk", "sclk", "sclk_sel",
1132 "lrclk", "lrclk_sel";
1133 status = "disabled";
1134 };
1135
1136 tdmin_lb: audio-controller@3c0 {
1137 compatible = "amlogic,axg-tdmin";
1138 reg = <0x0 0x3c0 0x0 0x40>;
1139 sound-name-prefix = "TDMIN_LB";
1140 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
1141 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
1142 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
1143 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
1144 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
1145 clock-names = "pclk", "sclk", "sclk_sel",
1146 "lrclk", "lrclk_sel";
1147 status = "disabled";
1148 };
1149
1150 spdifout: audio-controller@480 {
1151 compatible = "amlogic,axg-spdifout";
1152 reg = <0x0 0x480 0x0 0x50>;
1153 #sound-dai-cells = <0>;
1154 sound-name-prefix = "SPDIFOUT";
1155 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
1156 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
1157 clock-names = "pclk", "mclk";
1158 status = "disabled";
1159 };
1160
1161 tdmout_a: audio-controller@500 {
1162 compatible = "amlogic,axg-tdmout";
1163 reg = <0x0 0x500 0x0 0x40>;
1164 sound-name-prefix = "TDMOUT_A";
1165 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
1166 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
1167 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
1168 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
1169 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
1170 clock-names = "pclk", "sclk", "sclk_sel",
1171 "lrclk", "lrclk_sel";
1172 status = "disabled";
1173 };
1174
1175 tdmout_b: audio-controller@540 {
1176 compatible = "amlogic,axg-tdmout";
1177 reg = <0x0 0x540 0x0 0x40>;
1178 sound-name-prefix = "TDMOUT_B";
1179 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
1180 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
1181 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
1182 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
1183 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
1184 clock-names = "pclk", "sclk", "sclk_sel",
1185 "lrclk", "lrclk_sel";
1186 status = "disabled";
1187 };
1188
1189 tdmout_c: audio-controller@580 {
1190 compatible = "amlogic,axg-tdmout";
1191 reg = <0x0 0x580 0x0 0x40>;
1192 sound-name-prefix = "TDMOUT_C";
1193 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
1194 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
1195 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
1196 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
1197 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
1198 clock-names = "pclk", "sclk", "sclk_sel",
1199 "lrclk", "lrclk_sel";
1200 status = "disabled";
1201 };
1202 };
1203
1204 aobus: bus@ff800000 {
1205 compatible = "simple-bus";
1206 reg = <0x0 0xff800000 0x0 0x100000>;
1207 #address-cells = <2>;
1208 #size-cells = <2>;
1209 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1210
1211 sysctrl_AO: sys-ctrl@0 {
1212 compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon";
1213 reg = <0x0 0x0 0x0 0x100>;
1214
1215 clkc_AO: clock-controller {
1216 compatible = "amlogic,meson-axg-aoclkc";
1217 #clock-cells = <1>;
1218 #reset-cells = <1>;
1219 };
1220 };
1221
1222 pinctrl_aobus: pinctrl@14 {
1223 compatible = "amlogic,meson-axg-aobus-pinctrl";
1224 #address-cells = <2>;
1225 #size-cells = <2>;
1226 ranges;
1227
1228 gpio_ao: bank@14 {
1229 reg = <0x0 0x00014 0x0 0x8>,
1230 <0x0 0x0002c 0x0 0x4>,
1231 <0x0 0x00024 0x0 0x8>;
1232 reg-names = "mux", "pull", "gpio";
1233 gpio-controller;
1234 #gpio-cells = <2>;
1235 gpio-ranges = <&pinctrl_aobus 0 0 15>;
1236 };
1237
1238 i2c_ao_sck_4_pins: i2c_ao_sck_4 {
1239 mux {
1240 groups = "i2c_ao_sck_4";
1241 function = "i2c_ao";
1242 };
1243 };
1244
1245 i2c_ao_sck_8_pins: i2c_ao_sck_8 {
1246 mux {
1247 groups = "i2c_ao_sck_8";
1248 function = "i2c_ao";
1249 };
1250 };
1251
1252 i2c_ao_sck_10_pins: i2c_ao_sck_10 {
1253 mux {
1254 groups = "i2c_ao_sck_10";
1255 function = "i2c_ao";
1256 };
1257 };
1258
1259 i2c_ao_sda_5_pins: i2c_ao_sda_5 {
1260 mux {
1261 groups = "i2c_ao_sda_5";
1262 function = "i2c_ao";
1263 };
1264 };
1265
1266 i2c_ao_sda_9_pins: i2c_ao_sda_9 {
1267 mux {
1268 groups = "i2c_ao_sda_9";
1269 function = "i2c_ao";
1270 };
1271 };
1272
1273 i2c_ao_sda_11_pins: i2c_ao_sda_11 {
1274 mux {
1275 groups = "i2c_ao_sda_11";
1276 function = "i2c_ao";
1277 };
1278 };
1279
1280 remote_input_ao_pins: remote_input_ao {
1281 mux {
1282 groups = "remote_input_ao";
1283 function = "remote_input_ao";
1284 };
1285 };
1286
1287 uart_ao_a_pins: uart_ao_a {
1288 mux {
1289 groups = "uart_ao_tx_a",
1290 "uart_ao_rx_a";
1291 function = "uart_ao_a";
1292 };
1293 };
1294
1295 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
1296 mux {
1297 groups = "uart_ao_cts_a",
1298 "uart_ao_rts_a";
1299 function = "uart_ao_a";
1300 };
1301 };
1302
1303 uart_ao_b_pins: uart_ao_b {
1304 mux {
1305 groups = "uart_ao_tx_b",
1306 "uart_ao_rx_b";
1307 function = "uart_ao_b";
1308 };
1309 };
1310
1311 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
1312 mux {
1313 groups = "uart_ao_cts_b",
1314 "uart_ao_rts_b";
1315 function = "uart_ao_b";
1316 };
1317 };
1318 };
1319
1320 sec_AO: ao-secure@140 {
1321 compatible = "amlogic,meson-gx-ao-secure", "syscon";
1322 reg = <0x0 0x140 0x0 0x140>;
1323 amlogic,has-chip-id;
1324 };
1325
1326 pwm_AO_cd: pwm@2000 {
1327 compatible = "amlogic,meson-axg-ao-pwm";
1328 reg = <0x0 0x02000 0x0 0x20>;
1329 #pwm-cells = <3>;
1330 status = "disabled";
1331 };
1332
1333 uart_AO: serial@3000 {
1334 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1335 reg = <0x0 0x3000 0x0 0x18>;
1336 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1337 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
1338 clock-names = "xtal", "pclk", "baud";
1339 status = "disabled";
1340 };
1341
1342 uart_AO_B: serial@4000 {
1343 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1344 reg = <0x0 0x4000 0x0 0x18>;
1345 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1346 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
1347 clock-names = "xtal", "pclk", "baud";
1348 status = "disabled";
1349 };
1350
1351 i2c_AO: i2c@5000 {
1352 compatible = "amlogic,meson-axg-i2c";
1353 reg = <0x0 0x05000 0x0 0x20>;
1354 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1355 clocks = <&clkc CLKID_AO_I2C>;
1356 #address-cells = <1>;
1357 #size-cells = <0>;
1358 status = "disabled";
1359 };
1360
1361 pwm_AO_ab: pwm@7000 {
1362 compatible = "amlogic,meson-axg-ao-pwm";
1363 reg = <0x0 0x07000 0x0 0x20>;
1364 #pwm-cells = <3>;
1365 status = "disabled";
1366 };
1367
1368 ir: ir@8000 {
1369 compatible = "amlogic,meson-gxbb-ir";
1370 reg = <0x0 0x8000 0x0 0x20>;
1371 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1372 status = "disabled";
1373 };
1374
1375 saradc: adc@9000 {
1376 compatible = "amlogic,meson-axg-saradc",
1377 "amlogic,meson-saradc";
1378 reg = <0x0 0x9000 0x0 0x38>;
1379 #io-channel-cells = <1>;
1380 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
1381 clocks = <&xtal>,
1382 <&clkc_AO CLKID_AO_SAR_ADC>,
1383 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
1384 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
1385 clock-names = "clkin", "core", "adc_clk", "adc_sel";
1386 status = "disabled";
1387 };
1388 };
1389
1390 gic: interrupt-controller@ffc01000 {
1391 compatible = "arm,gic-400";
1392 reg = <0x0 0xffc01000 0 0x1000>,
1393 <0x0 0xffc02000 0 0x2000>,
1394 <0x0 0xffc04000 0 0x2000>,
1395 <0x0 0xffc06000 0 0x2000>;
1396 interrupt-controller;
1397 interrupts = <GIC_PPI 9
1398 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1399 #interrupt-cells = <3>;
1400 #address-cells = <0>;
1401 };
1402
1403 cbus: bus@ffd00000 {
1404 compatible = "simple-bus";
1405 reg = <0x0 0xffd00000 0x0 0x25000>;
1406 #address-cells = <2>;
1407 #size-cells = <2>;
1408 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
1409
1410 reset: reset-controller@1004 {
1411 compatible = "amlogic,meson-axg-reset";
1412 reg = <0x0 0x01004 0x0 0x9c>;
1413 #reset-cells = <1>;
1414 };
1415
1416 gpio_intc: interrupt-controller@f080 {
1417 compatible = "amlogic,meson-gpio-intc";
1418 reg = <0x0 0xf080 0x0 0x10>;
1419 interrupt-controller;
1420 #interrupt-cells = <2>;
1421 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
1422 status = "disabled";
1423 };
1424
1425 pwm_ab: pwm@1b000 {
1426 compatible = "amlogic,meson-axg-ee-pwm";
1427 reg = <0x0 0x1b000 0x0 0x20>;
1428 #pwm-cells = <3>;
1429 status = "disabled";
1430 };
1431
1432 pwm_cd: pwm@1a000 {
1433 compatible = "amlogic,meson-axg-ee-pwm";
1434 reg = <0x0 0x1a000 0x0 0x20>;
1435 #pwm-cells = <3>;
1436 status = "disabled";
1437 };
1438
1439 spicc0: spi@13000 {
1440 compatible = "amlogic,meson-axg-spicc";
1441 reg = <0x0 0x13000 0x0 0x3c>;
1442 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1443 clocks = <&clkc CLKID_SPICC0>;
1444 clock-names = "core";
1445 #address-cells = <1>;
1446 #size-cells = <0>;
1447 status = "disabled";
1448 };
1449
1450 spicc1: spi@15000 {
1451 compatible = "amlogic,meson-axg-spicc";
1452 reg = <0x0 0x15000 0x0 0x3c>;
1453 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1454 clocks = <&clkc CLKID_SPICC1>;
1455 clock-names = "core";
1456 #address-cells = <1>;
1457 #size-cells = <0>;
1458 status = "disabled";
1459 };
1460
1461 i2c3: i2c@1c000 {
1462 compatible = "amlogic,meson-axg-i2c";
1463 reg = <0x0 0x1c000 0x0 0x20>;
1464 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
1465 clocks = <&clkc CLKID_I2C>;
1466 #address-cells = <1>;
1467 #size-cells = <0>;
1468 status = "disabled";
1469 };
1470
1471 i2c2: i2c@1d000 {
1472 compatible = "amlogic,meson-axg-i2c";
1473 reg = <0x0 0x1d000 0x0 0x20>;
1474 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
1475 clocks = <&clkc CLKID_I2C>;
1476 #address-cells = <1>;
1477 #size-cells = <0>;
1478 status = "disabled";
1479 };
1480
1481 i2c1: i2c@1e000 {
1482 compatible = "amlogic,meson-axg-i2c";
1483 reg = <0x0 0x1e000 0x0 0x20>;
1484 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
1485 clocks = <&clkc CLKID_I2C>;
1486 #address-cells = <1>;
1487 #size-cells = <0>;
1488 status = "disabled";
1489 };
1490
1491 i2c0: i2c@1f000 {
1492 compatible = "amlogic,meson-axg-i2c";
1493 reg = <0x0 0x1f000 0x0 0x20>;
1494 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
1495 clocks = <&clkc CLKID_I2C>;
1496 #address-cells = <1>;
1497 #size-cells = <0>;
1498 status = "disabled";
1499 };
1500
1501 uart_B: serial@23000 {
1502 compatible = "amlogic,meson-gx-uart";
1503 reg = <0x0 0x23000 0x0 0x18>;
1504 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
1505 status = "disabled";
1506 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
1507 clock-names = "xtal", "pclk", "baud";
1508 };
1509
1510 uart_A: serial@24000 {
1511 compatible = "amlogic,meson-gx-uart";
1512 reg = <0x0 0x24000 0x0 0x18>;
1513 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
1514 status = "disabled";
1515 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
1516 clock-names = "xtal", "pclk", "baud";
1517 };
1518 };
1519
1520 apb: bus@ffe00000 {
1521 compatible = "simple-bus";
1522 reg = <0x0 0xffe00000 0x0 0x200000>;
1523 #address-cells = <2>;
1524 #size-cells = <2>;
1525 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
1526
1527 sd_emmc_b: sd@5000 {
1528 compatible = "amlogic,meson-axg-mmc";
1529 reg = <0x0 0x5000 0x0 0x800>;
1530 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
1531 status = "disabled";
1532 clocks = <&clkc CLKID_SD_EMMC_B>,
1533 <&clkc CLKID_SD_EMMC_B_CLK0>,
1534 <&clkc CLKID_FCLK_DIV2>;
1535 clock-names = "core", "clkin0", "clkin1";
1536 resets = <&reset RESET_SD_EMMC_B>;
1537 };
1538
1539 sd_emmc_c: mmc@7000 {
1540 compatible = "amlogic,meson-axg-mmc";
1541 reg = <0x0 0x7000 0x0 0x800>;
1542 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
1543 status = "disabled";
1544 clocks = <&clkc CLKID_SD_EMMC_C>,
1545 <&clkc CLKID_SD_EMMC_C_CLK0>,
1546 <&clkc CLKID_FCLK_DIV2>;
1547 clock-names = "core", "clkin0", "clkin1";
1548 resets = <&reset RESET_SD_EMMC_C>;
1549 };
1550 };
1551
1552 sram: sram@fffc0000 {
1553 compatible = "amlogic,meson-axg-sram", "mmio-sram";
1554 reg = <0x0 0xfffc0000 0x0 0x20000>;
1555 #address-cells = <1>;
1556 #size-cells = <1>;
1557 ranges = <0 0x0 0xfffc0000 0x20000>;
1558
1559 cpu_scp_lpri: scp-shmem@0 {
1560 compatible = "amlogic,meson-axg-scp-shmem";
1561 reg = <0x13000 0x400>;
1562 };
1563
1564 cpu_scp_hpri: scp-shmem@200 {
1565 compatible = "amlogic,meson-axg-scp-shmem";
1566 reg = <0x13400 0x400>;
1567 };
1568 };
1569 };
1570
1571 timer {
1572 compatible = "arm,armv8-timer";
1573 interrupts = <GIC_PPI 13
1574 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1575 <GIC_PPI 14
1576 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1577 <GIC_PPI 11
1578 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1579 <GIC_PPI 10
1580 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
1581 };
1582
1583 xtal: xtal-clk {
1584 compatible = "fixed-clock";
1585 clock-frequency = <24000000>;
1586 clock-output-names = "xtal";
1587 #clock-cells = <0>;
1588 };
1589};