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gerrit.cesnet.cz / github / trini / u-boot / 45997e0a86ee8d8abec6d791a241cb20011fe0e3 / . / board / prodrive / alpr / init.S
blob: 9f9812ad0734d8ca7c4d1922a8e17298de157881 [file] [log] [blame]
Stefan Roese899620c2006-08-15 14:22:35 +0200[diff] [blame]1/*
Stefan Roese5bc528f2006-10-07 11:35:25 +0200[diff] [blame]2 * (C) Copyright 2006
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
Stefan Roese899620c2006-08-15 14:22:35 +0200[diff] [blame]23
24#include <ppc_asm.tmpl>
Stefan Roesecf6eb6d2010-04-14 13:57:18 +0200[diff] [blame]25#include <asm/mmu.h>
Stefan Roese899620c2006-08-15 14:22:35 +0200[diff] [blame]26#include <config.h>
27
Stefan Roese899620c2006-08-15 14:22:35 +0200[diff] [blame]28/**************************************************************************
29 * TLB TABLE
30 *
31 * This table is used by the cpu boot code to setup the initial tlb
32 * entries. Rather than make broad assumptions in the cpu source tree,
33 * this table lets each board set things up however they like.
34 *
35 * Pointer to the table is returned in r1
36 *
37 *************************************************************************/
38
Stefan Roese5bc528f2006-10-07 11:35:25 +0200[diff] [blame]39 .section .bootpg,"ax"
40 .globl tlbtab
Stefan Roese899620c2006-08-15 14:22:35 +0200[diff] [blame]41
42tlbtab:
Stefan Roese5bc528f2006-10-07 11:35:25 +0200[diff] [blame]43 tlbtab_start
Stefan Roesecf6eb6d2010-04-14 13:57:18 +0200[diff] [blame]44 tlbentry(0xff000000, SZ_16M, 0xff000000, 1, AC_RWX | SA_IG )
45 tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
46 tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX)
47 tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX)
Pieter Voorthuijsen511e4f92008-03-17 09:27:56 +0100[diff] [blame]48#ifdef CONFIG_4xx_DCACHE
Stefan Roesecf6eb6d2010-04-14 13:57:18 +0200[diff] [blame]49 tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_G)
Pieter Voorthuijsen511e4f92008-03-17 09:27:56 +0100[diff] [blame]50#else
Stefan Roesecf6eb6d2010-04-14 13:57:18 +0200[diff] [blame]51 tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG)
Pieter Voorthuijsen511e4f92008-03-17 09:27:56 +0100[diff] [blame]52#endif
53
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]54#ifdef CONFIG_SYS_INIT_RAM_DCACHE
Pieter Voorthuijsen511e4f92008-03-17 09:27:56 +0100[diff] [blame]55 /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
Stefan Roesecf6eb6d2010-04-14 13:57:18 +0200[diff] [blame]56 tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
Pieter Voorthuijsen511e4f92008-03-17 09:27:56 +0100[diff] [blame]57#endif
Stefan Roesecf6eb6d2010-04-14 13:57:18 +0200[diff] [blame]58 tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG)
Stefan Roese899620c2006-08-15 14:22:35 +0200[diff] [blame]59
Stefan Roese5bc528f2006-10-07 11:35:25 +0200[diff] [blame]60 /* PCI */
Stefan Roesecf6eb6d2010-04-14 13:57:18 +0200[diff] [blame]61 tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 3, AC_RW | SA_IG)
62 tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 3, AC_RW | SA_IG)
63 tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 3, AC_RW | SA_IG)
Stefan Roese5bc528f2006-10-07 11:35:25 +0200[diff] [blame]64
65 /* NAND */
Stefan Roesecf6eb6d2010-04-14 13:57:18 +0200[diff] [blame]66 tlbentry(CONFIG_SYS_NAND_BASE, SZ_4K, CONFIG_SYS_NAND_BASE, 1, AC_RWX | SA_IG)
Stefan Roese5bc528f2006-10-07 11:35:25 +0200[diff] [blame]67 tlbtab_end