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gerrit.cesnet.cz / github / trini / u-boot / 45370e1836dc0a7ac8e1d4828924e971d01fd92a / . / arch / m68k / cpu / mcf5445x / start.S
blob: 5fc944d2f3edfd009e955df1bf968d92a46eb573 [file] [log] [blame]
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]1/*
2 * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
3 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
4 *
Alison Wang45370e12012-10-18 19:25:51 +0000[diff] [blame^]5 * Copyright 2010-2012 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 *
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
Alison Wang45370e12012-10-18 19:25:51 +0000[diff] [blame^]27#include <common.h>
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200[diff] [blame]28#include <asm-offsets.h>
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]29#include <config.h>
Alison Wang45370e12012-10-18 19:25:51 +0000[diff] [blame^]30#include <timestamp.h>
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]31#include "version.h"
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600[diff] [blame]32#include <asm/cache.h>
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]33
34#ifndef CONFIG_IDENT_STRING
35#define CONFIG_IDENT_STRING ""
36#endif
37
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]38#define _START _start
39#define _FAULT _fault
40
41#define SAVE_ALL \
42 move.w #0x2700,%sr; /* disable intrs */ \
43 subl #60,%sp; /* space for 15 regs */ \
44 moveml %d0-%d7/%a0-%a6,%sp@;
45
46#define RESTORE_ALL \
47 moveml %sp@,%d0-%d7/%a0-%a6; \
48 addl #60,%sp; /* space for 15 regs */ \
49 rte;
50
Alison Wang45370e12012-10-18 19:25:51 +0000[diff] [blame^]51#if defined(CONFIG_SERIAL_BOOT)
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200[diff] [blame]52#define ASM_DRAMINIT (asm_dram_init - CONFIG_SYS_TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
Alison Wang45370e12012-10-18 19:25:51 +0000[diff] [blame^]53#define ASM_DRAMINIT_N (asm_dram_init - TEXT_BASE)
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200[diff] [blame]54#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - CONFIG_SYS_TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]55#endif
56
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]57.text
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]58
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]59/*
60 * Vector table. This is used for initial platform startup.
61 * These vectors are to catch any un-intended traps.
62 */
63_vectors:
Alison Wang45370e12012-10-18 19:25:51 +0000[diff] [blame^]64#if defined(CONFIG_SERIAL_BOOT)
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]65
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]66INITSP: .long 0 /* Initial SP */
Alison Wang45370e12012-10-18 19:25:51 +0000[diff] [blame^]67#ifdef CONFIG_CF_SBF
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]68INITPC: .long ASM_DRAMINIT /* Initial PC */
Alison Wang45370e12012-10-18 19:25:51 +0000[diff] [blame^]69#endif
70#ifdef CONFIG_SYS_NAND_BOOT
71INITPC: .long ASM_DRAMINIT_N /* Initial PC */
72#endif
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]73
74#else
75
76INITSP: .long 0 /* Initial SP */
77INITPC: .long _START /* Initial PC */
78
79#endif
80
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]81vector02: .long _FAULT /* Access Error */
82vector03: .long _FAULT /* Address Error */
83vector04: .long _FAULT /* Illegal Instruction */
84vector05: .long _FAULT /* Reserved */
85vector06: .long _FAULT /* Reserved */
86vector07: .long _FAULT /* Reserved */
87vector08: .long _FAULT /* Privilege Violation */
88vector09: .long _FAULT /* Trace */
89vector0A: .long _FAULT /* Unimplemented A-Line */
90vector0B: .long _FAULT /* Unimplemented F-Line */
91vector0C: .long _FAULT /* Debug Interrupt */
92vector0D: .long _FAULT /* Reserved */
93vector0E: .long _FAULT /* Format Error */
94vector0F: .long _FAULT /* Unitialized Int. */
95
96/* Reserved */
97vector10_17:
98.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
99
100vector18: .long _FAULT /* Spurious Interrupt */
101vector19: .long _FAULT /* Autovector Level 1 */
102vector1A: .long _FAULT /* Autovector Level 2 */
103vector1B: .long _FAULT /* Autovector Level 3 */
104vector1C: .long _FAULT /* Autovector Level 4 */
105vector1D: .long _FAULT /* Autovector Level 5 */
106vector1E: .long _FAULT /* Autovector Level 6 */
107vector1F: .long _FAULT /* Autovector Level 7 */
108
Alison Wang45370e12012-10-18 19:25:51 +0000[diff] [blame^]109#if !defined(CONFIG_SERIAL_BOOT)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]110
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]111/* TRAP #0 - #15 */
112vector20_2F:
113.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
114.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
115
116/* Reserved */
117vector30_3F:
118.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
119.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
120
121vector64_127:
122.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
123.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
124.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
125.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
126.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
127.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
128.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
129.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
130
131vector128_191:
132.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
133.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
134.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
135.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
136.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
137.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
138.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
139.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
140
141vector192_255:
142.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
143.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
144.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
145.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
146.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
147.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
148.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
149.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]150#endif
151
Alison Wang45370e12012-10-18 19:25:51 +0000[diff] [blame^]152#if defined(CONFIG_SERIAL_BOOT)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]153 /* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
154asm_sbf_img_hdr:
155 .long 0x00000000 /* checksum, not yet implemented */
Alison Wang45370e12012-10-18 19:25:51 +0000[diff] [blame^]156 .long 0x00040000 /* image length */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200[diff] [blame]157 .long CONFIG_SYS_TEXT_BASE /* image to be relocated at */
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]158
159asm_dram_init:
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame]160 move.w #0x2700,%sr /* Mask off Interrupt */
161
Alison Wang45370e12012-10-18 19:25:51 +0000[diff] [blame^]162#ifdef CONFIG_SYS_NAND_BOOT
163 /* for assembly stack */
164 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
165 movec %d0, %RAMBAR1
166
167 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
168 clr.l %sp@-
169#endif
170
171#ifdef CONFIG_CF_SBF
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame]172 move.l #CONFIG_SYS_INIT_RAM_ADDR, %d0
173 movec %d0, %VBR
174
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]175 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame]176 movec %d0, %RAMBAR1
177
178 /* initialize general use internal ram */
179 move.l #0, %d0
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600[diff] [blame]180 move.l #(ICACHE_STATUS), %a1 /* icache */
181 move.l #(DCACHE_STATUS), %a2 /* dcache */
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame]182 move.l %d0, (%a1)
183 move.l %d0, (%a2)
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame]184
185 /* invalidate and disable cache */
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600[diff] [blame]186 move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame]187 movec %d0, %CACR /* Invalidate cache */
188 move.l #0, %d0
189 movec %d0, %ACR0
190 movec %d0, %ACR1
191 movec %d0, %ACR2
192 movec %d0, %ACR3
193
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]194 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]195 clr.l %sp@-
196
197 /* Must disable global address */
198 move.l #0xFC008000, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]199 move.l #(CONFIG_SYS_CS0_BASE), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]200 move.l #0xFC008008, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]201 move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]202 move.l #0xFC008004, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]203 move.l #(CONFIG_SYS_CS0_MASK), (%a1)
Alison Wang45370e12012-10-18 19:25:51 +0000[diff] [blame^]204#endif /* CONFIG_CF_SBF */
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]205
Alison Wang45370e12012-10-18 19:25:51 +0000[diff] [blame^]206#ifdef CONFIG_MCF5441x
207 /* TC: enable all peripherals,
208 in the future only enable certain peripherals */
209 move.l #0xFC04002D, %a1
210
211#if defined(CONFIG_CF_SBF)
212 move.b #23, (%a1) /* dspi */
213#endif
214 move.b #46, (%a1) /* DDR */
215
216 /* slew settings */
217 move.l #0xEC094060, %a1
218 move.b #0, (%a1)
219
220 /* use vco instead of cpu*2 clock for ddr clock */
221 move.l #0xEC09001A, %a1
222 move.w #0xE01D, (%a1)
223
224 /* DDR settings */
225 move.l #0xFC0B8180, %a1
226 move.l #0x00000000, (%a1)
227 move.l #0x40000000, (%a1)
228
229 move.l #0xFC0B81AC, %a1
230 move.l #0x01030203, (%a1)
231
232 move.l #0xFC0B8000, %a1
233 move.l #0x01010101, (%a1)+ /* 0x00 */
234 move.l #0x00000101, (%a1)+ /* 0x04 */
235 move.l #0x01010100, (%a1)+ /* 0x08 */
236 move.l #0x01010000, (%a1)+ /* 0x0C */
237 move.l #0x00010101, (%a1)+ /* 0x10 */
238 move.l #0xFC0B8018, %a1
239 move.l #0x00010100, (%a1)+ /* 0x18 */
240 move.l #0x00000001, (%a1)+ /* 0x1C */
241 move.l #0x01000001, (%a1)+ /* 0x20 */
242 move.l #0x00000100, (%a1)+ /* 0x24 */
243 move.l #0x00010001, (%a1)+ /* 0x28 */
244 move.l #0x00000200, (%a1)+ /* 0x2C */
245 move.l #0x01000002, (%a1)+ /* 0x30 */
246 move.l #0x00000000, (%a1)+ /* 0x34 */
247 move.l #0x00000100, (%a1)+ /* 0x38 */
248 move.l #0x02000100, (%a1)+ /* 0x3C */
249 move.l #0x02000407, (%a1)+ /* 0x40 */
250 move.l #0x02030007, (%a1)+ /* 0x44 */
251 move.l #0x02000100, (%a1)+ /* 0x48 */
252 move.l #0x0A030203, (%a1)+ /* 0x4C */
253 move.l #0x00020708, (%a1)+ /* 0x50 */
254 move.l #0x00050008, (%a1)+ /* 0x54 */
255 move.l #0x04030002, (%a1)+ /* 0x58 */
256 move.l #0x00000004, (%a1)+ /* 0x5C */
257 move.l #0x020A0000, (%a1)+ /* 0x60 */
258 move.l #0x0C00000E, (%a1)+ /* 0x64 */
259 move.l #0x00002004, (%a1)+ /* 0x68 */
260 move.l #0x00000000, (%a1)+ /* 0x6C */
261 move.l #0x00100010, (%a1)+ /* 0x70 */
262 move.l #0x00100010, (%a1)+ /* 0x74 */
263 move.l #0x00000000, (%a1)+ /* 0x78 */
264 move.l #0x07990000, (%a1)+ /* 0x7C */
265 move.l #0xFC0B80A0, %a1
266 move.l #0x00000000, (%a1)+ /* 0xA0 */
267 move.l #0x00C80064, (%a1)+ /* 0xA4 */
268 move.l #0x44520002, (%a1)+ /* 0xA8 */
269 move.l #0x00C80023, (%a1)+ /* 0xAC */
270 move.l #0xFC0B80B4, %a1
271 move.l #0x0000C350, (%a1) /* 0xB4 */
272 move.l #0xFC0B80E0, %a1
273 move.l #0x04000000, (%a1)+ /* 0xE0 */
274 move.l #0x03000304, (%a1)+ /* 0xE4 */
275 move.l #0x40040000, (%a1)+ /* 0xE8 */
276 move.l #0xC0004004, (%a1)+ /* 0xEC */
277 move.l #0x0642C000, (%a1)+ /* 0xF0 */
278 move.l #0x00000642, (%a1)+ /* 0xF4 */
279 move.l #0xFC0B8024, %a1
280 tpf
281 move.l #0x01000100, (%a1) /* 0x24 */
282
283 move.l #0x2000, %d1
284 jsr asm_delay
285#endif /* CONFIG_MCF5441x */
286
287#ifdef CONFIG_MCF5445x
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame]288 /* Dram Initialization a1, a2, and d0 */
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]289 /* mscr sdram */
290 move.l #0xFC0A4074, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]291 move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]292 nop
293
294 /* SDRAM Chip 0 and 1 */
295 move.l #0xFC0B8110, %a1
296 move.l #0xFC0B8114, %a2
297
298 /* calculate the size */
299 move.l #0x13, %d1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]300 move.l #(CONFIG_SYS_SDRAM_SIZE), %d2
301#ifdef CONFIG_SYS_SDRAM_BASE1
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]302 lsr.l #1, %d2
303#endif
304
305dramsz_loop:
306 lsr.l #1, %d2
307 add.l #1, %d1
308 cmp.l #1, %d2
309 bne dramsz_loop
Alison Wang45370e12012-10-18 19:25:51 +0000[diff] [blame^]310#ifdef CONFIG_SYS_NAND_BOOT
311 beq asm_nand_chk_status
312#endif
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]313 /* SDRAM Chip 0 and 1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]314 move.l #(CONFIG_SYS_SDRAM_BASE), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]315 or.l %d1, (%a1)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]316#ifdef CONFIG_SYS_SDRAM_BASE1
317 move.l #(CONFIG_SYS_SDRAM_BASE1), (%a2)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]318 or.l %d1, (%a2)
319#endif
320 nop
321
322 /* dram cfg1 and cfg2 */
323 move.l #0xFC0B8008, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]324 move.l #(CONFIG_SYS_SDRAM_CFG1), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]325 nop
326 move.l #0xFC0B800C, %a2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]327 move.l #(CONFIG_SYS_SDRAM_CFG2), (%a2)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]328 nop
329
330 move.l #0xFC0B8000, %a1 /* Mode */
331 move.l #0xFC0B8004, %a2 /* Ctrl */
332
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]333 /* Issue PALL */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]334 move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]335 nop
336
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame]337#ifdef CONFIG_M54455EVB
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]338 /* Issue LEMR */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]339 move.l #(CONFIG_SYS_SDRAM_EMOD + 0x408), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]340 nop
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]341 move.l #(CONFIG_SYS_SDRAM_MODE + 0x300), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]342 nop
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]343#endif
344
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame]345 move.l #1000, %d1
346 jsr asm_delay
347
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]348 /* Issue PALL */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]349 move.l #(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]350 nop
351
352 /* Perform two refresh cycles */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]353 move.l #(CONFIG_SYS_SDRAM_CTRL + 4), %d0
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]354 nop
355 move.l %d0, (%a2)
356 move.l %d0, (%a2)
357 nop
358
359#ifdef CONFIG_M54455EVB
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]360 move.l #(CONFIG_SYS_SDRAM_MODE + 0x200), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]361 nop
362#elif defined(CONFIG_M54451EVB)
363 /* Issue LEMR */
TsiChung Liewc3a9e632009-02-18 11:49:31 +0000[diff] [blame]364 move.l #(CONFIG_SYS_SDRAM_MODE), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]365 nop
TsiChung Liewc3a9e632009-02-18 11:49:31 +0000[diff] [blame]366 move.l #(CONFIG_SYS_SDRAM_EMOD), (%a1)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]367#endif
368
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame]369 move.l #500, %d1
370 jsr asm_delay
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]371
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame]372 move.l #(CONFIG_SYS_SDRAM_CTRL), %d1
373 and.l #0x7FFFFFFF, %d1
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]374#ifdef CONFIG_M54455EVB
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame]375 or.l #0x10000C00, %d1
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]376#elif defined(CONFIG_M54451EVB)
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame]377 or.l #0x10000C00, %d1
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]378#endif
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame]379 move.l %d1, (%a2)
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]380 nop
381
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame]382 move.l #2000, %d1
383 jsr asm_delay
Alison Wang45370e12012-10-18 19:25:51 +0000[diff] [blame^]384#endif /* CONFIG_MCF5445x */
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame]385
Alison Wang45370e12012-10-18 19:25:51 +0000[diff] [blame^]386#ifdef CONFIG_CF_SBF
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]387 /*
388 * DSPI Initialization
389 * a0 - general, sram - 0x80008000 - 32, see M54455EVB.h
390 * a1 - dspi status
391 * a2 - dtfr
392 * a3 - drfr
393 * a4 - Dst addr
394 */
395 /* Enable pins for DSPI mode - chip-selects are enabled later */
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame]396asm_dspi_init:
Alison Wang45370e12012-10-18 19:25:51 +0000[diff] [blame^]397#ifdef CONFIG_MCF5441x
398 move.l #0xEC09404E, %a1
399 move.l #0xEC09404F, %a2
400 move.b #0xFF, (%a1)
401 move.b #0x80, (%a2)
402#endif
403
404#ifdef CONFIG_MCF5445x
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]405 move.l #0xFC0A4063, %a0
406 move.b #0x7F, (%a0)
Alison Wang45370e12012-10-18 19:25:51 +0000[diff] [blame^]407#endif
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]408 /* Configure DSPI module */
409 move.l #0xFC05C000, %a0
410 move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */
411
412 move.l #0xFC05C00C, %a0
Alison Wang45370e12012-10-18 19:25:51 +0000[diff] [blame^]413#ifdef CONFIG_MCF5441x
414 move.l #0x3E000016, (%a0)
415#endif
416#ifdef CONFIG_MCF5445x
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]417 move.l #0x3E000011, (%a0)
Alison Wang45370e12012-10-18 19:25:51 +0000[diff] [blame^]418#endif
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]419
420 move.l #0xFC05C034, %a2 /* dtfr */
421 move.l #0xFC05C03B, %a3 /* drfr */
422
423 move.l #(ASM_SBF_IMG_HDR + 4), %a1
424 move.l (%a1)+, %d5
425 move.l (%a1), %a4
426
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]427 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0
428 move.l #(CONFIG_SYS_SBFHDR_SIZE), %d4
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]429
430 move.l #0xFC05C02C, %a1 /* dspi status */
431
432 /* Issue commands and address */
433 move.l #0x8002000B, %d2 /* Fast Read Cmd */
434 jsr asm_dspi_wr_status
435 jsr asm_dspi_rd_status
436
437 move.l #0x80020000, %d2 /* Address byte 2 */
438 jsr asm_dspi_wr_status
439 jsr asm_dspi_rd_status
440
441 move.l #0x80020000, %d2 /* Address byte 1 */
442 jsr asm_dspi_wr_status
443 jsr asm_dspi_rd_status
444
445 move.l #0x80020000, %d2 /* Address byte 0 */
446 jsr asm_dspi_wr_status
447 jsr asm_dspi_rd_status
448
449 move.l #0x80020000, %d2 /* Dummy Wr and Rd */
450 jsr asm_dspi_wr_status
451 jsr asm_dspi_rd_status
452
453 /* Transfer serial boot header to sram */
454asm_dspi_rd_loop1:
455 move.l #0x80020000, %d2
456 jsr asm_dspi_wr_status
457 jsr asm_dspi_rd_status
458
459 move.b %d1, (%a0) /* read, copy to dst */
460
461 add.l #1, %a0 /* inc dst by 1 */
462 sub.l #1, %d4 /* dec cnt by 1 */
463 bne asm_dspi_rd_loop1
464
465 /* Transfer u-boot from serial flash to memory */
466asm_dspi_rd_loop2:
467 move.l #0x80020000, %d2
468 jsr asm_dspi_wr_status
469 jsr asm_dspi_rd_status
470
471 move.b %d1, (%a4) /* read, copy to dst */
472
473 add.l #1, %a4 /* inc dst by 1 */
474 sub.l #1, %d5 /* dec cnt by 1 */
475 bne asm_dspi_rd_loop2
476
477 move.l #0x00020000, %d2 /* Terminate */
478 jsr asm_dspi_wr_status
479 jsr asm_dspi_rd_status
480
481 /* jump to memory and execute */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200[diff] [blame]482 move.l #(CONFIG_SYS_TEXT_BASE + 0x400), %a0
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]483 jmp (%a0)
484
485asm_dspi_wr_status:
486 move.l (%a1), %d0 /* status */
487 and.l #0x0000F000, %d0
488 cmp.l #0x00003000, %d0
489 bgt asm_dspi_wr_status
490
491 move.l %d2, (%a2)
492 rts
493
494asm_dspi_rd_status:
495 move.l (%a1), %d0 /* status */
496 and.l #0x000000F0, %d0
497 lsr.l #4, %d0
498 cmp.l #0, %d0
499 beq asm_dspi_rd_status
500
501 move.b (%a3), %d1
502 rts
Alison Wang45370e12012-10-18 19:25:51 +0000[diff] [blame^]503#endif /* CONFIG_CF_SBF */
504
505#ifdef CONFIG_SYS_NAND_BOOT
506 /* copy 4 boot pages to dram as soon as possible */
507 /* each page is 996 bytes (1056 total with 60 ECC bytes */
508 move.l #0x00000000, %a1 /* src */
509 move.l #TEXT_BASE, %a2 /* dst */
510 move.l #0x3E0, %d0 /* sz in long */
511
512asm_boot_nand_copy:
513 move.l (%a1)+, (%a2)+
514 subq.l #1, %d0
515 bne asm_boot_nand_copy
516
517 /* jump to memory and execute */
518 move.l #(asm_nand_init), %a0
519 jmp (%a0)
520
521asm_nand_init:
522 /* exit nand boot-mode */
523 move.l #0xFC0FFF30, %a1
524 or.l #0x00000040, %d1
525 move.l %d1, (%a1)
526
527 /* initialize general use internal ram */
528 move.l #0, %d0
529 move.l #(CACR_STATUS), %a1 /* CACR */
530 move.l #(ICACHE_STATUS), %a2 /* icache */
531 move.l #(DCACHE_STATUS), %a3 /* dcache */
532 move.l %d0, (%a1)
533 move.l %d0, (%a2)
534 move.l %d0, (%a3)
535
536 /* invalidate and disable cache */
537 move.l #0x01004100, %d0 /* Invalidate cache cmd */
538 movec %d0, %CACR /* Invalidate cache */
539 move.l #0, %d0
540 movec %d0, %ACR0
541 movec %d0, %ACR1
542 movec %d0, %ACR2
543 movec %d0, %ACR3
544
545 /* Must disable global address */
546 move.l #0xFC008000, %a1
547 move.l #(CONFIG_SYS_CS0_BASE), (%a1)
548 move.l #0xFC008008, %a1
549 move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
550 move.l #0xFC008004, %a1
551 move.l #(CONFIG_SYS_CS0_MASK), (%a1)
552
553 /* NAND port configuration */
554 move.l #0xEC094048, %a1
555 move.b #0xFD, (%a1)+
556 move.b #0x5F, (%a1)+
557 move.b #0x04, (%a1)+
558
559 /* reset nand */
560 move.l #0xFC0FFF38, %a1 /* isr */
561 move.l #0x000e0000, (%a1)
562 move.l #0xFC0FFF08, %a2
563 move.l #0x00000000, (%a2)+ /* car */
564 move.l #0x11000000, (%a2)+ /* rar */
565 move.l #0x00000000, (%a2)+ /* rpt */
566 move.l #0x00000000, (%a2)+ /* rai */
567 move.l #0xFC0FFF2c, %a2 /* cfg */
568 move.l #0x00000000, (%a2)+ /* secsz */
569 move.l #0x000e0681, (%a2)+
570 move.l #0xFC0FFF04, %a2 /* cmd2 */
571 move.l #0xFF404001, (%a2)
572 move.l #0x000e0000, (%a1)
573
574 move.l #0x2000, %d1
575 jsr asm_delay
576
577 /* setup nand */
578 move.l #0xFC0FFF00, %a1
579 move.l #0x30700000, (%a1)+ /* cmd1 */
580 move.l #0x007EF000, (%a1)+ /* cmd2 */
581
582 move.l #0xFC0FFF2C, %a1
583 move.l #0x00000841, (%a1)+ /* secsz */
584 move.l #0x000e0681, (%a1)+ /* cfg */
585
586 move.l #100, %d4 /* 100 pages ~200KB */
587 move.l #4, %d2 /* start at 4 */
588 move.l #0xFC0FFF04, %a0 /* cmd2 */
589 move.l #0xFC0FFF0C, %a1 /* rar */
590 move.l #(TEXT_BASE + 0xF80), %a2 /* dst */
591
592asm_nand_read:
593 move.l #0x11000000, %d0 /* rar */
594 or.l %d2, %d0
595 move.l %d0, (%a1)
596 add.l #1, %d2
597
598 move.l (%a0), %d0 /* cmd2 */
599 or.l #1, %d0
600 move.l %d0, (%a0)
601
602 move.l #0x200, %d1
603 jsr asm_delay
604
605asm_nand_chk_status:
606 move.l #0xFC0FFF38, %a4 /* isr */
607 move.l (%a4), %d0
608 and.l #0x40000000, %d0
609 tst.l %d0
610 beq asm_nand_chk_status
611
612 move.l #0xFC0FFF38, %a4 /* isr */
613 move.l (%a4), %d0
614 or.l #0x000E0000, %d0
615 move.l %d0, (%a4)
616
617 move.l #0x200, %d3
618 move.l #0xFC0FC000, %a3 /* buf 1 */
619asm_nand_copy:
620 move.l (%a3)+, (%a2)+
621 subq.l #1, %d3
622 bgt asm_nand_copy
623
624 subq.l #1, %d4
625 bgt asm_nand_read
626
627 /* jump to memory and execute */
628 move.l #(TEXT_BASE + 0x400), %a0
629 jmp (%a0)
630
631#endif /* CONFIG_SYS_NAND_BOOT */
TsiChung Liew709b3842009-06-11 15:39:57 +0000[diff] [blame]632
633asm_delay:
634 nop
635 subq.l #1, %d1
636 bne asm_delay
637 rts
Alison Wang45370e12012-10-18 19:25:51 +0000[diff] [blame^]638#endif /* CONFIG_CF_SBF || CONFIG_NAND_U_BOOT */
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]639
640 .text
TsiChung Liew9f751552008-07-23 20:38:53 -0500[diff] [blame]641 . = 0x400
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]642 .globl _start
643_start:
Alison Wang45370e12012-10-18 19:25:51 +0000[diff] [blame^]644#if !defined(CONFIG_SERIAL_BOOT)
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]645 nop
646 nop
647 move.w #0x2700,%sr /* Mask off Interrupt */
648
649 /* Set vector base register at the beginning of the Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]650 move.l #CONFIG_SYS_FLASH_BASE, %d0
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]651 movec %d0, %VBR
652
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]653 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
TsiChungLiew225a24b2007-11-07 18:00:54 -0600[diff] [blame]654 movec %d0, %RAMBAR1
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]655
656 /* initialize general use internal ram */
657 move.l #0, %d0
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600[diff] [blame]658 move.l #(ICACHE_STATUS), %a1 /* icache */
659 move.l #(DCACHE_STATUS), %a2 /* dcache */
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]660 move.l %d0, (%a1)
661 move.l %d0, (%a2)
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]662
663 /* invalidate and disable cache */
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600[diff] [blame]664 move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]665 movec %d0, %CACR /* Invalidate cache */
666 move.l #0, %d0
667 movec %d0, %ACR0
668 movec %d0, %ACR1
669 movec %d0, %ACR2
670 movec %d0, %ACR3
Alison Wang45370e12012-10-18 19:25:51 +0000[diff] [blame^]671#else
672 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
673 movec %d0, %RAMBAR1
674#endif
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]675
676 /* set stackpointer to end of internal ram to get some stackspace for
677 the first c-code */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]678 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]679 clr.l %sp@-
680
681 move.l #__got_start, %a5 /* put relocation table address to a5 */
682
683 bsr cpu_init_f /* run low-level CPU init code (from flash) */
684 bsr board_init_f /* run low-level board init code (from flash) */
685
686 /* board_init_f() does not return */
687
688/*------------------------------------------------------------------------------*/
689
690/*
691 * void relocate_code (addr_sp, gd, addr_moni)
692 *
693 * This "function" does not return, instead it continues in RAM
694 * after relocating the monitor code.
695 *
696 * r3 = dest
697 * r4 = src
698 * r5 = length in bytes
699 * r6 = cachelinesize
700 */
701 .globl relocate_code
702relocate_code:
703 link.w %a6,#0
704 move.l 8(%a6), %sp /* set new stack pointer */
705
706 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
707 move.l 16(%a6), %a0 /* Save copy of Destination Address */
708
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]709 move.l #CONFIG_SYS_MONITOR_BASE, %a1
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]710 move.l #__init_end, %a2
711 move.l %a0, %a3
712
713 /* copy the code to RAM */
7141:
715 move.l (%a1)+, (%a3)+
716 cmp.l %a1,%a2
717 bgt.s 1b
718
719/*
720 * We are done. Do not return, instead branch to second part of board
721 * initialization, now running from RAM.
722 */
723 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]724 add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]725 jmp (%a1)
726
727in_ram:
728
729clear_bss:
730 /*
731 * Now clear BSS segment
732 */
733 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]734 add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]735 move.l %a0, %d1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]736 add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]7376:
738 clr.l (%a1)+
739 cmp.l %a1,%d1
740 bgt.s 6b
741
742 /*
743 * fix got table in RAM
744 */
745 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]746 add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]747 move.l %a1,%a5 /* * fix got pointer register a5 */
748
749 move.l %a0, %a2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]750 add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]751
7527:
753 move.l (%a1),%d1
754 sub.l #_start,%d1
755 add.l %a0,%d1
756 move.l %d1,(%a1)+
757 cmp.l %a2, %a1
758 bne 7b
759
760 /* calculate relative jump to board_init_r in ram */
761 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]762 add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]763
764 /* set parameters for board_init_r */
765 move.l %a0,-(%sp) /* dest_addr */
766 move.l %d0,-(%sp) /* gd */
767 jsr (%a1)
768
769/*------------------------------------------------------------------------------*/
770/* exception code */
771 .globl _fault
772_fault:
TsiChung Liew3b1e8ac2008-06-18 19:12:13 -0500[diff] [blame]773 bra _fault
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]774 .globl _exc_handler
775
776_exc_handler:
777 SAVE_ALL
778 movel %sp,%sp@-
779 bsr exc_handler
780 addql #4,%sp
781 RESTORE_ALL
782
783 .globl _int_handler
784_int_handler:
785 SAVE_ALL
786 movel %sp,%sp@-
787 bsr int_handler
788 addql #4,%sp
789 RESTORE_ALL
790
791/*------------------------------------------------------------------------------*/
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500[diff] [blame]792
793 .globl version_string
794version_string:
Andreas Bießmann09c2e902011-07-18 20:24:04 +0200[diff] [blame]795 .ascii U_BOOT_VERSION_STRING, "\0"
TsiChung Liew9b464322008-03-28 08:47:45 -0500[diff] [blame]796 .align 4