| Heiko Schocher | 4535a24 | 2013-11-18 08:07:23 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * (C) Copyright 2007-2008 |
| 3 | * Stelian Pop <stelian@popies.net> |
| 4 | * Lead Tech Design <www.leadtechdesign.com> |
| 5 | * |
| 6 | * (C) Copyright 2012 |
| 7 | * Markus Hubig <mhubig@imko.de> |
| 8 | * IMKO GmbH <www.imko.de> |
| 9 | * |
| 10 | * Copyright (C) 2013 DENX Software Engineering, hs@denx.de |
| 11 | * |
| 12 | * SPDX-License-Identifier: GPL-2.0+ |
| 13 | */ |
| 14 | |
| 15 | #include <common.h> |
| 16 | #include <asm/io.h> |
| 17 | #include <asm/sizes.h> |
| 18 | #include <asm/arch/at91_pmc.h> |
| 19 | #include <asm/arch/at91_rstc.h> |
| 20 | #include <watchdog.h> |
| 21 | |
| 22 | void at91_phy_reset(void) |
| 23 | { |
| 24 | unsigned long erstl; |
| 25 | unsigned long start = get_timer(0); |
| 26 | unsigned long const timeout = 1000; /* 1000ms */ |
| 27 | at91_rstc_t *rstc = (at91_rstc_t *)ATMEL_BASE_RSTC; |
| 28 | |
| 29 | erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; |
| 30 | |
| 31 | /* |
| 32 | * Need to reset PHY -> 500ms reset |
| 33 | * Reset PHY by pulling the NRST line for 500ms to low. To do so |
| 34 | * disable user reset for low level on NRST pin and poll the NRST |
| 35 | * level in reset status register. |
| 36 | */ |
| 37 | writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) | |
| 38 | AT91_RSTC_MR_URSTEN, &rstc->mr); |
| 39 | |
| 40 | writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); |
| 41 | |
| 42 | /* Wait for end of hardware reset */ |
| 43 | while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) { |
| 44 | /* avoid shutdown by watchdog */ |
| 45 | WATCHDOG_RESET(); |
| 46 | mdelay(10); |
| 47 | |
| 48 | /* timeout for not getting stuck in an endless loop */ |
| 49 | if (get_timer(start) >= timeout) { |
| 50 | puts("*** ERROR: Timeout waiting for PHY reset!\n"); |
| 51 | break; |
| 52 | } |
| 53 | }; |
| 54 | |
| 55 | /* Restore NRST value */ |
| 56 | writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr); |
| 57 | } |