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wdenk5772de42002-11-03 10:23:02 +00001/**************************************************************************
2Etherboot - BOOTP/TFTP Bootstrap Program
3Skeleton NIC driver for Etherboot
4***************************************************************************/
5
6/*
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2, or (at
10 * your option) any later version.
11 */
12
13/*
14 * This file is a modified version from the Galileo polled mode
15 * network driver for the ethernet contained within the GT64260
16 * chip. It has been modified to fit into the U-Boot framework, from
17 * the original (etherboot) setup. Also, additional cleanup and features
18 * were added.
19 *
20 * - Josh Huber <huber@mclx.com>
21 */
22
23#include <common.h>
24#include <malloc.h>
25#include <cmd_bsp.h>
26#include <galileo/gt64260R.h>
27#include <galileo/core.h>
28#include <asm/cache.h>
29#include <miiphy.h>
30#include <net.h>
31
32#include "eth.h"
33#include "eth_addrtbl.h"
34
35#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI)
36
37#define GT6426x_ETH_BUF_SIZE 1536
38
39/* if you like verbose output, turn this on! */
40#undef DEBUG
41
42/* Restart autoneg if we detect link is up on phy init. */
43
44/*
45 * The GT doc's say that after Rst is deasserted, and the PHY
46 * reports autoneg complete, it runs through its autoneg
47 * procedures. This doesn't seem to be the case for MII
48 * PHY's. To work around this check for link up && autoneg
49 * complete when initilizing the port. If they are both set,
50 * then restart PHY autoneg. Of course, it may be something
51 * completly different.
52 */
53#ifdef CONFIG_ETHER_PORT_MII
54# define RESTART_AUTONEG
55#endif
56
57/* do this if you dont want to use snooping */
58#define USE_SOFTWARE_CACHE_MANAGEMENT
59
60#ifdef USE_SOFTWARE_CACHE_MANAGEMENT
61#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
62#define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
63#define INVALIDATE_DCACHE(a,b) if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
64#else
65/* bummer - w/o flush, nothing works, even with snooping - FIXME */
66/* #define FLUSH_DCACHE(a,b) */
67#define FLUSH_DCACHE(a,b) if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
68#define FLUSH_AND_INVALIDATE_DCACHE(a,b)
69#define INVALIDATE_DCACHE(a,b)
70#endif
71struct eth_dev_s {
72 eth0_tx_desc_single *eth_tx_desc;
73 eth0_rx_desc_single *eth_rx_desc;
74 char *eth_tx_buffer;
75 char *eth_rx_buffer[NR];
76 int tdn, rdn;
77 int dev;
78 unsigned int reg_base;
79};
80
81
82#ifdef CONFIG_INTEL_LXT97X
83/* for intel LXT972 */
84static const char ether_port_phy_addr[3]={0,1,2};
85#else
86static const char ether_port_phy_addr[3]={4,5,6};
87#endif
88
89
90static inline unsigned short
91miiphy_read_ret(unsigned short phy, unsigned short reg)
92{
93 unsigned short val;
94 miiphy_read(phy,reg,&val);
95 return val;
96}
97
98
99/**************************************************************************
100RESET - Reset adapter
101***************************************************************************/
102void
103gt6426x_eth_reset(void *v)
104{
105 /* we should do something here...
106 struct eth_device *wp = (struct eth_device *)v;
107 struct eth_dev_s *p = wp->priv;
108 */
109
110 printf ("RESET\n");
111 /* put the card in its initial state */
112}
113
114static void gt6426x_handle_SMI(struct eth_dev_s *p, unsigned int icr)
115{
116#ifdef DEBUG
117 printf("SMI interrupt: ");
118
119 if(icr&0x20000000) {
120 printf("SMI done\n");
121 }
122#endif
123
124 if(icr&0x10000000) {
125 unsigned int psr;
126 psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base);
127#ifdef DEBUG
128 printf("PHY state change:\n"
129 " GT:%s:%s:%s:%s\n",
130 psr&1?"100":" 10",
131 psr&8?" Link":"nLink",
132 psr&2?"FD":"HD",
133 psr&4?" FC":"nFC");
134
135#ifdef CONFIG_INTEL_LXT97X /* non-standard mii reg (intel lxt972a) */
136 {
137 unsigned short mii_11;
138 mii_11=miiphy_read_ret(ether_port_phy_addr[p->dev],0x11);
139
140 printf(" mii:%s:%s:%s:%s %s:%s %s\n",
141 mii_11&(1<<14)?"100":" 10",
142 mii_11&(1<<10)?" Link":"nLink",
143 mii_11&(1<<9)?"FD":"HD",
144 mii_11&(1<<4)?" FC":"nFC",
145
146 mii_11&(1<<7)?"ANc":"ANnc",
147 mii_11&(1<<8)?"AN":"Manual",
148 ""
149 );
150 }
151#endif /* CONFIG_INTEL_LXT97X */
152#endif /* DEBUG */
153 }
154}
155
156static int
157gt6426x_eth_receive(struct eth_dev_s *p,unsigned int icr)
158{
159 int eth_len=0;
160 char *eth_data;
161
162 eth0_rx_desc_single *rx=&p->eth_rx_desc[(p->rdn)];
163
164 INVALIDATE_DCACHE((unsigned int)rx,(unsigned int)(rx+1));
165
166 if (rx->command_status & 0x80000000) {
167 return 0; /* No packet received */
168 }
169
170 eth_len = (unsigned int)
171 (rx->buff_size_byte_count) & 0x0000ffff;
172 eth_data = (char *) p->eth_rx_buffer[p->rdn];
173
174#ifdef DEBUG
175 if (eth_len) {
176 printf ("%s: Recived %d byte Packet @ 0x%p\n",
177 __FUNCTION__, eth_len, eth_data);
178 }
179#endif
180 /*
181 * packet is now in:
182 * eth0_rx_buffer[RDN_ETH0];
183 */
184
185 /* let the upper layer handle the packet */
186 NetReceive (eth_data, eth_len);
187
188 rx->buff_size_byte_count = GT6426x_ETH_BUF_SIZE<<16;
189
190
191 /* GT96100 Owner */
192 rx->command_status = 0x80000000;
193
194 FLUSH_DCACHE((unsigned int)rx,(unsigned int)(rx+1));
195
196 p->rdn ++;
197 if (p->rdn == NR) {p->rdn = 0;}
198
199 sync();
200
201 /* Start Rx*/
202 GT_REG_WRITE (ETHERNET0_SDMA_COMMAND_REGISTER + p->reg_base, 0x00000080);
203
204#ifdef DEBUG
205 {
206 int i;
207 for (i=0;i<12;i++) {
208 printf(" %02x", eth_data[i]);
209 }
210 }
211 printf(": %d bytes\n", eth_len);
212#endif
213 INVALIDATE_DCACHE((unsigned int)eth_data,
214 (unsigned int)eth_data+eth_len);
215 return eth_len;
216}
217
218/**************************************************************************
219POLL - look for an rx frame, handle other conditions
220***************************************************************************/
221int
222gt6426x_eth_poll(void *v)
223{
224 struct eth_device *wp = (struct eth_device *)v;
225 struct eth_dev_s *p = wp->priv;
226 unsigned int icr=GTREGREAD(ETHERNET0_INTERRUPT_CAUSE_REGISTER + p->reg_base);
227
228 if(icr) {
229 GT_REG_WRITE(ETHERNET0_INTERRUPT_CAUSE_REGISTER +p->reg_base, 0);
230#ifdef DEBUG
231 printf("poll got ICR %08x\n", icr);
232#endif
233 /* SMI done or PHY state change*/
234 if(icr&0x30000000) gt6426x_handle_SMI(p, icr);
235 }
236 /* always process. We aren't using RX interrupts */
237 return gt6426x_eth_receive(p, icr);
238}
239
240/**************************************************************************
241TRANSMIT - Transmit a frame
242***************************************************************************/
243int
244gt6426x_eth_transmit(void *v, volatile char *p, unsigned int s)
245{
246 struct eth_device *wp = (struct eth_device *)v;
247 struct eth_dev_s *dev = (struct eth_dev_s *)wp->priv;
248#ifdef DEBUG
249 unsigned int old_command_stat,old_psr;
250#endif
251 eth0_tx_desc_single *tx=&dev->eth_tx_desc[dev->tdn];
252
253 /* wait for tx to be ready */
254 INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1));
255 while (tx->command_status & 0x80000000) {
256 int i;
257 for(i=0;i<1000;i++);
258 INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1));
259 }
260
261 GT_REG_WRITE (ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + dev->reg_base,
262 (unsigned int)tx);
263
264#ifdef DEBUG
265 printf("copying to tx_buffer [%p], length %x, desc = %p\n",
266 dev->eth_tx_buffer, s, dev->eth_tx_desc);
267#endif
268 memcpy(dev->eth_tx_buffer, (char *) p, s);
269
270 tx->buff_pointer = dev->eth_tx_buffer;
271 tx->bytecount_reserved = ((__u16)s) << 16;
272
273 /* 31 - own
274 * 22 - gencrc
275 * 18:16 - pad, last, first */
276 tx->command_status = (1<<31) | (1<<22) | (7<<16);
277#if 0
278 /* FEr #18 */
279 tx->next_desc = NULL;
280#else
281 tx->next_desc =
282 (struct eth0_tx_desc_struct *)
283 &dev->eth_tx_desc[(dev->tdn+1)%NT].bytecount_reserved;
284
285 /* cpu owned */
286 dev->eth_tx_desc[(dev->tdn+1)%NT].command_status = (7<<16); /* pad, last, first */
287#endif
288
289#ifdef DEBUG
290 old_command_stat=tx->command_status,
291 old_psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + dev->reg_base);
292#endif
293
294 FLUSH_DCACHE((unsigned int)tx,
295 (unsigned int)&dev->eth_tx_desc[(dev->tdn+2)%NT]);
296
297 FLUSH_DCACHE((unsigned int)dev->eth_tx_buffer,(unsigned int)dev->eth_tx_buffer+s);
298
299 GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + dev->reg_base, 0x01000000);
300
301#ifdef DEBUG
302 {
303 unsigned int command_stat=0;
304 printf("cmd_stat: %08x PSR: %08x\n", old_command_stat, old_psr);
305 /* wait for tx to be ready */
306 do {
307 unsigned int psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + dev->reg_base);
308 command_stat=tx->command_status;
309 if(command_stat!=old_command_stat || psr !=old_psr) {
310 printf("cmd_stat: %08x PSR: %08x\n", command_stat, psr);
311 old_command_stat = command_stat;
312 old_psr = psr;
313 }
314 /* gt6426x_eth0_poll(); */
315 } while (command_stat & 0x80000000);
316
317 printf("sent %d byte frame\n", s);
318
319 if((command_stat & (3<<15)) == 3) {
320 printf("frame had error (stat=%08x)\n", command_stat);
321 }
322 }
323#endif
324 return 0;
325}
326
327/**************************************************************************
328DISABLE - Turn off ethernet interface
329***************************************************************************/
330void
331gt6426x_eth_disable(void *v)
332{
333 struct eth_device *wp = (struct eth_device *)v;
334 struct eth_dev_s *p = (struct eth_dev_s *)wp->priv;
335
336 GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + p->reg_base, 0x80008000);
337}
338
339/**************************************************************************
340MII utilities - write: write to an MII register via SMI
341***************************************************************************/
342int
343miiphy_write(unsigned char phy, unsigned char reg,
344 unsigned short data)
345{
346 unsigned int temp= (reg<<21) | (phy<<16) | data;
347
348 while(GTREGREAD(ETHERNET_SMI_REGISTER) & (1<<28)); /* wait for !Busy */
349
350 GT_REG_WRITE(ETHERNET_SMI_REGISTER, temp);
351 return 0;
352}
353
354/**************************************************************************
355MII utilities - read: read from an MII register via SMI
356***************************************************************************/
357int
358miiphy_read(unsigned char phy, unsigned char reg,
359 unsigned short *val)
360{
361 unsigned int temp= (reg<<21) | (phy<<16) | 1<<26;
362
363 while(GTREGREAD(ETHERNET_SMI_REGISTER) & (1<<28)); /* wait for !Busy */
364
365 GT_REG_WRITE(ETHERNET_SMI_REGISTER, temp);
366
367 while(1) {
368 temp=GTREGREAD(ETHERNET_SMI_REGISTER);
369 if(temp & (1<<27)) break; /* wait for ReadValid */
370 }
371 *val = temp & 0xffff;
372
373 return 0;
374}
375
376#ifdef DEBUG
377/**************************************************************************
378MII utilities - dump mii registers
379***************************************************************************/
380static void
381gt6426x_dump_mii(bd_t *bis, unsigned short phy)
382{
383 printf("mii reg 0 - 3: %04x %04x %04x %04x\n",
384 miiphy_read_ret(phy, 0x0),
385 miiphy_read_ret(phy, 0x1),
386 miiphy_read_ret(phy, 0x2),
387 miiphy_read_ret(phy, 0x3)
388 );
389 printf(" 4 - 7: %04x %04x %04x %04x\n",
390 miiphy_read_ret(phy, 0x4),
391 miiphy_read_ret(phy, 0x5),
392 miiphy_read_ret(phy, 0x6),
393 miiphy_read_ret(phy, 0x7)
394 );
395 printf(" 8: %04x\n",
396 miiphy_read_ret(phy, 0x8)
397 );
398 printf(" 16-19: %04x %04x %04x %04x\n",
399 miiphy_read_ret(phy, 0x10),
400 miiphy_read_ret(phy, 0x11),
401 miiphy_read_ret(phy, 0x12),
402 miiphy_read_ret(phy, 0x13)
403 );
404 printf(" 20,30: %04x %04x\n",
405 miiphy_read_ret(phy, 20),
406 miiphy_read_ret(phy, 30)
407 );
408}
409#endif
410
411#ifdef RESTART_AUTONEG
412
413/* If link is up && autoneg compleate, and if
414 * GT and PHY disagree about link capabilitys,
415 * restart autoneg - something screwy with FD/HD
416 * unless we do this. */
417static void
418check_phy_state(struct eth_dev_s *p)
419{
420 int bmsr = miiphy_read_ret(ether_port_phy_addr[p->dev], PHY_BMSR);
421 int psr = GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base);
422
423 if ((psr & 1<<3) && (bmsr & PHY_BMSR_LS)) {
424 int nego = miiphy_read_ret(ether_port_phy_addr[p->dev], PHY_ANAR) &
425 miiphy_read_ret(ether_port_phy_addr[p->dev], PHY_ANLPAR);
426 int want;
427
428 if (nego & PHY_ANLPAR_TXFD) {
429 want = 0x3;
430 printf("MII: 100Base-TX, Full Duplex\n");
431 } else if (nego & PHY_ANLPAR_TX) {
432 want = 0x1;
433 printf("MII: 100Base-TX, Half Duplex\n");
434 } else if (nego & PHY_ANLPAR_10FD) {
435 want = 0x2;
436 printf("MII: 10Base-T, Full Duplex\n");
437 } else if (nego & PHY_ANLPAR_10) {
438 want = 0x0;
439 printf("MII: 10Base-T, Half Duplex\n");
440 } else {
441 printf("MII: Unknown link-foo! %x\n", nego);
442 return;
443 }
444
445 if ((psr & 0x3) != want) {
446 printf("MII: GT thinks %x, PHY thinks %x, restarting autoneg..\n",
447 psr & 0x3, want);
448 miiphy_write(ether_port_phy_addr[p->dev],0,
449 miiphy_read_ret(ether_port_phy_addr[p->dev],0) | (1<<9));
450 udelay(10000); /* the EVB's GT takes a while to notice phy
451 went down and up */
452 }
453 }
454}
455#endif
456
457/**************************************************************************
458PROBE - Look for an adapter, this routine's visible to the outside
459***************************************************************************/
460int
461gt6426x_eth_probe(void *v, bd_t *bis)
462{
463 struct eth_device *wp = (struct eth_device *)v;
464 struct eth_dev_s *p = (struct eth_dev_s *)wp->priv;
465 int dev = p->dev;
466 unsigned int reg_base = p->reg_base;
467 unsigned long temp;
468 int i;
469
470 if (( dev < 0 ) || ( dev >= GAL_ETH_DEVS ))
471 { /* This should never happen */
472 printf("%s: Invalid device %d\n", __FUNCTION__, dev );
473 return 0;
474 }
475
476#ifdef DEBUG
477 printf ("%s: initializing %s\n", __FUNCTION__, wp->name );
478 printf ("\nCOMM_CONTROL = %08x , COMM_CONF = %08x\n",
479 GTREGREAD(COMM_UNIT_ARBITER_CONTROL),
480 GTREGREAD(COMM_UNIT_ARBITER_CONFIGURATION_REGISTER));
481#endif
482
483 /* clear MIB counters */
484 for(i=0;i<255; i++)
485 temp=GTREGREAD(ETHERNET0_MIB_COUNTER_BASE + reg_base +i);
486
487#ifdef CONFIG_INTEL_LXT97X
488 /* for intel LXT972 */
489
490 /* led 1: 0x1=txact
491 led 2: 0xc=link/rxact
492 led 3: 0x2=rxact (N/C)
493 strch: 0,2=30 ms, enable */
494 miiphy_write(ether_port_phy_addr[p->dev], 20, 0x1c22);
495
496 /* 2.7ns port rise time */
497 /*miiphy_write(ether_port_phy_addr[p->dev], 30, 0x0<<10); */
498#else
499 /* already set up in mpsc.c */
500 /*GT_REG_WRITE(MAIN_ROUTING_REGISTER, 0x7ffe38); / b400 */
501
502 /* already set up in sdram_init.S... */
503 /* MPSC0, MPSC1, RMII */
504 /*GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, 0x1102); / f010 */
505#endif
506 GT_REG_WRITE(ETHERNET_PHY_ADDRESS_REGISTER,
507 ether_port_phy_addr[0] |
508 (ether_port_phy_addr[1]<<5) |
509 (ether_port_phy_addr[2]<<10)); /* 2000 */
510
511 /* 13:12 - 10: 4x64bit burst (cache line size = 32 bytes)
512 * 9 - 1: RIFB - interrupt on frame boundaries only
513 * 6:7 - 00: big endian rx and tx
514 * 5:2 - 1111: 15 retries */
515 GT_REG_WRITE(ETHERNET0_SDMA_CONFIGURATION_REGISTER + reg_base,
516 (2<<12) | (1<<9) | (0xf<<2) ); /* 2440 */
517
518#ifndef USE_SOFTWARE_CACHE_MANAGEMENT
519 /* enable rx/tx desc/buffer cache snoop */
520 GT_REG_READ(ETHERNET_0_ADDRESS_CONTROL_LOW + dev*0x20,
521 &temp); /* f200 */
522 temp|= (1<<6)| (1<<14)| (1<<22)| (1<<30);
523 GT_REG_WRITE(ETHERNET_0_ADDRESS_CONTROL_LOW + dev*0x20,
524 temp);
525#endif
526
527 /* 31 28 27 24 23 20 19 16
528 * 0000 0000 0000 0000 [0004]
529 * 15 12 11 8 7 4 3 0
530 * 1000 1101 0000 0000 [4d00]
531 * 20 - 0=MII 1=RMII
532 * 19 - 0=speed autoneg
533 * 15:14 - framesize 1536 (GT6426x_ETH_BUF_SIZE)
534 * 11 - no force link pass
535 * 10 - 1=disable fctl autoneg
536 * 8 - override prio ?? */
537 temp = 0x00004d00;
538#ifndef CONFIG_ETHER_PORT_MII
539 temp |= (1<<20); /* RMII */
540#endif
541 /* set En */
542 GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + reg_base,
543 temp); /* 2408 */
544
545 /* hardcode E1 also? */
546 /* -- according to dox, this is safer due to extra pulldowns? */
547 if (dev<2) {
548 GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + (dev+1) * 0x400,
549 temp); /* 2408 */
550 }
551
552 /* wake up MAC */ /* 2400 */
553 GT_REG_READ(ETHERNET0_PORT_CONFIGURATION_REGISTER + reg_base, &temp);
554 temp |= (1<<7); /* enable port */
555#ifdef CONFIG_GT_USE_MAC_HASH_TABLE
556 temp |= (1<<12); /* hash size 1/2k */
557#else
558 temp |= 1; /* promisc */
559#endif
560 GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_REGISTER + reg_base, temp);
561 /* 2400 */
562
563#ifdef RESTART_AUTONEG
564 check_phy_state(p);
565#endif
566
567 printf("%s: Waiting for link up..\n", wp->name);
568 temp = 10 * 1000;
569 /* wait for link back up */
570 while(!(GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + reg_base) & 8)
571 && (--temp > 0)){
572 udelay(1000); /* wait 1 ms */
573 }
574 if ( temp == 0) {
575 printf("%s: Failed!\n", wp->name);
576 return (0);
577 }
578
579 printf("%s: OK!\n", wp->name);
580
581 p->tdn = 0;
582 p->rdn = 0;
583 p->eth_tx_desc[p->tdn].command_status = 0;
584
585 /* Initialize Rx Side */
586 for (temp = 0; temp < NR; temp++) {
587 p->eth_rx_desc[temp].buff_pointer = p->eth_rx_buffer[temp];
588 p->eth_rx_desc[temp].buff_size_byte_count = GT6426x_ETH_BUF_SIZE<<16;
589
590 /* GT96100 Owner */
591 p->eth_rx_desc[temp].command_status = 0x80000000;
592 p->eth_rx_desc[temp].next_desc =
593 (struct eth0_rx_desc_struct *)
594 &p->eth_rx_desc[(temp+1)%NR].buff_size_byte_count;
595 }
596
597 FLUSH_DCACHE((unsigned int)&p->eth_tx_desc[0],
598 (unsigned int)&p->eth_tx_desc[NR]);
599 FLUSH_DCACHE((unsigned int)&p->eth_rx_desc[0],
600 (unsigned int)&p->eth_rx_desc[NR]);
601
602 GT_REG_WRITE(ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + reg_base,
603 (unsigned int) p->eth_tx_desc);
604 GT_REG_WRITE(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 + reg_base,
605 (unsigned int) p->eth_rx_desc);
606 GT_REG_WRITE(ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 + reg_base,
607 (unsigned int) p->eth_rx_desc);
608
609#ifdef DEBUG
610 printf ("\nRx descriptor pointer is %08x %08x\n",
611 GTREGREAD(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 + reg_base),
612 GTREGREAD(ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 + reg_base));
613 printf ("\n\n%08x %08x\n",
614 (unsigned int)p->eth_rx_desc,p->eth_rx_desc[0].command_status);
615
616 printf ("Descriptor dump:\n");
617 printf ("cmd status: %08x\n",p->eth_rx_desc[0].command_status);
618 printf ("byte_count: %08x\n",p->eth_rx_desc[0].buff_size_byte_count);
619 printf ("buff_ptr: %08x\n",(unsigned int)p->eth_rx_desc[0].buff_pointer);
620 printf ("next_desc: %08x\n\n",(unsigned int)p->eth_rx_desc[0].next_desc);
621 printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x0));
622 printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x4));
623 printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x8));
624 printf ("%08x\n\n",
625 *(unsigned int *) ((unsigned int)p->eth_rx_desc + 0xc));
626#endif
627
628#ifdef DEBUG
629 gt6426x_dump_mii(bis,ether_port_phy_addr[p->dev]);
630#endif
631
632#ifdef CONFIG_GT_USE_MAC_HASH_TABLE
633 {
634 unsigned int hashtable_base;
635 u8 *b = (u8 *)(wp->enetaddr);
636 u32 macH, macL;
637
638 /* twist the MAC up into the way the discovery wants it */
639 macH= (b[0]<<8) | b[1];
640 macL= (b[2]<<24) | (b[3]<<16) | (b[4]<<8) | b[5];
641
642 /* mode 0, size 0x800 */
643 hashtable_base =initAddressTable(dev,0,1);
644
645 if(!hashtable_base) {
646 printf("initAddressTable failed\n");
647 return 0;
648 }
649
650 addAddressTableEntry(dev, macH, macL, 1, 0);
651 GT_REG_WRITE(ETHERNET0_HASH_TABLE_POINTER_REGISTER + reg_base,
652 hashtable_base);
653 }
654#endif
655
656 /* Start Rx*/
657 GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + reg_base, 0x00000080);
658 printf("%s: gt6426x eth device %d init success \n", wp->name, dev );
659 return 1;
660}
661
662/* enter all the galileo ethernet devs into MULTI-BOOT */
663void
664gt6426x_eth_initialize(bd_t *bis)
665{
666 struct eth_device *dev;
667 struct eth_dev_s *p;
668 int devnum, x, temp;
669 char *s, *e, buf[64];
670
671#ifdef DEBUG
672 printf( "\n%s\n", __FUNCTION );
673#endif
674
675 for (devnum = 0; devnum < GAL_ETH_DEVS; devnum++) {
676 dev = calloc(sizeof(*dev), 1);
677 if (!dev) {
678 printf( "%s: gal_enet%d allocation failure, %s\n",
679 __FUNCTION__, devnum, "eth_device structure");
680 return;
681 }
682
683 /* must be less than NAMESIZE (16) */
684 sprintf(dev->name, "gal_enet%d", devnum);
685
686#ifdef DEBUG
687 printf( "Initializing %s\n", dev->name );
688#endif
689
690 /* Extract the MAC address from the environment */
691 switch (devnum)
692 {
693 case 0: s = "ethaddr"; break;
694#if (GAL_ETH_DEVS > 1)
695 case 1: s = "eth1addr"; break;
696#endif
697#if (GAL_ETH_DEVS > 2)
698 case 2: s = "eth2addr"; break;
699#endif
700 default: /* this should never happen */
701 printf( "%s: Invalid device number %d\n",
702 __FUNCTION__, devnum );
703 return;
704 }
705
706 temp = getenv_r (s, buf, sizeof(buf));
707 s = (temp > 0) ? buf : NULL;
708
709#ifdef DEBUG
710 printf ("Setting MAC %d to %s\n", devnum, s );
711#endif
712 for (x = 0; x < 6; ++x) {
713 dev->enetaddr[x] = s ? simple_strtoul(s, &e, 16) : 0;
714 if (s)
715 s = (*e) ? e+1 : e;
716 }
717
718 dev->init = (void*)gt6426x_eth_probe;
719 dev->halt = (void*)gt6426x_eth_reset;
720 dev->send = (void*)gt6426x_eth_transmit;
721 dev->recv = (void*)gt6426x_eth_poll;
722
723 dev->priv = (void*)p = calloc( sizeof(*p), 1 );
724 if (!p)
725 {
726 printf( "%s: %s allocation failure, %s\n",
727 __FUNCTION__, dev->name, "Private Device Structure");
728 free(dev);
729 return;
730 }
731
732 p->dev = devnum;
733 p->tdn=0;
734 p->rdn=0;
735 p->reg_base = devnum * ETHERNET_PORTS_DIFFERENCE_OFFSETS;
736
737 p->eth_tx_desc =
738 (eth0_tx_desc_single *)
739 (((unsigned int) malloc(sizeof (eth0_tx_desc_single) *
740 (NT+1)) & 0xfffffff0) + 0x10);
741 if (!p)
742 {
743 printf( "%s: %s allocation failure, %s\n",
744 __FUNCTION__, dev->name, "Tx Descriptor");
745 free(dev);
746 return;
747 }
748
749 p->eth_rx_desc =
750 (eth0_rx_desc_single *)
751 (((unsigned int) malloc(sizeof (eth0_rx_desc_single) *
752 (NR+1)) & 0xfffffff0) + 0x10);
753 if (!p->eth_rx_desc)
754 {
755 printf( "%s: %s allocation failure, %s\n",
756 __FUNCTION__, dev->name, "Rx Descriptor");
757 free(dev);
758 free(p);
759 return;
760 }
761
762 p->eth_tx_buffer =
763 (char *) (((unsigned int) malloc(GT6426x_ETH_BUF_SIZE) & 0xfffffff0) + 0x10);
764 if (!p->eth_tx_buffer)
765 {
766 printf( "%s: %s allocation failure, %s\n",
767 __FUNCTION__, dev->name, "Tx Bufffer");
768 free(dev);
769 free(p);
770 free(p->eth_rx_desc);
771 return;
772 }
773
774 for (temp = 0 ; temp < NR ; temp ++) {
775 p->eth_rx_buffer[temp] =
776 (char *)
777 (((unsigned int) malloc(GT6426x_ETH_BUF_SIZE) & 0xfffffff0) + 0x10);
778 if (!p->eth_rx_buffer[temp])
779 {
780 printf( "%s: %s allocation failure, %s\n",
781 __FUNCTION__, dev->name, "Rx Buffers");
782 free(dev);
783 free(p);
784 free(p->eth_tx_buffer);
785 free(p->eth_rx_desc);
786 free(p->eth_tx_desc);
787 while (temp >= 0)
788 free(p->eth_rx_buffer[--temp]);
789 return;
790 }
791 }
792
793
794 eth_register(dev);
795 }
796}
797#endif /* CFG_CMD_NET && CONFIG_NET_MULTI */