Gitiles
Code Review Sign In
gerrit.cesnet.cz / github / trini / u-boot / 44abcf6060db33e1f567dead02df92fecc01f299 / . / arch / arm / dts / stm32mp15-ddr.dtsi
blob: 0aac9131a602fbec940a2350d9f9e9dfacb13348 [file] [log] [blame]
Tom Rini4549e782018-05-06 18:27:01 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100[diff] [blame]2/*
3 * Copyright : STMicroelectronics 2018
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100[diff] [blame]4 */
Marek Vasuta8c97f42020-04-22 13:18:13 +0200[diff] [blame]5#include <linux/stringify.h>
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100[diff] [blame]6
Marek Vasuta8c97f42020-04-22 13:18:13 +0200[diff] [blame]7&ddr {
8 config-DDR_MEM_COMPATIBLE {
9 u-boot,dm-pre-reloc;
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100[diff] [blame]10
Marek Vasuta8c97f42020-04-22 13:18:13 +0200[diff] [blame]11 compatible = __stringify(st,DDR_MEM_COMPATIBLE);
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100[diff] [blame]12
Marek Vasuta8c97f42020-04-22 13:18:13 +0200[diff] [blame]13 st,mem-name = DDR_MEM_NAME;
14 st,mem-speed = <DDR_MEM_SPEED>;
15 st,mem-size = <DDR_MEM_SIZE>;
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100[diff] [blame]16
Marek Vasuta8c97f42020-04-22 13:18:13 +0200[diff] [blame]17 st,ctl-reg = <
18 DDR_MSTR
19 DDR_MRCTRL0
20 DDR_MRCTRL1
21 DDR_DERATEEN
22 DDR_DERATEINT
23 DDR_PWRCTL
24 DDR_PWRTMG
25 DDR_HWLPCTL
26 DDR_RFSHCTL0
27 DDR_RFSHCTL3
28 DDR_CRCPARCTL0
29 DDR_ZQCTL0
30 DDR_DFITMG0
31 DDR_DFITMG1
32 DDR_DFILPCFG0
33 DDR_DFIUPD0
34 DDR_DFIUPD1
35 DDR_DFIUPD2
36 DDR_DFIPHYMSTR
37 DDR_ODTMAP
38 DDR_DBG0
39 DDR_DBG1
40 DDR_DBGCMD
41 DDR_POISONCFG
42 DDR_PCCFG
43 >;
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100[diff] [blame]44
Marek Vasuta8c97f42020-04-22 13:18:13 +0200[diff] [blame]45 st,ctl-timing = <
46 DDR_RFSHTMG
47 DDR_DRAMTMG0
48 DDR_DRAMTMG1
49 DDR_DRAMTMG2
50 DDR_DRAMTMG3
51 DDR_DRAMTMG4
52 DDR_DRAMTMG5
53 DDR_DRAMTMG6
54 DDR_DRAMTMG7
55 DDR_DRAMTMG8
56 DDR_DRAMTMG14
57 DDR_ODTCFG
58 >;
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100[diff] [blame]59
Marek Vasuta8c97f42020-04-22 13:18:13 +0200[diff] [blame]60 st,ctl-map = <
61 DDR_ADDRMAP1
62 DDR_ADDRMAP2
63 DDR_ADDRMAP3
64 DDR_ADDRMAP4
65 DDR_ADDRMAP5
66 DDR_ADDRMAP6
67 DDR_ADDRMAP9
68 DDR_ADDRMAP10
69 DDR_ADDRMAP11
70 >;
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100[diff] [blame]71
Marek Vasuta8c97f42020-04-22 13:18:13 +0200[diff] [blame]72 st,ctl-perf = <
73 DDR_SCHED
74 DDR_SCHED1
75 DDR_PERFHPR1
76 DDR_PERFLPR1
77 DDR_PERFWR1
78 DDR_PCFGR_0
79 DDR_PCFGW_0
80 DDR_PCFGQOS0_0
81 DDR_PCFGQOS1_0
82 DDR_PCFGWQOS0_0
83 DDR_PCFGWQOS1_0
84 DDR_PCFGR_1
85 DDR_PCFGW_1
86 DDR_PCFGQOS0_1
87 DDR_PCFGQOS1_1
88 DDR_PCFGWQOS0_1
89 DDR_PCFGWQOS1_1
90 >;
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100[diff] [blame]91
Marek Vasuta8c97f42020-04-22 13:18:13 +0200[diff] [blame]92 st,phy-reg = <
93 DDR_PGCR
94 DDR_ACIOCR
95 DDR_DXCCR
96 DDR_DSGCR
97 DDR_DCR
98 DDR_ODTCR
99 DDR_ZQ0CR1
100 DDR_DX0GCR
101 DDR_DX1GCR
102 DDR_DX2GCR
103 DDR_DX3GCR
104 >;
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100[diff] [blame]105
Marek Vasuta8c97f42020-04-22 13:18:13 +0200[diff] [blame]106 st,phy-timing = <
107 DDR_PTR0
108 DDR_PTR1
109 DDR_PTR2
110 DDR_DTPR0
111 DDR_DTPR1
112 DDR_DTPR2
113 DDR_MR0
114 DDR_MR1
115 DDR_MR2
116 DDR_MR3
117 >;
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100[diff] [blame]118
Marek Vasuta8c97f42020-04-22 13:18:13 +0200[diff] [blame]119 status = "okay";
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100[diff] [blame]120 };
121};
Marek Vasuta8c97f42020-04-22 13:18:13 +0200[diff] [blame]122
123#undef DDR_MEM_COMPATIBLE
124#undef DDR_MEM_NAME
125#undef DDR_MEM_SPEED
126#undef DDR_MEM_SIZE
127
128#undef DDR_MSTR
129#undef DDR_MRCTRL0
130#undef DDR_MRCTRL1
131#undef DDR_DERATEEN
132#undef DDR_DERATEINT
133#undef DDR_PWRCTL
134#undef DDR_PWRTMG
135#undef DDR_HWLPCTL
136#undef DDR_RFSHCTL0
137#undef DDR_RFSHCTL3
138#undef DDR_RFSHTMG
139#undef DDR_CRCPARCTL0
140#undef DDR_DRAMTMG0
141#undef DDR_DRAMTMG1
142#undef DDR_DRAMTMG2
143#undef DDR_DRAMTMG3
144#undef DDR_DRAMTMG4
145#undef DDR_DRAMTMG5
146#undef DDR_DRAMTMG6
147#undef DDR_DRAMTMG7
148#undef DDR_DRAMTMG8
149#undef DDR_DRAMTMG14
150#undef DDR_ZQCTL0
151#undef DDR_DFITMG0
152#undef DDR_DFITMG1
153#undef DDR_DFILPCFG0
154#undef DDR_DFIUPD0
155#undef DDR_DFIUPD1
156#undef DDR_DFIUPD2
157#undef DDR_DFIPHYMSTR
158#undef DDR_ADDRMAP1
159#undef DDR_ADDRMAP2
160#undef DDR_ADDRMAP3
161#undef DDR_ADDRMAP4
162#undef DDR_ADDRMAP5
163#undef DDR_ADDRMAP6
164#undef DDR_ADDRMAP9
165#undef DDR_ADDRMAP10
166#undef DDR_ADDRMAP11
167#undef DDR_ODTCFG
168#undef DDR_ODTMAP
169#undef DDR_SCHED
170#undef DDR_SCHED1
171#undef DDR_PERFHPR1
172#undef DDR_PERFLPR1
173#undef DDR_PERFWR1
174#undef DDR_DBG0
175#undef DDR_DBG1
176#undef DDR_DBGCMD
177#undef DDR_POISONCFG
178#undef DDR_PCCFG
179#undef DDR_PCFGR_0
180#undef DDR_PCFGW_0
181#undef DDR_PCFGQOS0_0
182#undef DDR_PCFGQOS1_0
183#undef DDR_PCFGWQOS0_0
184#undef DDR_PCFGWQOS1_0
185#undef DDR_PCFGR_1
186#undef DDR_PCFGW_1
187#undef DDR_PCFGQOS0_1
188#undef DDR_PCFGQOS1_1
189#undef DDR_PCFGWQOS0_1
190#undef DDR_PCFGWQOS1_1
191#undef DDR_PGCR
192#undef DDR_PTR0
193#undef DDR_PTR1
194#undef DDR_PTR2
195#undef DDR_ACIOCR
196#undef DDR_DXCCR
197#undef DDR_DSGCR
198#undef DDR_DCR
199#undef DDR_DTPR0
200#undef DDR_DTPR1
201#undef DDR_DTPR2
202#undef DDR_MR0
203#undef DDR_MR1
204#undef DDR_MR2
205#undef DDR_MR3
206#undef DDR_ODTCR
207#undef DDR_ZQ0CR1
208#undef DDR_DX0GCR
Marek Vasuta8c97f42020-04-22 13:18:13 +0200[diff] [blame]209#undef DDR_DX1GCR
Marek Vasuta8c97f42020-04-22 13:18:13 +0200[diff] [blame]210#undef DDR_DX2GCR
Marek Vasuta8c97f42020-04-22 13:18:13 +0200[diff] [blame]211#undef DDR_DX3GCR