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gerrit.cesnet.cz / github / trini / u-boot / 433ff2bdbccc5190189528305e4ed6f7205dbafd / . / arch / i386 / cpu / interrupts.c
blob: 51023f3a86f0285ea047823d3b69a8f10c065154 [file] [log] [blame]
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]1/*
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]2 * (C) Copyright 2008
3 * Graeme Russ, graeme.russ@gmail.com.
4 *
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]5 * (C) Copyright 2002
6 * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
7 *
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame^]8 * Portions of this file are derived from the Linux kernel source
9 * Copyright (C) 1991, 1992 Linus Torvalds
10 *
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30#include <common.h>
Graeme Russ9933d602008-12-07 10:29:01 +1100[diff] [blame]31#include <asm/interrupt.h>
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]32
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]33#define DECLARE_INTERRUPT(x) \
34 ".globl irq_"#x"\n" \
Graeme Russ0fc1b492009-11-24 20:04:19 +1100[diff] [blame]35 ".hidden irq_"#x"\n" \
36 ".type irq_"#x", @function\n" \
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]37 "irq_"#x":\n" \
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]38 "pushl $"#x"\n" \
39 "jmp irq_common_entry\n"
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]40
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame^]41/*
42 * Volatile isn't enough to prevent the compiler from reordering the
43 * read/write functions for the control registers and messing everything up.
44 * A memory clobber would solve the problem, but would prevent reordering of
45 * all loads stores around it, which can hurt performance. Solution is to
46 * use a variable and mimic reads and writes to it to enforce serialization
47 */
48static unsigned long __force_order;
49
50static inline unsigned long read_cr0(void)
51{
52 unsigned long val;
53 asm volatile("mov %%cr0,%0\n\t" : "=r" (val), "=m" (__force_order));
54 return val;
55}
56
57static inline unsigned long read_cr2(void)
58{
59 unsigned long val;
60 asm volatile("mov %%cr2,%0\n\t" : "=r" (val), "=m" (__force_order));
61 return val;
62}
63
64static inline unsigned long read_cr3(void)
65{
66 unsigned long val;
67 asm volatile("mov %%cr3,%0\n\t" : "=r" (val), "=m" (__force_order));
68 return val;
69}
70
71static inline unsigned long read_cr4(void)
72{
73 unsigned long val;
74 asm volatile("mov %%cr4,%0\n\t" : "=r" (val), "=m" (__force_order));
75 return val;
76}
77
78static inline unsigned long get_debugreg(int regno)
79{
80 unsigned long val = 0; /* Damn you, gcc! */
81
82 switch (regno) {
83 case 0:
84 asm("mov %%db0, %0" :"=r" (val));
85 break;
86 case 1:
87 asm("mov %%db1, %0" :"=r" (val));
88 break;
89 case 2:
90 asm("mov %%db2, %0" :"=r" (val));
91 break;
92 case 3:
93 asm("mov %%db3, %0" :"=r" (val));
94 break;
95 case 6:
96 asm("mov %%db6, %0" :"=r" (val));
97 break;
98 case 7:
99 asm("mov %%db7, %0" :"=r" (val));
100 break;
101 default:
102 val = 0;
103 }
104 return val;
105}
106
107void dump_regs(struct pt_regs *regs)
108{
109 unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
110 unsigned long d0, d1, d2, d3, d6, d7;
111
112 printf("EIP: %04x:[<%08lx>] EFLAGS: %08lx\n",
113 (u16)regs->xcs, regs->eip, regs->eflags);
114
115 printf("EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
116 regs->eax, regs->ebx, regs->ecx, regs->edx);
117 printf("ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n",
118 regs->esi, regs->edi, regs->ebp, regs->esp);
119 printf(" DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x\n",
120 (u16)regs->xds, (u16)regs->xes, (u16)regs->xfs, (u16)regs->xgs, (u16)regs->xss);
121
122 cr0 = read_cr0();
123 cr2 = read_cr2();
124 cr3 = read_cr3();
125 cr4 = read_cr4();
126
127 printf("CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n",
128 cr0, cr2, cr3, cr4);
129
130 d0 = get_debugreg(0);
131 d1 = get_debugreg(1);
132 d2 = get_debugreg(2);
133 d3 = get_debugreg(3);
134
135 printf("DR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n",
136 d0, d1, d2, d3);
137
138 d6 = get_debugreg(6);
139 d7 = get_debugreg(7);
140 printf("DR6: %08lx DR7: %08lx\n",
141 d6, d7);
142}
143
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]144struct idt_entry {
145 u16 base_low;
146 u16 selector;
147 u8 res;
148 u8 access;
149 u16 base_high;
150} __attribute__ ((packed));
151
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]152struct desc_ptr {
153 unsigned short size;
154 unsigned long address;
155 unsigned short segment;
156} __attribute__((packed));
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]157
158struct idt_entry idt[256];
159
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]160struct desc_ptr idt_ptr;
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]161
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]162static inline void load_idt(const struct desc_ptr *dtr)
163{
164 asm volatile("cs lidt %0"::"m" (*dtr));
165}
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]166
Graeme Russabf0cd32009-02-24 21:13:40 +1100[diff] [blame]167void set_vector(u8 intnum, void *routine)
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]168{
Graeme Russ1c409bc2009-11-24 20:04:21 +1100[diff] [blame]169 idt[intnum].base_high = (u16)((u32)(routine) >> 16);
170 idt[intnum].base_low = (u16)((u32)(routine) & 0xffff);
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]171}
172
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]173void irq_0(void);
174void irq_1(void);
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]175
Graeme Russabf0cd32009-02-24 21:13:40 +1100[diff] [blame]176int cpu_init_interrupts(void)
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]177{
178 int i;
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]179
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]180 int irq_entry_size = irq_1 - irq_0;
181 void *irq_entry = (void *)irq_0;
182
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]183 /* Just in case... */
184 disable_interrupts();
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]185
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]186 /* Setup the IDT */
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]187 for (i=0;i<256;i++) {
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]188 idt[i].access = 0x8e;
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]189 idt[i].res = 0;
190 idt[i].selector = 0x10;
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]191 set_vector(i, irq_entry);
192 irq_entry += irq_entry_size;
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]193 }
194
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]195 idt_ptr.size = 256 * 8;
196 idt_ptr.address = (unsigned long) idt;
197 idt_ptr.segment = 0x18;
198
199 load_idt(&idt_ptr);
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]200
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]201 /* It is now safe to enable interrupts */
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]202 enable_interrupts();
203
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]204 return 0;
205}
206
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]207void __do_irq(int irq)
208{
209 printf("Unhandled IRQ : %d\n", irq);
210}
211void do_irq(int irq) __attribute__((weak, alias("__do_irq")));
212
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]213void enable_interrupts(void)
214{
215 asm("sti\n");
216}
217
218int disable_interrupts(void)
219{
220 long flags;
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]221
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]222 asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
wdenk8bde7f72003-06-27 21:31:46 +0000[diff] [blame]223
wdenk2262cfe2002-11-18 00:14:45 +0000[diff] [blame]224 return (flags&0x200); /* IE flags is bit 9 */
225}
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]226
227/* IRQ Low-Level Service Routine */
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame^]228__isr__ irq_llsr(struct pt_regs *regs)
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]229{
230 /*
231 * For detailed description of each exception, refer to:
232 * Intel® 64 and IA-32 Architectures Software Developer's Manual
233 * Volume 1: Basic Architecture
234 * Order Number: 253665-029US, November 2008
235 * Table 6-1. Exceptions and Interrupts
236 */
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame^]237 switch (regs->orig_eax) {
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]238 case 0x00:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame^]239 printf("Divide Error (Division by zero)\n");
240 dump_regs(regs);
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]241 while(1);
242 break;
243 case 0x01:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame^]244 printf("Debug Interrupt (Single step)\n");
245 dump_regs(regs);
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]246 break;
247 case 0x02:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame^]248 printf("NMI Interrupt\n");
249 dump_regs(regs);
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]250 break;
251 case 0x03:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame^]252 printf("Breakpoint\n");
253 dump_regs(regs);
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]254 break;
255 case 0x04:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame^]256 printf("Overflow\n");
257 dump_regs(regs);
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]258 while(1);
259 break;
260 case 0x05:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame^]261 printf("BOUND Range Exceeded\n");
262 dump_regs(regs);
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]263 while(1);
264 break;
265 case 0x06:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame^]266 printf("Invalid Opcode (UnDefined Opcode)\n");
267 dump_regs(regs);
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]268 while(1);
269 break;
270 case 0x07:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame^]271 printf("Device Not Available (No Math Coprocessor)\n");
272 dump_regs(regs);
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]273 while(1);
274 break;
275 case 0x08:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame^]276 printf("Double fault\n");
277 dump_regs(regs);
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]278 while(1);
279 break;
280 case 0x09:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame^]281 printf("Co-processor segment overrun\n");
282 dump_regs(regs);
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]283 while(1);
284 break;
285 case 0x0a:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame^]286 printf("Invalid TSS\n");
287 dump_regs(regs);
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]288 break;
289 case 0x0b:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame^]290 printf("Segment Not Present\n");
291 dump_regs(regs);
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]292 while(1);
293 break;
294 case 0x0c:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame^]295 printf("Stack Segment Fault\n");
296 dump_regs(regs);
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]297 while(1);
298 break;
299 case 0x0d:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame^]300 printf("General Protection\n");
301 dump_regs(regs);
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]302 break;
303 case 0x0e:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame^]304 printf("Page fault\n");
305 dump_regs(regs);
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]306 while(1);
307 break;
308 case 0x0f:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame^]309 printf("Floating-Point Error (Math Fault)\n");
310 dump_regs(regs);
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]311 break;
312 case 0x10:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame^]313 printf("Alignment check\n");
314 dump_regs(regs);
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]315 break;
316 case 0x11:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame^]317 printf("Machine Check\n");
318 dump_regs(regs);
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]319 break;
320 case 0x12:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame^]321 printf("SIMD Floating-Point Exception\n");
322 dump_regs(regs);
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]323 break;
324 case 0x13:
325 case 0x14:
326 case 0x15:
327 case 0x16:
328 case 0x17:
329 case 0x18:
330 case 0x19:
331 case 0x1a:
332 case 0x1b:
333 case 0x1c:
334 case 0x1d:
335 case 0x1e:
336 case 0x1f:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame^]337 printf("Reserved Exception\n");
338 dump_regs(regs);
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]339 break;
340
341 default:
342 /* Hardware or User IRQ */
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame^]343 do_irq(regs->orig_eax);
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]344 }
345}
346
347/*
348 * OK - This looks really horrible, but it serves a purpose - It helps create
349 * fully relocatable code.
350 * - The call to irq_llsr will be a relative jump
351 * - The IRQ entries will be guaranteed to be in order
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame^]352 * Interrupt entries are now very small (a push and a jump) but they are
353 * now slower (all registers pushed on stack which provides complete
354 * crash dumps in the low level handlers
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]355 */
356asm(".globl irq_common_entry\n" \
Graeme Russ0fc1b492009-11-24 20:04:19 +1100[diff] [blame]357 ".hidden irq_common_entry\n" \
358 ".type irq_common_entry, @function\n" \
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]359 "irq_common_entry:\n" \
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame^]360 "cld\n" \
361 "pushl %gs\n" \
362 "pushl %fs\n" \
363 "pushl %es\n" \
364 "pushl %ds\n" \
365 "pushl %eax\n" \
366 "pushl %ebp\n" \
367 "pushl %edi\n" \
368 "pushl %esi\n" \
369 "pushl %edx\n" \
370 "pushl %ecx\n" \
371 "pushl %ebx\n" \
372 "mov %esp, %eax\n" \
373 "pushl %ebp\n" \
374 "movl %esp,%ebp\n" \
375 "pushl %eax\n" \
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]376 "call irq_llsr\n" \
377 "popl %eax\n" \
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]378 "leave\n"\
Graeme Russ433ff2b2010-04-24 00:05:38 +1000[diff] [blame^]379 "popl %ebx\n" \
380 "popl %ecx\n" \
381 "popl %edx\n" \
382 "popl %esi\n" \
383 "popl %edi\n" \
384 "popl %ebp\n" \
385 "popl %eax\n" \
386 "popl %ds\n" \
387 "popl %es\n" \
388 "popl %fs\n" \
389 "popl %gs\n" \
390 "add $4, %esp\n" \
Graeme Russ564a9982009-11-24 20:04:18 +1100[diff] [blame]391 "iret\n" \
392 DECLARE_INTERRUPT(0) \
393 DECLARE_INTERRUPT(1) \
394 DECLARE_INTERRUPT(2) \
395 DECLARE_INTERRUPT(3) \
396 DECLARE_INTERRUPT(4) \
397 DECLARE_INTERRUPT(5) \
398 DECLARE_INTERRUPT(6) \
399 DECLARE_INTERRUPT(7) \
400 DECLARE_INTERRUPT(8) \
401 DECLARE_INTERRUPT(9) \
402 DECLARE_INTERRUPT(10) \
403 DECLARE_INTERRUPT(11) \
404 DECLARE_INTERRUPT(12) \
405 DECLARE_INTERRUPT(13) \
406 DECLARE_INTERRUPT(14) \
407 DECLARE_INTERRUPT(15) \
408 DECLARE_INTERRUPT(16) \
409 DECLARE_INTERRUPT(17) \
410 DECLARE_INTERRUPT(18) \
411 DECLARE_INTERRUPT(19) \
412 DECLARE_INTERRUPT(20) \
413 DECLARE_INTERRUPT(21) \
414 DECLARE_INTERRUPT(22) \
415 DECLARE_INTERRUPT(23) \
416 DECLARE_INTERRUPT(24) \
417 DECLARE_INTERRUPT(25) \
418 DECLARE_INTERRUPT(26) \
419 DECLARE_INTERRUPT(27) \
420 DECLARE_INTERRUPT(28) \
421 DECLARE_INTERRUPT(29) \
422 DECLARE_INTERRUPT(30) \
423 DECLARE_INTERRUPT(31) \
424 DECLARE_INTERRUPT(32) \
425 DECLARE_INTERRUPT(33) \
426 DECLARE_INTERRUPT(34) \
427 DECLARE_INTERRUPT(35) \
428 DECLARE_INTERRUPT(36) \
429 DECLARE_INTERRUPT(37) \
430 DECLARE_INTERRUPT(38) \
431 DECLARE_INTERRUPT(39) \
432 DECLARE_INTERRUPT(40) \
433 DECLARE_INTERRUPT(41) \
434 DECLARE_INTERRUPT(42) \
435 DECLARE_INTERRUPT(43) \
436 DECLARE_INTERRUPT(44) \
437 DECLARE_INTERRUPT(45) \
438 DECLARE_INTERRUPT(46) \
439 DECLARE_INTERRUPT(47) \
440 DECLARE_INTERRUPT(48) \
441 DECLARE_INTERRUPT(49) \
442 DECLARE_INTERRUPT(50) \
443 DECLARE_INTERRUPT(51) \
444 DECLARE_INTERRUPT(52) \
445 DECLARE_INTERRUPT(53) \
446 DECLARE_INTERRUPT(54) \
447 DECLARE_INTERRUPT(55) \
448 DECLARE_INTERRUPT(56) \
449 DECLARE_INTERRUPT(57) \
450 DECLARE_INTERRUPT(58) \
451 DECLARE_INTERRUPT(59) \
452 DECLARE_INTERRUPT(60) \
453 DECLARE_INTERRUPT(61) \
454 DECLARE_INTERRUPT(62) \
455 DECLARE_INTERRUPT(63) \
456 DECLARE_INTERRUPT(64) \
457 DECLARE_INTERRUPT(65) \
458 DECLARE_INTERRUPT(66) \
459 DECLARE_INTERRUPT(67) \
460 DECLARE_INTERRUPT(68) \
461 DECLARE_INTERRUPT(69) \
462 DECLARE_INTERRUPT(70) \
463 DECLARE_INTERRUPT(71) \
464 DECLARE_INTERRUPT(72) \
465 DECLARE_INTERRUPT(73) \
466 DECLARE_INTERRUPT(74) \
467 DECLARE_INTERRUPT(75) \
468 DECLARE_INTERRUPT(76) \
469 DECLARE_INTERRUPT(77) \
470 DECLARE_INTERRUPT(78) \
471 DECLARE_INTERRUPT(79) \
472 DECLARE_INTERRUPT(80) \
473 DECLARE_INTERRUPT(81) \
474 DECLARE_INTERRUPT(82) \
475 DECLARE_INTERRUPT(83) \
476 DECLARE_INTERRUPT(84) \
477 DECLARE_INTERRUPT(85) \
478 DECLARE_INTERRUPT(86) \
479 DECLARE_INTERRUPT(87) \
480 DECLARE_INTERRUPT(88) \
481 DECLARE_INTERRUPT(89) \
482 DECLARE_INTERRUPT(90) \
483 DECLARE_INTERRUPT(91) \
484 DECLARE_INTERRUPT(92) \
485 DECLARE_INTERRUPT(93) \
486 DECLARE_INTERRUPT(94) \
487 DECLARE_INTERRUPT(95) \
488 DECLARE_INTERRUPT(97) \
489 DECLARE_INTERRUPT(96) \
490 DECLARE_INTERRUPT(98) \
491 DECLARE_INTERRUPT(99) \
492 DECLARE_INTERRUPT(100) \
493 DECLARE_INTERRUPT(101) \
494 DECLARE_INTERRUPT(102) \
495 DECLARE_INTERRUPT(103) \
496 DECLARE_INTERRUPT(104) \
497 DECLARE_INTERRUPT(105) \
498 DECLARE_INTERRUPT(106) \
499 DECLARE_INTERRUPT(107) \
500 DECLARE_INTERRUPT(108) \
501 DECLARE_INTERRUPT(109) \
502 DECLARE_INTERRUPT(110) \
503 DECLARE_INTERRUPT(111) \
504 DECLARE_INTERRUPT(112) \
505 DECLARE_INTERRUPT(113) \
506 DECLARE_INTERRUPT(114) \
507 DECLARE_INTERRUPT(115) \
508 DECLARE_INTERRUPT(116) \
509 DECLARE_INTERRUPT(117) \
510 DECLARE_INTERRUPT(118) \
511 DECLARE_INTERRUPT(119) \
512 DECLARE_INTERRUPT(120) \
513 DECLARE_INTERRUPT(121) \
514 DECLARE_INTERRUPT(122) \
515 DECLARE_INTERRUPT(123) \
516 DECLARE_INTERRUPT(124) \
517 DECLARE_INTERRUPT(125) \
518 DECLARE_INTERRUPT(126) \
519 DECLARE_INTERRUPT(127) \
520 DECLARE_INTERRUPT(128) \
521 DECLARE_INTERRUPT(129) \
522 DECLARE_INTERRUPT(130) \
523 DECLARE_INTERRUPT(131) \
524 DECLARE_INTERRUPT(132) \
525 DECLARE_INTERRUPT(133) \
526 DECLARE_INTERRUPT(134) \
527 DECLARE_INTERRUPT(135) \
528 DECLARE_INTERRUPT(136) \
529 DECLARE_INTERRUPT(137) \
530 DECLARE_INTERRUPT(138) \
531 DECLARE_INTERRUPT(139) \
532 DECLARE_INTERRUPT(140) \
533 DECLARE_INTERRUPT(141) \
534 DECLARE_INTERRUPT(142) \
535 DECLARE_INTERRUPT(143) \
536 DECLARE_INTERRUPT(144) \
537 DECLARE_INTERRUPT(145) \
538 DECLARE_INTERRUPT(146) \
539 DECLARE_INTERRUPT(147) \
540 DECLARE_INTERRUPT(148) \
541 DECLARE_INTERRUPT(149) \
542 DECLARE_INTERRUPT(150) \
543 DECLARE_INTERRUPT(151) \
544 DECLARE_INTERRUPT(152) \
545 DECLARE_INTERRUPT(153) \
546 DECLARE_INTERRUPT(154) \
547 DECLARE_INTERRUPT(155) \
548 DECLARE_INTERRUPT(156) \
549 DECLARE_INTERRUPT(157) \
550 DECLARE_INTERRUPT(158) \
551 DECLARE_INTERRUPT(159) \
552 DECLARE_INTERRUPT(160) \
553 DECLARE_INTERRUPT(161) \
554 DECLARE_INTERRUPT(162) \
555 DECLARE_INTERRUPT(163) \
556 DECLARE_INTERRUPT(164) \
557 DECLARE_INTERRUPT(165) \
558 DECLARE_INTERRUPT(166) \
559 DECLARE_INTERRUPT(167) \
560 DECLARE_INTERRUPT(168) \
561 DECLARE_INTERRUPT(169) \
562 DECLARE_INTERRUPT(170) \
563 DECLARE_INTERRUPT(171) \
564 DECLARE_INTERRUPT(172) \
565 DECLARE_INTERRUPT(173) \
566 DECLARE_INTERRUPT(174) \
567 DECLARE_INTERRUPT(175) \
568 DECLARE_INTERRUPT(176) \
569 DECLARE_INTERRUPT(177) \
570 DECLARE_INTERRUPT(178) \
571 DECLARE_INTERRUPT(179) \
572 DECLARE_INTERRUPT(180) \
573 DECLARE_INTERRUPT(181) \
574 DECLARE_INTERRUPT(182) \
575 DECLARE_INTERRUPT(183) \
576 DECLARE_INTERRUPT(184) \
577 DECLARE_INTERRUPT(185) \
578 DECLARE_INTERRUPT(186) \
579 DECLARE_INTERRUPT(187) \
580 DECLARE_INTERRUPT(188) \
581 DECLARE_INTERRUPT(189) \
582 DECLARE_INTERRUPT(190) \
583 DECLARE_INTERRUPT(191) \
584 DECLARE_INTERRUPT(192) \
585 DECLARE_INTERRUPT(193) \
586 DECLARE_INTERRUPT(194) \
587 DECLARE_INTERRUPT(195) \
588 DECLARE_INTERRUPT(196) \
589 DECLARE_INTERRUPT(197) \
590 DECLARE_INTERRUPT(198) \
591 DECLARE_INTERRUPT(199) \
592 DECLARE_INTERRUPT(200) \
593 DECLARE_INTERRUPT(201) \
594 DECLARE_INTERRUPT(202) \
595 DECLARE_INTERRUPT(203) \
596 DECLARE_INTERRUPT(204) \
597 DECLARE_INTERRUPT(205) \
598 DECLARE_INTERRUPT(206) \
599 DECLARE_INTERRUPT(207) \
600 DECLARE_INTERRUPT(208) \
601 DECLARE_INTERRUPT(209) \
602 DECLARE_INTERRUPT(210) \
603 DECLARE_INTERRUPT(211) \
604 DECLARE_INTERRUPT(212) \
605 DECLARE_INTERRUPT(213) \
606 DECLARE_INTERRUPT(214) \
607 DECLARE_INTERRUPT(215) \
608 DECLARE_INTERRUPT(216) \
609 DECLARE_INTERRUPT(217) \
610 DECLARE_INTERRUPT(218) \
611 DECLARE_INTERRUPT(219) \
612 DECLARE_INTERRUPT(220) \
613 DECLARE_INTERRUPT(221) \
614 DECLARE_INTERRUPT(222) \
615 DECLARE_INTERRUPT(223) \
616 DECLARE_INTERRUPT(224) \
617 DECLARE_INTERRUPT(225) \
618 DECLARE_INTERRUPT(226) \
619 DECLARE_INTERRUPT(227) \
620 DECLARE_INTERRUPT(228) \
621 DECLARE_INTERRUPT(229) \
622 DECLARE_INTERRUPT(230) \
623 DECLARE_INTERRUPT(231) \
624 DECLARE_INTERRUPT(232) \
625 DECLARE_INTERRUPT(233) \
626 DECLARE_INTERRUPT(234) \
627 DECLARE_INTERRUPT(235) \
628 DECLARE_INTERRUPT(236) \
629 DECLARE_INTERRUPT(237) \
630 DECLARE_INTERRUPT(238) \
631 DECLARE_INTERRUPT(239) \
632 DECLARE_INTERRUPT(240) \
633 DECLARE_INTERRUPT(241) \
634 DECLARE_INTERRUPT(242) \
635 DECLARE_INTERRUPT(243) \
636 DECLARE_INTERRUPT(244) \
637 DECLARE_INTERRUPT(245) \
638 DECLARE_INTERRUPT(246) \
639 DECLARE_INTERRUPT(247) \
640 DECLARE_INTERRUPT(248) \
641 DECLARE_INTERRUPT(249) \
642 DECLARE_INTERRUPT(250) \
643 DECLARE_INTERRUPT(251) \
644 DECLARE_INTERRUPT(252) \
645 DECLARE_INTERRUPT(253) \
646 DECLARE_INTERRUPT(254) \
647 DECLARE_INTERRUPT(255));