blob: 22bfdd8dce61d03203ee06f1e81c7fd8ff32ce68 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Siva Durga Prasad Paladugu6b245012016-01-13 16:25:37 +05302/*
3 * (C) Copyright 2015 - 2016, Xilinx, Inc,
4 * Michal Simek <michal.simek@xilinx.com>
5 * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
Siva Durga Prasad Paladugu6b245012016-01-13 16:25:37 +05306 */
7
8#include <console.h>
9#include <common.h>
10#include <zynqmppl.h>
11#include <linux/sizes.h>
Siva Durga Prasad Paladugu7033ae22017-02-17 16:16:01 +053012#include <asm/arch/sys_proto.h>
Siva Durga Prasad Paladugu31bcb342018-03-15 00:17:24 +053013#include <memalign.h>
Siva Durga Prasad Paladugu6b245012016-01-13 16:25:37 +053014
15#define DUMMY_WORD 0xffffffff
16
17/* Xilinx binary format header */
18static const u32 bin_format[] = {
19 DUMMY_WORD, /* Dummy words */
20 DUMMY_WORD,
21 DUMMY_WORD,
22 DUMMY_WORD,
23 DUMMY_WORD,
24 DUMMY_WORD,
25 DUMMY_WORD,
26 DUMMY_WORD,
27 DUMMY_WORD,
28 DUMMY_WORD,
29 DUMMY_WORD,
30 DUMMY_WORD,
31 DUMMY_WORD,
32 DUMMY_WORD,
33 DUMMY_WORD,
34 DUMMY_WORD,
35 0x000000bb, /* Sync word */
36 0x11220044, /* Sync word */
37 DUMMY_WORD,
38 DUMMY_WORD,
39 0xaa995566, /* Sync word */
40};
41
42#define SWAP_NO 1
43#define SWAP_DONE 2
44
45/*
46 * Load the whole word from unaligned buffer
47 * Keep in your mind that it is byte loading on little-endian system
48 */
49static u32 load_word(const void *buf, u32 swap)
50{
51 u32 word = 0;
52 u8 *bitc = (u8 *)buf;
53 int p;
54
55 if (swap == SWAP_NO) {
56 for (p = 0; p < 4; p++) {
57 word <<= 8;
58 word |= bitc[p];
59 }
60 } else {
61 for (p = 3; p >= 0; p--) {
62 word <<= 8;
63 word |= bitc[p];
64 }
65 }
66
67 return word;
68}
69
70static u32 check_header(const void *buf)
71{
72 u32 i, pattern;
73 int swap = SWAP_NO;
74 u32 *test = (u32 *)buf;
75
76 debug("%s: Let's check bitstream header\n", __func__);
77
78 /* Checking that passing bin is not a bitstream */
79 for (i = 0; i < ARRAY_SIZE(bin_format); i++) {
80 pattern = load_word(&test[i], swap);
81
82 /*
83 * Bitstreams in binary format are swapped
84 * compare to regular bistream.
85 * Do not swap dummy word but if swap is done assume
86 * that parsing buffer is binary format
87 */
88 if ((__swab32(pattern) != DUMMY_WORD) &&
89 (__swab32(pattern) == bin_format[i])) {
90 swap = SWAP_DONE;
91 debug("%s: data swapped - let's swap\n", __func__);
92 }
93
94 debug("%s: %d/%px: pattern %x/%x bin_format\n", __func__, i,
95 &test[i], pattern, bin_format[i]);
96 }
97 debug("%s: Found bitstream header at %px %s swapinng\n", __func__,
98 buf, swap == SWAP_NO ? "without" : "with");
99
100 return swap;
101}
102
103static void *check_data(u8 *buf, size_t bsize, u32 *swap)
104{
105 u32 word, p = 0; /* possition */
106
107 /* Because buf doesn't need to be aligned let's read it by chars */
108 for (p = 0; p < bsize; p++) {
109 word = load_word(&buf[p], SWAP_NO);
110 debug("%s: word %x %x/%px\n", __func__, word, p, &buf[p]);
111
112 /* Find the first bitstream dummy word */
113 if (word == DUMMY_WORD) {
114 debug("%s: Found dummy word at position %x/%px\n",
115 __func__, p, &buf[p]);
116 *swap = check_header(&buf[p]);
117 if (*swap) {
118 /* FIXME add full bitstream checking here */
119 return &buf[p];
120 }
121 }
122 /* Loop can be huge - support CTRL + C */
123 if (ctrlc())
124 return NULL;
125 }
126 return NULL;
127}
128
129static ulong zynqmp_align_dma_buffer(u32 *buf, u32 len, u32 swap)
130{
131 u32 *new_buf;
132 u32 i;
133
134 if ((ulong)buf != ALIGN((ulong)buf, ARCH_DMA_MINALIGN)) {
135 new_buf = (u32 *)ALIGN((ulong)buf, ARCH_DMA_MINALIGN);
136
137 /*
138 * This might be dangerous but permits to flash if
139 * ARCH_DMA_MINALIGN is greater than header size
140 */
141 if (new_buf > (u32 *)buf) {
142 debug("%s: Aligned buffer is after buffer start\n",
143 __func__);
144 new_buf -= ARCH_DMA_MINALIGN;
145 }
146 printf("%s: Align buffer at %px to %px(swap %d)\n", __func__,
147 buf, new_buf, swap);
148
149 for (i = 0; i < (len/4); i++)
150 new_buf[i] = load_word(&buf[i], swap);
151
152 buf = new_buf;
Siva Durga Prasad Paladugufbf7fb02018-08-21 15:44:50 +0530153 } else if ((swap != SWAP_DONE) &&
154 (zynqmp_pmufw_version() <= PMUFW_V1_0)) {
Siva Durga Prasad Paladugu6b245012016-01-13 16:25:37 +0530155 /* For bitstream which are aligned */
156 u32 *new_buf = (u32 *)buf;
157
158 printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
159 swap);
160
161 for (i = 0; i < (len/4); i++)
162 new_buf[i] = load_word(&buf[i], swap);
163 }
164
165 return (ulong)buf;
166}
167
168static int zynqmp_validate_bitstream(xilinx_desc *desc, const void *buf,
169 size_t bsize, u32 blocksize, u32 *swap)
170{
171 ulong *buf_start;
172 ulong diff;
173
174 buf_start = check_data((u8 *)buf, blocksize, swap);
175
176 if (!buf_start)
177 return FPGA_FAIL;
178
179 /* Check if data is postpone from start */
180 diff = (ulong)buf_start - (ulong)buf;
181 if (diff) {
182 printf("%s: Bitstream is not validated yet (diff %lx)\n",
183 __func__, diff);
184 return FPGA_FAIL;
185 }
186
187 if ((ulong)buf < SZ_1M) {
188 printf("%s: Bitstream has to be placed up to 1MB (%px)\n",
189 __func__, buf);
190 return FPGA_FAIL;
191 }
192
193 return 0;
194}
195
Siva Durga Prasad Paladugu6b245012016-01-13 16:25:37 +0530196static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
197 bitstream_type bstype)
198{
Siva Durga Prasad Paladugu31bcb342018-03-15 00:17:24 +0530199 ALLOC_CACHE_ALIGN_BUFFER(u32, bsizeptr, 1);
Siva Durga Prasad Paladugufbf7fb02018-08-21 15:44:50 +0530200 u32 swap = 0;
Siva Durga Prasad Paladugu7033ae22017-02-17 16:16:01 +0530201 ulong bin_buf;
Siva Durga Prasad Paladugu6b245012016-01-13 16:25:37 +0530202 int ret;
Siva Durga Prasad Paladugu7033ae22017-02-17 16:16:01 +0530203 u32 buf_lo, buf_hi;
204 u32 ret_payload[PAYLOAD_ARG_CNT];
Siva Durga Prasad Paladugufbf7fb02018-08-21 15:44:50 +0530205 bool xilfpga_old = false;
Siva Durga Prasad Paladugu6b245012016-01-13 16:25:37 +0530206
Siva Durga Prasad Paladugufbf7fb02018-08-21 15:44:50 +0530207 if (zynqmp_pmufw_version() <= PMUFW_V1_0) {
208 puts("WARN: PMUFW v1.0 or less is detected\n");
209 puts("WARN: Not all bitstream formats are supported\n");
210 puts("WARN: Please upgrade PMUFW\n");
211 xilfpga_old = true;
212 if (zynqmp_validate_bitstream(desc, buf, bsize, bsize, &swap))
213 return FPGA_FAIL;
214 bsizeptr = (u32 *)&bsize;
215 flush_dcache_range((ulong)bsizeptr,
216 (ulong)bsizeptr + sizeof(size_t));
217 bstype |= BIT(ZYNQMP_FPGA_BIT_NS);
218 }
Siva Durga Prasad Paladugu6b245012016-01-13 16:25:37 +0530219
220 bin_buf = zynqmp_align_dma_buffer((u32 *)buf, bsize, swap);
221
222 debug("%s called!\n", __func__);
223 flush_dcache_range(bin_buf, bin_buf + bsize);
224
Siva Durga Prasad Paladugu7033ae22017-02-17 16:16:01 +0530225 buf_lo = (u32)bin_buf;
226 buf_hi = upper_32_bits(bin_buf);
Siva Durga Prasad Paladugufbf7fb02018-08-21 15:44:50 +0530227
228 if (xilfpga_old)
229 ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi,
230 (u32)(uintptr_t)bsizeptr, bstype, ret_payload);
231 else
232 ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi,
233 (u32)bsize, 0, ret_payload);
234
Siva Durga Prasad Paladugu6b245012016-01-13 16:25:37 +0530235 if (ret)
Luca Ceresoli8df324a2019-01-11 17:09:45 +0100236 puts("PL FPGA LOAD fail\n");
Siva Durga Prasad Paladugu6b245012016-01-13 16:25:37 +0530237
238 return ret;
239}
240
Siva Durga Prasad Paladugua18d09e2018-05-31 15:10:23 +0530241#if defined(CONFIG_CMD_FPGA_LOAD_SECURE) && !defined(CONFIG_SPL_BUILD)
242static int zynqmp_loads(xilinx_desc *desc, const void *buf, size_t bsize,
243 struct fpga_secure_info *fpga_sec_info)
244{
245 int ret;
246 u32 buf_lo, buf_hi;
247 u32 ret_payload[PAYLOAD_ARG_CNT];
248 u8 flag = 0;
249
250 flush_dcache_range((ulong)buf, (ulong)buf +
251 ALIGN(bsize, CONFIG_SYS_CACHELINE_SIZE));
252
253 if (!fpga_sec_info->encflag)
254 flag |= BIT(ZYNQMP_FPGA_BIT_ENC_DEV_KEY);
255
256 if (fpga_sec_info->userkey_addr &&
257 fpga_sec_info->encflag == FPGA_ENC_USR_KEY) {
258 flush_dcache_range((ulong)fpga_sec_info->userkey_addr,
259 (ulong)fpga_sec_info->userkey_addr +
260 ALIGN(KEY_PTR_LEN,
261 CONFIG_SYS_CACHELINE_SIZE));
262 flag |= BIT(ZYNQMP_FPGA_BIT_ENC_USR_KEY);
263 }
264
265 if (!fpga_sec_info->authflag)
266 flag |= BIT(ZYNQMP_FPGA_BIT_AUTH_OCM);
267
268 if (fpga_sec_info->authflag == ZYNQMP_FPGA_AUTH_DDR)
269 flag |= BIT(ZYNQMP_FPGA_BIT_AUTH_DDR);
270
271 buf_lo = lower_32_bits((ulong)buf);
272 buf_hi = upper_32_bits((ulong)buf);
273
274 ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, buf_hi,
275 (u32)(uintptr_t)fpga_sec_info->userkey_addr,
276 flag, ret_payload);
277 if (ret)
278 puts("PL FPGA LOAD fail\n");
279 else
280 puts("Bitstream successfully loaded\n");
281
282 return ret;
283}
284#endif
285
Nitin Jainb32e11a72018-02-16 17:29:54 +0530286static int zynqmp_pcap_info(xilinx_desc *desc)
287{
288 int ret;
289 u32 ret_payload[PAYLOAD_ARG_CNT];
290
291 ret = invoke_smc(ZYNQMP_SIP_SVC_PM_FPGA_STATUS, 0, 0, 0,
292 0, ret_payload);
293 if (!ret)
294 printf("PCAP status\t0x%x\n", ret_payload[1]);
295
296 return ret;
297}
298
Siva Durga Prasad Paladugu6b245012016-01-13 16:25:37 +0530299struct xilinx_fpga_op zynqmp_op = {
300 .load = zynqmp_load,
Siva Durga Prasad Paladugua18d09e2018-05-31 15:10:23 +0530301#if defined CONFIG_CMD_FPGA_LOAD_SECURE
302 .loads = zynqmp_loads,
303#endif
Nitin Jainb32e11a72018-02-16 17:29:54 +0530304 .info = zynqmp_pcap_info,
Siva Durga Prasad Paladugu6b245012016-01-13 16:25:37 +0530305};