Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Marvell PHY drivers |
| 3 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 5 | * |
| 6 | * Copyright 2010-2011 Freescale Semiconductor, Inc. |
| 7 | * author Andy Fleming |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 8 | */ |
| 9 | #include <config.h> |
| 10 | #include <common.h> |
Simon Glass | fbfa1ab | 2016-07-05 17:10:12 -0600 | [diff] [blame] | 11 | #include <errno.h> |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 12 | #include <phy.h> |
| 13 | |
| 14 | #define PHY_AUTONEGOTIATE_TIMEOUT 5000 |
| 15 | |
Phil Edworthy | 68e6eca | 2017-05-24 14:43:06 +0100 | [diff] [blame] | 16 | #define MII_MARVELL_PHY_PAGE 22 |
| 17 | |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 18 | /* 88E1011 PHY Status Register */ |
| 19 | #define MIIM_88E1xxx_PHY_STATUS 0x11 |
| 20 | #define MIIM_88E1xxx_PHYSTAT_SPEED 0xc000 |
| 21 | #define MIIM_88E1xxx_PHYSTAT_GBIT 0x8000 |
| 22 | #define MIIM_88E1xxx_PHYSTAT_100 0x4000 |
| 23 | #define MIIM_88E1xxx_PHYSTAT_DUPLEX 0x2000 |
| 24 | #define MIIM_88E1xxx_PHYSTAT_SPDDONE 0x0800 |
| 25 | #define MIIM_88E1xxx_PHYSTAT_LINK 0x0400 |
| 26 | |
| 27 | #define MIIM_88E1xxx_PHY_SCR 0x10 |
| 28 | #define MIIM_88E1xxx_PHY_MDI_X_AUTO 0x0060 |
| 29 | |
| 30 | /* 88E1111 PHY LED Control Register */ |
| 31 | #define MIIM_88E1111_PHY_LED_CONTROL 24 |
| 32 | #define MIIM_88E1111_PHY_LED_DIRECT 0x4100 |
| 33 | #define MIIM_88E1111_PHY_LED_COMBINE 0x411C |
| 34 | |
Zang Roy-R61911 | fa12a08 | 2011-10-27 18:52:09 +0000 | [diff] [blame] | 35 | /* 88E1111 Extended PHY Specific Control Register */ |
| 36 | #define MIIM_88E1111_PHY_EXT_CR 0x14 |
| 37 | #define MIIM_88E1111_RX_DELAY 0x80 |
| 38 | #define MIIM_88E1111_TX_DELAY 0x2 |
| 39 | |
| 40 | /* 88E1111 Extended PHY Specific Status Register */ |
| 41 | #define MIIM_88E1111_PHY_EXT_SR 0x1b |
| 42 | #define MIIM_88E1111_HWCFG_MODE_MASK 0xf |
| 43 | #define MIIM_88E1111_HWCFG_MODE_COPPER_RGMII 0xb |
| 44 | #define MIIM_88E1111_HWCFG_MODE_FIBER_RGMII 0x3 |
| 45 | #define MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK 0x4 |
| 46 | #define MIIM_88E1111_HWCFG_MODE_COPPER_RTBI 0x9 |
| 47 | #define MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO 0x8000 |
| 48 | #define MIIM_88E1111_HWCFG_FIBER_COPPER_RES 0x2000 |
| 49 | |
| 50 | #define MIIM_88E1111_COPPER 0 |
| 51 | #define MIIM_88E1111_FIBER 1 |
| 52 | |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 53 | /* 88E1118 PHY defines */ |
| 54 | #define MIIM_88E1118_PHY_PAGE 22 |
| 55 | #define MIIM_88E1118_PHY_LED_PAGE 3 |
| 56 | |
| 57 | /* 88E1121 PHY LED Control Register */ |
| 58 | #define MIIM_88E1121_PHY_LED_CTRL 16 |
| 59 | #define MIIM_88E1121_PHY_LED_PAGE 3 |
| 60 | #define MIIM_88E1121_PHY_LED_DEF 0x0030 |
| 61 | |
| 62 | /* 88E1121 PHY IRQ Enable/Status Register */ |
| 63 | #define MIIM_88E1121_PHY_IRQ_EN 18 |
| 64 | #define MIIM_88E1121_PHY_IRQ_STATUS 19 |
| 65 | |
| 66 | #define MIIM_88E1121_PHY_PAGE 22 |
| 67 | |
| 68 | /* 88E1145 Extended PHY Specific Control Register */ |
| 69 | #define MIIM_88E1145_PHY_EXT_CR 20 |
| 70 | #define MIIM_M88E1145_RGMII_RX_DELAY 0x0080 |
| 71 | #define MIIM_M88E1145_RGMII_TX_DELAY 0x0002 |
| 72 | |
| 73 | #define MIIM_88E1145_PHY_LED_CONTROL 24 |
| 74 | #define MIIM_88E1145_PHY_LED_DIRECT 0x4100 |
| 75 | |
| 76 | #define MIIM_88E1145_PHY_PAGE 29 |
| 77 | #define MIIM_88E1145_PHY_CAL_OV 30 |
| 78 | |
| 79 | #define MIIM_88E1149_PHY_PAGE 29 |
| 80 | |
Sebastian Hesselbarth | aeceec0 | 2012-12-04 09:31:59 +0100 | [diff] [blame] | 81 | /* 88E1310 PHY defines */ |
| 82 | #define MIIM_88E1310_PHY_LED_CTRL 16 |
| 83 | #define MIIM_88E1310_PHY_IRQ_EN 18 |
| 84 | #define MIIM_88E1310_PHY_RGMII_CTRL 21 |
| 85 | #define MIIM_88E1310_PHY_PAGE 22 |
| 86 | |
Joe Hershberger | 93cc295 | 2016-12-09 11:54:39 -0600 | [diff] [blame] | 87 | /* 88E151x PHY defines */ |
Phil Edworthy | 68e6eca | 2017-05-24 14:43:06 +0100 | [diff] [blame] | 88 | /* Page 2 registers */ |
| 89 | #define MIIM_88E151x_PHY_MSCR 21 |
| 90 | #define MIIM_88E151x_RGMII_RX_DELAY BIT(5) |
| 91 | #define MIIM_88E151x_RGMII_TX_DELAY BIT(4) |
| 92 | #define MIIM_88E151x_RGMII_RXTX_DELAY (BIT(5) | BIT(4)) |
Joe Hershberger | 93cc295 | 2016-12-09 11:54:39 -0600 | [diff] [blame] | 93 | /* Page 3 registers */ |
| 94 | #define MIIM_88E151x_LED_FUNC_CTRL 16 |
| 95 | #define MIIM_88E151x_LED_FLD_SZ 4 |
| 96 | #define MIIM_88E151x_LED0_OFFS (0 * MIIM_88E151x_LED_FLD_SZ) |
| 97 | #define MIIM_88E151x_LED1_OFFS (1 * MIIM_88E151x_LED_FLD_SZ) |
| 98 | #define MIIM_88E151x_LED0_ACT 3 |
| 99 | #define MIIM_88E151x_LED1_100_1000_LINK 6 |
| 100 | #define MIIM_88E151x_LED_TIMER_CTRL 18 |
| 101 | #define MIIM_88E151x_INT_EN_OFFS 7 |
| 102 | /* Page 18 registers */ |
| 103 | #define MIIM_88E151x_GENERAL_CTRL 20 |
| 104 | #define MIIM_88E151x_MODE_SGMII 1 |
| 105 | #define MIIM_88E151x_RESET_OFFS 15 |
| 106 | |
Lukasz Majewski | ce27eb9 | 2017-10-30 22:57:53 +0100 | [diff] [blame] | 107 | static int m88e1xxx_phy_extread(struct phy_device *phydev, int addr, |
| 108 | int devaddr, int regnum) |
| 109 | { |
| 110 | int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE); |
| 111 | int val; |
| 112 | |
| 113 | phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, devaddr); |
| 114 | val = phy_read(phydev, MDIO_DEVAD_NONE, regnum); |
| 115 | phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, oldpage); |
| 116 | |
| 117 | return val; |
| 118 | } |
| 119 | |
| 120 | static int m88e1xxx_phy_extwrite(struct phy_device *phydev, int addr, |
| 121 | int devaddr, int regnum, u16 val) |
| 122 | { |
| 123 | int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE); |
| 124 | |
| 125 | phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, devaddr); |
| 126 | phy_write(phydev, MDIO_DEVAD_NONE, regnum, val); |
| 127 | phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, oldpage); |
| 128 | |
| 129 | return 0; |
| 130 | } |
| 131 | |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 132 | /* Marvell 88E1011S */ |
| 133 | static int m88e1011s_config(struct phy_device *phydev) |
| 134 | { |
| 135 | /* Reset and configure the PHY */ |
| 136 | phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); |
| 137 | |
| 138 | phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); |
| 139 | phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c); |
| 140 | phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); |
| 141 | phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0); |
| 142 | phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); |
| 143 | |
| 144 | phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); |
| 145 | |
| 146 | genphy_config_aneg(phydev); |
| 147 | |
| 148 | return 0; |
| 149 | } |
| 150 | |
| 151 | /* Parse the 88E1011's status register for speed and duplex |
| 152 | * information |
| 153 | */ |
Michal Simek | ef5e821 | 2016-05-18 12:48:57 +0200 | [diff] [blame] | 154 | static int m88e1xxx_parse_status(struct phy_device *phydev) |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 155 | { |
| 156 | unsigned int speed; |
| 157 | unsigned int mii_reg; |
| 158 | |
| 159 | mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_STATUS); |
| 160 | |
| 161 | if ((mii_reg & MIIM_88E1xxx_PHYSTAT_LINK) && |
Mario Six | 76f11d3 | 2018-01-15 11:08:24 +0100 | [diff] [blame^] | 162 | !(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) { |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 163 | int i = 0; |
| 164 | |
| 165 | puts("Waiting for PHY realtime link"); |
| 166 | while (!(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) { |
| 167 | /* Timeout reached ? */ |
| 168 | if (i > PHY_AUTONEGOTIATE_TIMEOUT) { |
| 169 | puts(" TIMEOUT !\n"); |
| 170 | phydev->link = 0; |
Michal Simek | ef5e821 | 2016-05-18 12:48:57 +0200 | [diff] [blame] | 171 | return -ETIMEDOUT; |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 172 | } |
| 173 | |
| 174 | if ((i++ % 1000) == 0) |
| 175 | putc('.'); |
| 176 | udelay(1000); |
| 177 | mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, |
Mario Six | 76f11d3 | 2018-01-15 11:08:24 +0100 | [diff] [blame^] | 178 | MIIM_88E1xxx_PHY_STATUS); |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 179 | } |
| 180 | puts(" done\n"); |
Mario Six | 76f11d3 | 2018-01-15 11:08:24 +0100 | [diff] [blame^] | 181 | mdelay(500); /* another 500 ms (results in faster booting) */ |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 182 | } else { |
| 183 | if (mii_reg & MIIM_88E1xxx_PHYSTAT_LINK) |
| 184 | phydev->link = 1; |
| 185 | else |
| 186 | phydev->link = 0; |
| 187 | } |
| 188 | |
| 189 | if (mii_reg & MIIM_88E1xxx_PHYSTAT_DUPLEX) |
| 190 | phydev->duplex = DUPLEX_FULL; |
| 191 | else |
| 192 | phydev->duplex = DUPLEX_HALF; |
| 193 | |
| 194 | speed = mii_reg & MIIM_88E1xxx_PHYSTAT_SPEED; |
| 195 | |
| 196 | switch (speed) { |
| 197 | case MIIM_88E1xxx_PHYSTAT_GBIT: |
| 198 | phydev->speed = SPEED_1000; |
| 199 | break; |
| 200 | case MIIM_88E1xxx_PHYSTAT_100: |
| 201 | phydev->speed = SPEED_100; |
| 202 | break; |
| 203 | default: |
| 204 | phydev->speed = SPEED_10; |
| 205 | break; |
| 206 | } |
| 207 | |
| 208 | return 0; |
| 209 | } |
| 210 | |
| 211 | static int m88e1011s_startup(struct phy_device *phydev) |
| 212 | { |
Michal Simek | b733c27 | 2016-05-18 12:46:12 +0200 | [diff] [blame] | 213 | int ret; |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 214 | |
Michal Simek | b733c27 | 2016-05-18 12:46:12 +0200 | [diff] [blame] | 215 | ret = genphy_update_link(phydev); |
| 216 | if (ret) |
| 217 | return ret; |
| 218 | |
| 219 | return m88e1xxx_parse_status(phydev); |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 220 | } |
| 221 | |
| 222 | /* Marvell 88E1111S */ |
| 223 | static int m88e1111s_config(struct phy_device *phydev) |
| 224 | { |
| 225 | int reg; |
| 226 | |
Phil Edworthy | 24d98cb | 2016-12-12 12:54:15 +0000 | [diff] [blame] | 227 | if (phy_interface_is_rgmii(phydev)) { |
Zang Roy-R61911 | fa12a08 | 2011-10-27 18:52:09 +0000 | [diff] [blame] | 228 | reg = phy_read(phydev, |
Mario Six | 76f11d3 | 2018-01-15 11:08:24 +0100 | [diff] [blame^] | 229 | MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR); |
Zang Roy-R61911 | fa12a08 | 2011-10-27 18:52:09 +0000 | [diff] [blame] | 230 | if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) || |
Mario Six | 76f11d3 | 2018-01-15 11:08:24 +0100 | [diff] [blame^] | 231 | (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)) { |
Zang Roy-R61911 | fa12a08 | 2011-10-27 18:52:09 +0000 | [diff] [blame] | 232 | reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY); |
| 233 | } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { |
| 234 | reg &= ~MIIM_88E1111_TX_DELAY; |
| 235 | reg |= MIIM_88E1111_RX_DELAY; |
| 236 | } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { |
| 237 | reg &= ~MIIM_88E1111_RX_DELAY; |
| 238 | reg |= MIIM_88E1111_TX_DELAY; |
| 239 | } |
| 240 | |
| 241 | phy_write(phydev, |
Mario Six | 76f11d3 | 2018-01-15 11:08:24 +0100 | [diff] [blame^] | 242 | MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg); |
Zang Roy-R61911 | fa12a08 | 2011-10-27 18:52:09 +0000 | [diff] [blame] | 243 | |
| 244 | reg = phy_read(phydev, |
Mario Six | 76f11d3 | 2018-01-15 11:08:24 +0100 | [diff] [blame^] | 245 | MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR); |
Zang Roy-R61911 | fa12a08 | 2011-10-27 18:52:09 +0000 | [diff] [blame] | 246 | |
| 247 | reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK); |
| 248 | |
| 249 | if (reg & MIIM_88E1111_HWCFG_FIBER_COPPER_RES) |
| 250 | reg |= MIIM_88E1111_HWCFG_MODE_FIBER_RGMII; |
| 251 | else |
| 252 | reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RGMII; |
| 253 | |
| 254 | phy_write(phydev, |
Mario Six | 76f11d3 | 2018-01-15 11:08:24 +0100 | [diff] [blame^] | 255 | MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR, reg); |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 256 | } |
| 257 | |
Zang Roy-R61911 | fa12a08 | 2011-10-27 18:52:09 +0000 | [diff] [blame] | 258 | if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { |
| 259 | reg = phy_read(phydev, |
Mario Six | 76f11d3 | 2018-01-15 11:08:24 +0100 | [diff] [blame^] | 260 | MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR); |
Zang Roy-R61911 | fa12a08 | 2011-10-27 18:52:09 +0000 | [diff] [blame] | 261 | |
| 262 | reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK); |
| 263 | reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK; |
| 264 | reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; |
| 265 | |
| 266 | phy_write(phydev, MDIO_DEVAD_NONE, |
Mario Six | 76f11d3 | 2018-01-15 11:08:24 +0100 | [diff] [blame^] | 267 | MIIM_88E1111_PHY_EXT_SR, reg); |
Zang Roy-R61911 | fa12a08 | 2011-10-27 18:52:09 +0000 | [diff] [blame] | 268 | } |
| 269 | |
| 270 | if (phydev->interface == PHY_INTERFACE_MODE_RTBI) { |
| 271 | reg = phy_read(phydev, |
Mario Six | 76f11d3 | 2018-01-15 11:08:24 +0100 | [diff] [blame^] | 272 | MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR); |
Zang Roy-R61911 | fa12a08 | 2011-10-27 18:52:09 +0000 | [diff] [blame] | 273 | reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY); |
| 274 | phy_write(phydev, |
Mario Six | 76f11d3 | 2018-01-15 11:08:24 +0100 | [diff] [blame^] | 275 | MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg); |
Zang Roy-R61911 | fa12a08 | 2011-10-27 18:52:09 +0000 | [diff] [blame] | 276 | |
| 277 | reg = phy_read(phydev, MDIO_DEVAD_NONE, |
Mario Six | 76f11d3 | 2018-01-15 11:08:24 +0100 | [diff] [blame^] | 278 | MIIM_88E1111_PHY_EXT_SR); |
Zang Roy-R61911 | fa12a08 | 2011-10-27 18:52:09 +0000 | [diff] [blame] | 279 | reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK | |
| 280 | MIIM_88E1111_HWCFG_FIBER_COPPER_RES); |
| 281 | reg |= 0x7 | MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; |
| 282 | phy_write(phydev, MDIO_DEVAD_NONE, |
Mario Six | 76f11d3 | 2018-01-15 11:08:24 +0100 | [diff] [blame^] | 283 | MIIM_88E1111_PHY_EXT_SR, reg); |
Zang Roy-R61911 | fa12a08 | 2011-10-27 18:52:09 +0000 | [diff] [blame] | 284 | |
| 285 | /* soft reset */ |
Stefan Roese | 3089c47 | 2016-02-10 07:06:05 +0100 | [diff] [blame] | 286 | phy_reset(phydev); |
Zang Roy-R61911 | fa12a08 | 2011-10-27 18:52:09 +0000 | [diff] [blame] | 287 | |
| 288 | reg = phy_read(phydev, MDIO_DEVAD_NONE, |
Mario Six | 76f11d3 | 2018-01-15 11:08:24 +0100 | [diff] [blame^] | 289 | MIIM_88E1111_PHY_EXT_SR); |
Zang Roy-R61911 | fa12a08 | 2011-10-27 18:52:09 +0000 | [diff] [blame] | 290 | reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK | |
Mario Six | 76f11d3 | 2018-01-15 11:08:24 +0100 | [diff] [blame^] | 291 | MIIM_88E1111_HWCFG_FIBER_COPPER_RES); |
Zang Roy-R61911 | fa12a08 | 2011-10-27 18:52:09 +0000 | [diff] [blame] | 292 | reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RTBI | |
| 293 | MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; |
| 294 | phy_write(phydev, MDIO_DEVAD_NONE, |
Mario Six | 76f11d3 | 2018-01-15 11:08:24 +0100 | [diff] [blame^] | 295 | MIIM_88E1111_PHY_EXT_SR, reg); |
Zang Roy-R61911 | fa12a08 | 2011-10-27 18:52:09 +0000 | [diff] [blame] | 296 | } |
| 297 | |
| 298 | /* soft reset */ |
Stefan Roese | 3089c47 | 2016-02-10 07:06:05 +0100 | [diff] [blame] | 299 | phy_reset(phydev); |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 300 | |
| 301 | genphy_config_aneg(phydev); |
Stefan Roese | a8c3eca | 2016-02-10 07:06:06 +0100 | [diff] [blame] | 302 | genphy_restart_aneg(phydev); |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 303 | |
| 304 | return 0; |
| 305 | } |
| 306 | |
Hao Zhang | 35fa0dd | 2014-10-30 18:59:43 +0200 | [diff] [blame] | 307 | /** |
| 308 | * m88e1518_phy_writebits - write bits to a register |
| 309 | */ |
| 310 | void m88e1518_phy_writebits(struct phy_device *phydev, |
Mario Six | 76f11d3 | 2018-01-15 11:08:24 +0100 | [diff] [blame^] | 311 | u8 reg_num, u16 offset, u16 len, u16 data) |
Hao Zhang | 35fa0dd | 2014-10-30 18:59:43 +0200 | [diff] [blame] | 312 | { |
| 313 | u16 reg, mask; |
| 314 | |
| 315 | if ((len + offset) >= 16) |
| 316 | mask = 0 - (1 << offset); |
| 317 | else |
| 318 | mask = (1 << (len + offset)) - (1 << offset); |
| 319 | |
| 320 | reg = phy_read(phydev, MDIO_DEVAD_NONE, reg_num); |
| 321 | |
| 322 | reg &= ~mask; |
| 323 | reg |= data << offset; |
| 324 | |
| 325 | phy_write(phydev, MDIO_DEVAD_NONE, reg_num, reg); |
| 326 | } |
| 327 | |
| 328 | static int m88e1518_config(struct phy_device *phydev) |
| 329 | { |
Phil Edworthy | 68e6eca | 2017-05-24 14:43:06 +0100 | [diff] [blame] | 330 | u16 reg; |
| 331 | |
Hao Zhang | 35fa0dd | 2014-10-30 18:59:43 +0200 | [diff] [blame] | 332 | /* |
| 333 | * As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512 |
| 334 | * /88E1514 Rev A0, Errata Section 3.1 |
| 335 | */ |
Clemens Gruber | 90a94ef | 2015-06-06 14:44:57 +0200 | [diff] [blame] | 336 | |
| 337 | /* EEE initialization */ |
Joe Hershberger | 93cc295 | 2016-12-09 11:54:39 -0600 | [diff] [blame] | 338 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00ff); |
Clemens Gruber | 90a94ef | 2015-06-06 14:44:57 +0200 | [diff] [blame] | 339 | phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x214B); |
| 340 | phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2144); |
| 341 | phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x0C28); |
| 342 | phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2146); |
| 343 | phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xB233); |
| 344 | phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x214D); |
| 345 | phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xCC0C); |
| 346 | phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2159); |
Joe Hershberger | 93cc295 | 2016-12-09 11:54:39 -0600 | [diff] [blame] | 347 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); |
Clemens Gruber | 90a94ef | 2015-06-06 14:44:57 +0200 | [diff] [blame] | 348 | |
| 349 | /* SGMII-to-Copper mode initialization */ |
Hao Zhang | 35fa0dd | 2014-10-30 18:59:43 +0200 | [diff] [blame] | 350 | if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { |
Clemens Gruber | 90a94ef | 2015-06-06 14:44:57 +0200 | [diff] [blame] | 351 | /* Select page 18 */ |
Joe Hershberger | 93cc295 | 2016-12-09 11:54:39 -0600 | [diff] [blame] | 352 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 18); |
Clemens Gruber | 90a94ef | 2015-06-06 14:44:57 +0200 | [diff] [blame] | 353 | |
| 354 | /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */ |
Joe Hershberger | 93cc295 | 2016-12-09 11:54:39 -0600 | [diff] [blame] | 355 | m88e1518_phy_writebits(phydev, MIIM_88E151x_GENERAL_CTRL, |
| 356 | 0, 3, MIIM_88E151x_MODE_SGMII); |
Hao Zhang | 35fa0dd | 2014-10-30 18:59:43 +0200 | [diff] [blame] | 357 | |
Clemens Gruber | 90a94ef | 2015-06-06 14:44:57 +0200 | [diff] [blame] | 358 | /* PHY reset is necessary after changing MODE[2:0] */ |
Joe Hershberger | 93cc295 | 2016-12-09 11:54:39 -0600 | [diff] [blame] | 359 | m88e1518_phy_writebits(phydev, MIIM_88E151x_GENERAL_CTRL, |
| 360 | MIIM_88E151x_RESET_OFFS, 1, 1); |
Clemens Gruber | 90a94ef | 2015-06-06 14:44:57 +0200 | [diff] [blame] | 361 | |
| 362 | /* Reset page selection */ |
Joe Hershberger | 93cc295 | 2016-12-09 11:54:39 -0600 | [diff] [blame] | 363 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0); |
Clemens Gruber | 90a94ef | 2015-06-06 14:44:57 +0200 | [diff] [blame] | 364 | |
Hao Zhang | 35fa0dd | 2014-10-30 18:59:43 +0200 | [diff] [blame] | 365 | udelay(100); |
| 366 | } |
| 367 | |
Phil Edworthy | 68e6eca | 2017-05-24 14:43:06 +0100 | [diff] [blame] | 368 | if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { |
| 369 | reg = phy_read(phydev, MDIO_DEVAD_NONE, |
| 370 | MIIM_88E1111_PHY_EXT_SR); |
| 371 | |
| 372 | reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK); |
| 373 | reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK; |
| 374 | reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; |
| 375 | |
| 376 | phy_write(phydev, MDIO_DEVAD_NONE, |
| 377 | MIIM_88E1111_PHY_EXT_SR, reg); |
| 378 | } |
| 379 | |
| 380 | if (phy_interface_is_rgmii(phydev)) { |
| 381 | phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, 2); |
| 382 | |
| 383 | reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E151x_PHY_MSCR); |
| 384 | reg &= ~MIIM_88E151x_RGMII_RXTX_DELAY; |
| 385 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) |
| 386 | reg |= MIIM_88E151x_RGMII_RXTX_DELAY; |
| 387 | else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) |
| 388 | reg |= MIIM_88E151x_RGMII_RX_DELAY; |
| 389 | else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) |
| 390 | reg |= MIIM_88E151x_RGMII_TX_DELAY; |
| 391 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E151x_PHY_MSCR, reg); |
| 392 | |
| 393 | phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, 0); |
| 394 | } |
| 395 | |
| 396 | /* soft reset */ |
| 397 | phy_reset(phydev); |
| 398 | |
| 399 | genphy_config_aneg(phydev); |
| 400 | genphy_restart_aneg(phydev); |
| 401 | |
| 402 | return 0; |
Hao Zhang | 35fa0dd | 2014-10-30 18:59:43 +0200 | [diff] [blame] | 403 | } |
| 404 | |
Clemens Gruber | 8396d0a | 2015-06-06 14:44:58 +0200 | [diff] [blame] | 405 | /* Marvell 88E1510 */ |
| 406 | static int m88e1510_config(struct phy_device *phydev) |
| 407 | { |
| 408 | /* Select page 3 */ |
Joe Hershberger | 93cc295 | 2016-12-09 11:54:39 -0600 | [diff] [blame] | 409 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, |
| 410 | MIIM_88E1118_PHY_LED_PAGE); |
Clemens Gruber | 8396d0a | 2015-06-06 14:44:58 +0200 | [diff] [blame] | 411 | |
| 412 | /* Enable INTn output on LED[2] */ |
Joe Hershberger | 93cc295 | 2016-12-09 11:54:39 -0600 | [diff] [blame] | 413 | m88e1518_phy_writebits(phydev, MIIM_88E151x_LED_TIMER_CTRL, |
| 414 | MIIM_88E151x_INT_EN_OFFS, 1, 1); |
Clemens Gruber | 8396d0a | 2015-06-06 14:44:58 +0200 | [diff] [blame] | 415 | |
| 416 | /* Configure LEDs */ |
Joe Hershberger | 93cc295 | 2016-12-09 11:54:39 -0600 | [diff] [blame] | 417 | /* LED[0]:0011 (ACT) */ |
| 418 | m88e1518_phy_writebits(phydev, MIIM_88E151x_LED_FUNC_CTRL, |
| 419 | MIIM_88E151x_LED0_OFFS, MIIM_88E151x_LED_FLD_SZ, |
| 420 | MIIM_88E151x_LED0_ACT); |
| 421 | /* LED[1]:0110 (LINK 100/1000 Mbps) */ |
| 422 | m88e1518_phy_writebits(phydev, MIIM_88E151x_LED_FUNC_CTRL, |
| 423 | MIIM_88E151x_LED1_OFFS, MIIM_88E151x_LED_FLD_SZ, |
| 424 | MIIM_88E151x_LED1_100_1000_LINK); |
Clemens Gruber | 8396d0a | 2015-06-06 14:44:58 +0200 | [diff] [blame] | 425 | |
| 426 | /* Reset page selection */ |
Joe Hershberger | 93cc295 | 2016-12-09 11:54:39 -0600 | [diff] [blame] | 427 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0); |
Clemens Gruber | 8396d0a | 2015-06-06 14:44:58 +0200 | [diff] [blame] | 428 | |
| 429 | return m88e1518_config(phydev); |
| 430 | } |
| 431 | |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 432 | /* Marvell 88E1118 */ |
| 433 | static int m88e1118_config(struct phy_device *phydev) |
| 434 | { |
| 435 | /* Change Page Number */ |
| 436 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0002); |
| 437 | /* Delay RGMII TX and RX */ |
| 438 | phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x1070); |
| 439 | /* Change Page Number */ |
| 440 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0003); |
| 441 | /* Adjust LED control */ |
| 442 | phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x021e); |
| 443 | /* Change Page Number */ |
| 444 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); |
| 445 | |
Michal Simek | 1b008fd | 2016-05-18 14:46:28 +0200 | [diff] [blame] | 446 | return genphy_config_aneg(phydev); |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 447 | } |
| 448 | |
| 449 | static int m88e1118_startup(struct phy_device *phydev) |
| 450 | { |
Michal Simek | b733c27 | 2016-05-18 12:46:12 +0200 | [diff] [blame] | 451 | int ret; |
| 452 | |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 453 | /* Change Page Number */ |
| 454 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); |
| 455 | |
Michal Simek | b733c27 | 2016-05-18 12:46:12 +0200 | [diff] [blame] | 456 | ret = genphy_update_link(phydev); |
| 457 | if (ret) |
| 458 | return ret; |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 459 | |
Michal Simek | b733c27 | 2016-05-18 12:46:12 +0200 | [diff] [blame] | 460 | return m88e1xxx_parse_status(phydev); |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 461 | } |
| 462 | |
| 463 | /* Marvell 88E1121R */ |
| 464 | static int m88e1121_config(struct phy_device *phydev) |
| 465 | { |
| 466 | int pg; |
| 467 | |
| 468 | /* Configure the PHY */ |
| 469 | genphy_config_aneg(phydev); |
| 470 | |
| 471 | /* Switch the page to access the led register */ |
| 472 | pg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE); |
| 473 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE, |
Mario Six | 76f11d3 | 2018-01-15 11:08:24 +0100 | [diff] [blame^] | 474 | MIIM_88E1121_PHY_LED_PAGE); |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 475 | /* Configure leds */ |
| 476 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_LED_CTRL, |
Mario Six | 76f11d3 | 2018-01-15 11:08:24 +0100 | [diff] [blame^] | 477 | MIIM_88E1121_PHY_LED_DEF); |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 478 | /* Restore the page pointer */ |
| 479 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE, pg); |
| 480 | |
| 481 | /* Disable IRQs and de-assert interrupt */ |
| 482 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_EN, 0); |
| 483 | phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_STATUS); |
| 484 | |
| 485 | return 0; |
| 486 | } |
| 487 | |
| 488 | /* Marvell 88E1145 */ |
| 489 | static int m88e1145_config(struct phy_device *phydev) |
| 490 | { |
| 491 | int reg; |
| 492 | |
| 493 | /* Errata E0, E1 */ |
| 494 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x001b); |
| 495 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0x418f); |
| 496 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x0016); |
| 497 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0xa2da); |
| 498 | |
| 499 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_SCR, |
Mario Six | 76f11d3 | 2018-01-15 11:08:24 +0100 | [diff] [blame^] | 500 | MIIM_88E1xxx_PHY_MDI_X_AUTO); |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 501 | |
| 502 | reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR); |
| 503 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) |
| 504 | reg |= MIIM_M88E1145_RGMII_RX_DELAY | |
| 505 | MIIM_M88E1145_RGMII_TX_DELAY; |
| 506 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR, reg); |
| 507 | |
| 508 | genphy_config_aneg(phydev); |
| 509 | |
York Sun | ef621da | 2017-06-06 09:22:40 -0700 | [diff] [blame] | 510 | /* soft reset */ |
| 511 | reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); |
| 512 | reg |= BMCR_RESET; |
| 513 | phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg); |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 514 | |
| 515 | return 0; |
| 516 | } |
| 517 | |
| 518 | static int m88e1145_startup(struct phy_device *phydev) |
| 519 | { |
Michal Simek | b733c27 | 2016-05-18 12:46:12 +0200 | [diff] [blame] | 520 | int ret; |
| 521 | |
| 522 | ret = genphy_update_link(phydev); |
| 523 | if (ret) |
| 524 | return ret; |
| 525 | |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 526 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_LED_CONTROL, |
Mario Six | 76f11d3 | 2018-01-15 11:08:24 +0100 | [diff] [blame^] | 527 | MIIM_88E1145_PHY_LED_DIRECT); |
Michal Simek | b733c27 | 2016-05-18 12:46:12 +0200 | [diff] [blame] | 528 | return m88e1xxx_parse_status(phydev); |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 529 | } |
| 530 | |
| 531 | /* Marvell 88E1149S */ |
| 532 | static int m88e1149_config(struct phy_device *phydev) |
| 533 | { |
| 534 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x1f); |
| 535 | phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c); |
| 536 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x5); |
| 537 | phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x0); |
| 538 | phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); |
| 539 | |
| 540 | genphy_config_aneg(phydev); |
| 541 | |
| 542 | phy_reset(phydev); |
| 543 | |
| 544 | return 0; |
| 545 | } |
| 546 | |
Sebastian Hesselbarth | aeceec0 | 2012-12-04 09:31:59 +0100 | [diff] [blame] | 547 | /* Marvell 88E1310 */ |
| 548 | static int m88e1310_config(struct phy_device *phydev) |
| 549 | { |
| 550 | u16 reg; |
| 551 | |
| 552 | /* LED link and activity */ |
| 553 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003); |
| 554 | reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL); |
| 555 | reg = (reg & ~0xf) | 0x1; |
| 556 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL, reg); |
| 557 | |
| 558 | /* Set LED2/INT to INT mode, low active */ |
| 559 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003); |
| 560 | reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN); |
| 561 | reg = (reg & 0x77ff) | 0x0880; |
| 562 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN, reg); |
| 563 | |
| 564 | /* Set RGMII delay */ |
| 565 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0002); |
| 566 | reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL); |
| 567 | reg |= 0x0030; |
| 568 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL, reg); |
| 569 | |
| 570 | /* Ensure to return to page 0 */ |
| 571 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0000); |
| 572 | |
Nathan Rossi | 08e64ce | 2016-06-03 23:16:17 +1000 | [diff] [blame] | 573 | return genphy_config_aneg(phydev); |
Sebastian Hesselbarth | aeceec0 | 2012-12-04 09:31:59 +0100 | [diff] [blame] | 574 | } |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 575 | |
Dirk Eibach | c52d428 | 2017-01-11 16:00:46 +0100 | [diff] [blame] | 576 | static int m88e1680_config(struct phy_device *phydev) |
| 577 | { |
| 578 | /* |
| 579 | * As per Marvell Release Notes - Alaska V 88E1680 Rev A2 |
| 580 | * Errata Section 4.1 |
| 581 | */ |
| 582 | u16 reg; |
| 583 | int res; |
| 584 | |
| 585 | /* Matrix LED mode (not neede if single LED mode is used */ |
| 586 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0004); |
| 587 | reg = phy_read(phydev, MDIO_DEVAD_NONE, 27); |
| 588 | reg |= (1 << 5); |
| 589 | phy_write(phydev, MDIO_DEVAD_NONE, 27, reg); |
| 590 | |
| 591 | /* QSGMII TX amplitude change */ |
| 592 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00fd); |
| 593 | phy_write(phydev, MDIO_DEVAD_NONE, 8, 0x0b53); |
| 594 | phy_write(phydev, MDIO_DEVAD_NONE, 7, 0x200d); |
| 595 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); |
| 596 | |
| 597 | /* EEE initialization */ |
| 598 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00ff); |
| 599 | phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xb030); |
| 600 | phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x215c); |
| 601 | phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00fc); |
| 602 | phy_write(phydev, MDIO_DEVAD_NONE, 24, 0x888c); |
| 603 | phy_write(phydev, MDIO_DEVAD_NONE, 25, 0x888c); |
| 604 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); |
| 605 | phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140); |
| 606 | |
| 607 | res = genphy_config_aneg(phydev); |
| 608 | if (res < 0) |
| 609 | return res; |
| 610 | |
| 611 | /* soft reset */ |
| 612 | reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); |
| 613 | reg |= BMCR_RESET; |
| 614 | phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg); |
| 615 | |
| 616 | return 0; |
| 617 | } |
| 618 | |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 619 | static struct phy_driver M88E1011S_driver = { |
| 620 | .name = "Marvell 88E1011S", |
| 621 | .uid = 0x1410c60, |
| 622 | .mask = 0xffffff0, |
| 623 | .features = PHY_GBIT_FEATURES, |
| 624 | .config = &m88e1011s_config, |
| 625 | .startup = &m88e1011s_startup, |
| 626 | .shutdown = &genphy_shutdown, |
| 627 | }; |
| 628 | |
| 629 | static struct phy_driver M88E1111S_driver = { |
| 630 | .name = "Marvell 88E1111S", |
| 631 | .uid = 0x1410cc0, |
| 632 | .mask = 0xffffff0, |
| 633 | .features = PHY_GBIT_FEATURES, |
| 634 | .config = &m88e1111s_config, |
| 635 | .startup = &m88e1011s_startup, |
| 636 | .shutdown = &genphy_shutdown, |
| 637 | }; |
| 638 | |
| 639 | static struct phy_driver M88E1118_driver = { |
| 640 | .name = "Marvell 88E1118", |
| 641 | .uid = 0x1410e10, |
| 642 | .mask = 0xffffff0, |
| 643 | .features = PHY_GBIT_FEATURES, |
| 644 | .config = &m88e1118_config, |
| 645 | .startup = &m88e1118_startup, |
| 646 | .shutdown = &genphy_shutdown, |
| 647 | }; |
| 648 | |
Michal Simek | b4b81e8 | 2012-08-07 02:23:07 +0000 | [diff] [blame] | 649 | static struct phy_driver M88E1118R_driver = { |
| 650 | .name = "Marvell 88E1118R", |
| 651 | .uid = 0x1410e40, |
| 652 | .mask = 0xffffff0, |
| 653 | .features = PHY_GBIT_FEATURES, |
| 654 | .config = &m88e1118_config, |
| 655 | .startup = &m88e1118_startup, |
| 656 | .shutdown = &genphy_shutdown, |
| 657 | }; |
| 658 | |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 659 | static struct phy_driver M88E1121R_driver = { |
| 660 | .name = "Marvell 88E1121R", |
| 661 | .uid = 0x1410cb0, |
| 662 | .mask = 0xffffff0, |
| 663 | .features = PHY_GBIT_FEATURES, |
| 664 | .config = &m88e1121_config, |
| 665 | .startup = &genphy_startup, |
| 666 | .shutdown = &genphy_shutdown, |
| 667 | }; |
| 668 | |
| 669 | static struct phy_driver M88E1145_driver = { |
| 670 | .name = "Marvell 88E1145", |
| 671 | .uid = 0x1410cd0, |
| 672 | .mask = 0xffffff0, |
| 673 | .features = PHY_GBIT_FEATURES, |
| 674 | .config = &m88e1145_config, |
| 675 | .startup = &m88e1145_startup, |
| 676 | .shutdown = &genphy_shutdown, |
| 677 | }; |
| 678 | |
| 679 | static struct phy_driver M88E1149S_driver = { |
| 680 | .name = "Marvell 88E1149S", |
| 681 | .uid = 0x1410ca0, |
| 682 | .mask = 0xffffff0, |
| 683 | .features = PHY_GBIT_FEATURES, |
| 684 | .config = &m88e1149_config, |
| 685 | .startup = &m88e1011s_startup, |
| 686 | .shutdown = &genphy_shutdown, |
| 687 | }; |
| 688 | |
Clemens Gruber | 8396d0a | 2015-06-06 14:44:58 +0200 | [diff] [blame] | 689 | static struct phy_driver M88E1510_driver = { |
| 690 | .name = "Marvell 88E1510", |
| 691 | .uid = 0x1410dd0, |
Phil Edworthy | 83cfbeb | 2016-12-12 12:54:13 +0000 | [diff] [blame] | 692 | .mask = 0xfffffff, |
Clemens Gruber | 8396d0a | 2015-06-06 14:44:58 +0200 | [diff] [blame] | 693 | .features = PHY_GBIT_FEATURES, |
| 694 | .config = &m88e1510_config, |
| 695 | .startup = &m88e1011s_startup, |
| 696 | .shutdown = &genphy_shutdown, |
Lukasz Majewski | ce27eb9 | 2017-10-30 22:57:53 +0100 | [diff] [blame] | 697 | .readext = &m88e1xxx_phy_extread, |
| 698 | .writeext = &m88e1xxx_phy_extwrite, |
Clemens Gruber | 8396d0a | 2015-06-06 14:44:58 +0200 | [diff] [blame] | 699 | }; |
| 700 | |
Phil Edworthy | 998640b | 2016-12-12 12:54:14 +0000 | [diff] [blame] | 701 | /* |
| 702 | * This supports: |
| 703 | * 88E1518, uid 0x1410dd1 |
| 704 | * 88E1512, uid 0x1410dd4 |
| 705 | */ |
Michal Simek | 1415107 | 2012-10-15 14:03:00 +0200 | [diff] [blame] | 706 | static struct phy_driver M88E1518_driver = { |
| 707 | .name = "Marvell 88E1518", |
Phil Edworthy | 998640b | 2016-12-12 12:54:14 +0000 | [diff] [blame] | 708 | .uid = 0x1410dd0, |
| 709 | .mask = 0xffffffa, |
Michal Simek | 1415107 | 2012-10-15 14:03:00 +0200 | [diff] [blame] | 710 | .features = PHY_GBIT_FEATURES, |
Hao Zhang | 35fa0dd | 2014-10-30 18:59:43 +0200 | [diff] [blame] | 711 | .config = &m88e1518_config, |
Michal Simek | 1415107 | 2012-10-15 14:03:00 +0200 | [diff] [blame] | 712 | .startup = &m88e1011s_startup, |
| 713 | .shutdown = &genphy_shutdown, |
Lukasz Majewski | ce27eb9 | 2017-10-30 22:57:53 +0100 | [diff] [blame] | 714 | .readext = &m88e1xxx_phy_extread, |
| 715 | .writeext = &m88e1xxx_phy_extwrite, |
Michal Simek | 1415107 | 2012-10-15 14:03:00 +0200 | [diff] [blame] | 716 | }; |
| 717 | |
Sebastian Hesselbarth | aeceec0 | 2012-12-04 09:31:59 +0100 | [diff] [blame] | 718 | static struct phy_driver M88E1310_driver = { |
| 719 | .name = "Marvell 88E1310", |
| 720 | .uid = 0x01410e90, |
| 721 | .mask = 0xffffff0, |
| 722 | .features = PHY_GBIT_FEATURES, |
| 723 | .config = &m88e1310_config, |
| 724 | .startup = &m88e1011s_startup, |
| 725 | .shutdown = &genphy_shutdown, |
| 726 | }; |
| 727 | |
Dirk Eibach | c52d428 | 2017-01-11 16:00:46 +0100 | [diff] [blame] | 728 | static struct phy_driver M88E1680_driver = { |
| 729 | .name = "Marvell 88E1680", |
| 730 | .uid = 0x1410ed0, |
| 731 | .mask = 0xffffff0, |
| 732 | .features = PHY_GBIT_FEATURES, |
| 733 | .config = &m88e1680_config, |
| 734 | .startup = &genphy_startup, |
| 735 | .shutdown = &genphy_shutdown, |
| 736 | }; |
| 737 | |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 738 | int phy_marvell_init(void) |
| 739 | { |
Sebastian Hesselbarth | aeceec0 | 2012-12-04 09:31:59 +0100 | [diff] [blame] | 740 | phy_register(&M88E1310_driver); |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 741 | phy_register(&M88E1149S_driver); |
| 742 | phy_register(&M88E1145_driver); |
| 743 | phy_register(&M88E1121R_driver); |
| 744 | phy_register(&M88E1118_driver); |
Michal Simek | b4b81e8 | 2012-08-07 02:23:07 +0000 | [diff] [blame] | 745 | phy_register(&M88E1118R_driver); |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 746 | phy_register(&M88E1111S_driver); |
| 747 | phy_register(&M88E1011S_driver); |
Clemens Gruber | 8396d0a | 2015-06-06 14:44:58 +0200 | [diff] [blame] | 748 | phy_register(&M88E1510_driver); |
Michal Simek | 1415107 | 2012-10-15 14:03:00 +0200 | [diff] [blame] | 749 | phy_register(&M88E1518_driver); |
Dirk Eibach | c52d428 | 2017-01-11 16:00:46 +0100 | [diff] [blame] | 750 | phy_register(&M88E1680_driver); |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 751 | |
| 752 | return 0; |
| 753 | } |