Bin Meng | b5b6b01 | 2015-04-24 18:10:05 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> |
| 3 | * |
| 4 | * Ported from coreboot src/arch/x86/include/arch/pirq_routing.h |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 7 | */ |
| 8 | |
| 9 | #ifndef _PIRQ_ROUTING_H_ |
| 10 | #define _PIRQ_ROUTING_H_ |
| 11 | |
| 12 | /* |
| 13 | * This is the maximum number on interrupt entries that a PCI device may have. |
| 14 | * This is NOT the number of slots or devices in the system |
| 15 | * This is NOT the number of entries in the PIRQ table |
| 16 | * |
| 17 | * This tells us that in the PIRQ table, we are going to have 4 link-bitmap |
| 18 | * entries per PCI device which is fixed at 4: INTA, INTB, INTC, and INTD. |
| 19 | * |
| 20 | * CAUTION: If you change this, PIRQ routing will not work correctly. |
| 21 | */ |
| 22 | #define MAX_INTX_ENTRIES 4 |
| 23 | |
| 24 | #define PIRQ_SIGNATURE \ |
| 25 | (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24)) |
| 26 | #define PIRQ_VERSION 0x0100 |
| 27 | |
| 28 | struct __packed irq_info { |
| 29 | u8 bus; /* Bus number */ |
| 30 | u8 devfn; /* Device and function number */ |
| 31 | struct __packed { |
| 32 | u8 link; /* IRQ line ID, 0=not routed */ |
| 33 | u16 bitmap; /* Available IRQs */ |
| 34 | } irq[MAX_INTX_ENTRIES]; |
| 35 | u8 slot; /* Slot number, 0=onboard */ |
| 36 | u8 rfu; |
| 37 | }; |
| 38 | |
| 39 | struct __packed irq_routing_table { |
| 40 | u32 signature; /* PIRQ_SIGNATURE */ |
| 41 | u16 version; /* PIRQ_VERSION */ |
| 42 | u16 size; /* Table size in bytes */ |
| 43 | u8 rtr_bus; /* busno of the interrupt router */ |
| 44 | u8 rtr_devfn; /* devfn of the interrupt router */ |
| 45 | u16 exclusive_irqs; /* IRQs devoted exclusively to PCI usage */ |
| 46 | u16 rtr_vendor; /* Vendor ID of the interrupt router */ |
| 47 | u16 rtr_device; /* Device ID of the interrupt router */ |
| 48 | u32 miniport_data; |
| 49 | u8 rfu[11]; |
| 50 | u8 checksum; /* Modulo 256 checksum must give zero */ |
| 51 | struct irq_info slots[CONFIG_IRQ_SLOT_COUNT]; |
| 52 | }; |
| 53 | |
| 54 | /** |
| 55 | * get_irq_slot_count() - Get the number of entries in the irq_info table |
| 56 | * |
| 57 | * This calculates the number of entries for the irq_info table. |
| 58 | * |
| 59 | * @rt: pointer to the base address of the struct irq_info |
| 60 | * @return: number of entries |
| 61 | */ |
| 62 | static inline int get_irq_slot_count(struct irq_routing_table *rt) |
| 63 | { |
| 64 | return (rt->size - 32) / sizeof(struct irq_info); |
| 65 | } |
| 66 | |
| 67 | /** |
| 68 | * pirq_check_irq_routed() - Check whether an IRQ is routed to 8259 PIC |
| 69 | * |
| 70 | * This function checks whether an IRQ is routed to 8259 PIC for a given link. |
| 71 | * |
| 72 | * Note: this function should be provided by the platform codes, as the |
| 73 | * implementation of interrupt router may be different. |
| 74 | * |
| 75 | * @link: link number which represents a PIRQ |
| 76 | * @irq: the 8259 IRQ number |
| 77 | * @return: true if the irq is already routed to 8259 for a given link, |
| 78 | * false elsewise |
| 79 | */ |
| 80 | bool pirq_check_irq_routed(int link, u8 irq); |
| 81 | |
| 82 | /** |
| 83 | * pirq_translate_link() - Translate a link value |
| 84 | * |
| 85 | * This function translates a platform-specific link value to a link number. |
| 86 | * On Intel platforms, the link value is normally a offset into the PCI |
| 87 | * configuration space into the legacy bridge. |
| 88 | * |
| 89 | * Note: this function should be provided by the platform codes, as the |
| 90 | * implementation of interrupt router may be different. |
| 91 | * |
| 92 | * @link: platform-specific link value |
| 93 | * @return: link number which represents a PIRQ |
| 94 | */ |
| 95 | int pirq_translate_link(int link); |
| 96 | |
| 97 | /** |
| 98 | * pirq_assign_irq() - Assign an IRQ to a PIRQ link |
| 99 | * |
| 100 | * This function assigns the IRQ to a PIRQ link so that the PIRQ is routed to |
| 101 | * the 8259 PIC. |
| 102 | * |
| 103 | * Note: this function should be provided by the platform codes, as the |
| 104 | * implementation of interrupt router may be different. |
| 105 | * |
| 106 | * @link: link number which represents a PIRQ |
| 107 | * @irq: IRQ to which the PIRQ is routed |
| 108 | */ |
| 109 | void pirq_assign_irq(int link, u8 irq); |
| 110 | |
| 111 | /** |
| 112 | * pirq_route_irqs() - Route PIRQs to 8259 PIC |
| 113 | * |
| 114 | * This function configures all PCI devices' interrupt pins and maps them to |
| 115 | * PIRQs and finally 8259 PIC. The routed irq number is written to interrupt |
| 116 | * line register in the configuration space of the PCI device for OS to use. |
| 117 | * The configuration source is taken from a struct irq_info table, the format |
| 118 | * of which is defined in PIRQ routing table spec and PCI BIOS spec. |
| 119 | * |
| 120 | * @irq: pointer to the base address of the struct irq_info |
| 121 | * @num: number of entries in the struct irq_info |
| 122 | */ |
| 123 | void pirq_route_irqs(struct irq_info *irq, int num); |
| 124 | |
| 125 | /** |
| 126 | * copy_pirq_routing_table() - Copy a PIRQ routing table |
| 127 | * |
| 128 | * This helper function copies the given PIRQ routing table to a given address. |
| 129 | * Before copying, it does several sanity tests against the PIRQ routing table. |
| 130 | * It also fixes up the table checksum and align the given address to a 16 byte |
| 131 | * boundary to meet the PIRQ routing table spec requirements. |
| 132 | * |
| 133 | * @addr: address to store the copied PIRQ routing table |
| 134 | * @rt: pointer to the PIRQ routing table to copy from |
| 135 | * @return: end address of the copied PIRQ routing table |
| 136 | */ |
| 137 | u32 copy_pirq_routing_table(u32 addr, struct irq_routing_table *rt); |
| 138 | |
| 139 | #endif /* _PIRQ_ROUTING_H_ */ |