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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Adam Fordf479cec2017-04-07 10:25:34 -05002/*
3 * Copyright (C) 2017 Logic PD, Inc.
4 *
5 * Author: Adam Ford <aford173@gmail.com>
6 *
7 * Based on SabreSD by Fabio Estevam <fabio.estevam@nxp.com>
8 * and updates by Jagan Teki <jagan@amarulasolutions.com>
Adam Fordf479cec2017-04-07 10:25:34 -05009 */
10
11#include <common.h>
12#include <miiphy.h>
Diego Dorta7594c512017-09-22 12:12:18 -030013#include <input.h>
Adam Fordf479cec2017-04-07 10:25:34 -050014#include <mmc.h>
Yangbo Lue37ac712019-06-21 11:42:28 +080015#include <fsl_esdhc_imx.h>
Adam Fordf479cec2017-04-07 10:25:34 -050016#include <asm/io.h>
17#include <asm/gpio.h>
18#include <linux/sizes.h>
19#include <asm/arch/clock.h>
20#include <asm/arch/crm_regs.h>
21#include <asm/arch/iomux.h>
22#include <asm/arch/mxc_hdmi.h>
23#include <asm/arch/mx6-pins.h>
24#include <asm/arch/sys_proto.h>
Stefano Babic552a8482017-06-29 10:16:06 +020025#include <asm/mach-imx/boot_mode.h>
26#include <asm/mach-imx/iomux-v3.h>
Adam Fordf479cec2017-04-07 10:25:34 -050027
28DECLARE_GLOBAL_DATA_PTR;
29
30#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
31 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
32 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
33
34#define NAND_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
35 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
36 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
37
38int dram_init(void)
39{
40 gd->ram_size = imx_ddr_size();
41 return 0;
42}
43
44static iomux_v3_cfg_t const uart1_pads[] = {
45 MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
46 MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
47};
48
49static iomux_v3_cfg_t const uart2_pads[] = {
50 MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
51 MX6_PAD_SD4_DAT5__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
52 MX6_PAD_SD4_DAT6__UART2_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
53 MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
54};
55
56static iomux_v3_cfg_t const uart3_pads[] = {
57 MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
58 MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
59 MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
60 MX6_PAD_EIM_EB3__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
61};
62
Adam Fordf479cec2017-04-07 10:25:34 -050063static void setup_iomux_uart(void)
64{
65 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
66 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
67 imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
68}
69
70static iomux_v3_cfg_t const nand_pads[] = {
71 MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
72 MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
73 MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
74 MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
75 MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
76 MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
77 MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
78 MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
79 MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
80 MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
81 MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
82 MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
83 MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
84 MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
85 MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
86};
87
88static void setup_nand_pins(void)
89{
90 imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
91}
92
Adam Ford8dd0dff2019-01-12 17:32:00 -060093static int ar8031_phy_fixup(struct phy_device *phydev)
94{
95 unsigned short val;
96
97 /* To enable AR8031 output a 125MHz clk from CLK_25M */
98 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
99 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
100 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
101
102 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
103 val &= 0xffe3;
104 val |= 0x18;
105 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
106
107 /* introduce tx clock delay */
108 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
109 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
110 val |= 0x0100;
111 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
112
113 return 0;
114}
115
Adam Fordf479cec2017-04-07 10:25:34 -0500116int board_phy_config(struct phy_device *phydev)
117{
Adam Ford8dd0dff2019-01-12 17:32:00 -0600118 ar8031_phy_fixup(phydev);
119
Adam Fordf479cec2017-04-07 10:25:34 -0500120 if (phydev->drv->config)
121 phydev->drv->config(phydev);
122
123 return 0;
124}
125
126/*
127 * Do not overwrite the console
128 * Use always serial for U-Boot console
129 */
130int overwrite_console(void)
131{
132 return 1;
133}
134
135int board_early_init_f(void)
136{
Adam Fordf479cec2017-04-07 10:25:34 -0500137 setup_iomux_uart();
138 setup_nand_pins();
139 return 0;
140}
141
142int board_init(void)
143{
144 /* address of boot parameters */
145 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
146 return 0;
147}
148
149int board_late_init(void)
150{
Simon Glass382bee52017-08-03 12:22:09 -0600151 env_set("board_name", "imx6logic");
Adam Fordf479cec2017-04-07 10:25:34 -0500152
153 if (is_mx6dq()) {
Simon Glass382bee52017-08-03 12:22:09 -0600154 env_set("board_rev", "MX6DQ");
Adam Forda9bcf932019-03-13 10:49:22 -0500155 if (!env_get("fdt_file"))
156 env_set("fdt_file", "imx6q-logicpd.dtb");
Adam Fordf479cec2017-04-07 10:25:34 -0500157 }
158
159 return 0;
160}
Adam Fordbbbb50f2018-07-05 20:58:24 -0500161
162#ifdef CONFIG_SPL_BUILD
163#include <asm/arch/mx6-ddr.h>
164#include <asm/arch/mx6q-ddr.h>
165#include <spl.h>
166#include <linux/libfdt.h>
167
168#ifdef CONFIG_SPL_OS_BOOT
169int spl_start_uboot(void)
170{
171 /* break into full u-boot on 'c' */
172 if (serial_tstc() && serial_getc() == 'c')
173 return 1;
174
175 return 0;
176}
177#endif
178
Adam Ford79ae06f2018-12-28 08:47:40 -0600179/* SD interface */
180#define USDHC_PAD_CTRL \
181 (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
182 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
183
184static iomux_v3_cfg_t const usdhc1_pads[] = {
185 MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
186 MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
187 MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
188 MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
189 MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
190 MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
191};
192
193static iomux_v3_cfg_t const usdhc2_pads[] = {
194 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
195 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
196 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
197 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
198 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
199 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
200 MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
201};
202
Yangbo Lue37ac712019-06-21 11:42:28 +0800203#ifdef CONFIG_FSL_ESDHC_IMX
Adam Ford79ae06f2018-12-28 08:47:40 -0600204struct fsl_esdhc_cfg usdhc_cfg[] = {
205 {USDHC1_BASE_ADDR}, /* SOM */
206 {USDHC2_BASE_ADDR} /* Baseboard */
207};
208
209int board_mmc_init(bd_t *bis)
210{
211 struct src *psrc = (struct src *)SRC_BASE_ADDR;
212 unsigned int reg = readl(&psrc->sbmr1) >> 11;
213 /*
214 * Upon reading BOOT_CFG register the following map is done:
215 * Bit 11 and 12 of BOOT_CFG register can determine the current
216 * mmc port
217 * 0x1 SD1-SOM
218 * 0x2 SD2-Baseboard
219 */
220
221 reg &= 0x3; /* Only care about bottom 2 bits */
222
223 switch (reg) {
224 case 0:
225 SETUP_IOMUX_PADS(usdhc1_pads);
Adam Ford79ae06f2018-12-28 08:47:40 -0600226 break;
227 case 1:
228 SETUP_IOMUX_PADS(usdhc2_pads);
Adam Ford79ae06f2018-12-28 08:47:40 -0600229 break;
230 }
231
Adam Ford8f4691e2019-05-23 14:11:32 -0500232 return 0;
Adam Ford79ae06f2018-12-28 08:47:40 -0600233}
234
Adam Ford79ae06f2018-12-28 08:47:40 -0600235#endif
236
Adam Fordbbbb50f2018-07-05 20:58:24 -0500237static void ccgr_init(void)
238{
239 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
240
241 writel(0x00C03F3F, &ccm->CCGR0);
242 writel(0x0030FC03, &ccm->CCGR1);
243 writel(0x0FFFC000, &ccm->CCGR2);
244 writel(0x3FF00000, &ccm->CCGR3);
245 writel(0xFFFFF300, &ccm->CCGR4);
246 writel(0x0F0000F3, &ccm->CCGR5);
247 writel(0x00000FFF, &ccm->CCGR6);
248}
249
250static int mx6q_dcd_table[] = {
251 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
252 MX6_IOM_GRP_DDRPKE, 0x00000000,
253 MX6_IOM_DRAM_SDCLK_0, 0x00000030,
254 MX6_IOM_DRAM_SDCLK_1, 0x00000030,
255 MX6_IOM_DRAM_CAS, 0x00000030,
256 MX6_IOM_DRAM_RAS, 0x00000030,
257 MX6_IOM_GRP_ADDDS, 0x00000030,
258 MX6_IOM_DRAM_RESET, 0x00000030,
259 MX6_IOM_DRAM_SDBA2, 0x00000000,
260 MX6_IOM_DRAM_SDODT0, 0x00000030,
261 MX6_IOM_DRAM_SDODT1, 0x00000030,
262 MX6_IOM_GRP_CTLDS, 0x00000030,
263 MX6_IOM_DDRMODE_CTL, 0x00020000,
264 MX6_IOM_DRAM_SDQS0, 0x00000030,
265 MX6_IOM_DRAM_SDQS1, 0x00000030,
266 MX6_IOM_DRAM_SDQS2, 0x00000030,
267 MX6_IOM_DRAM_SDQS3, 0x00000030,
268 MX6_IOM_GRP_DDRMODE, 0x00020000,
269 MX6_IOM_GRP_B0DS, 0x00000030,
270 MX6_IOM_GRP_B1DS, 0x00000030,
271 MX6_IOM_GRP_B2DS, 0x00000030,
272 MX6_IOM_GRP_B3DS, 0x00000030,
273 MX6_IOM_DRAM_DQM0, 0x00000030,
274 MX6_IOM_DRAM_DQM1, 0x00000030,
275 MX6_IOM_DRAM_DQM2, 0x00000030,
276 MX6_IOM_DRAM_DQM3, 0x00000030,
277 MX6_MMDC_P0_MDSCR, 0x00008000,
278 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
279 MX6_MMDC_P0_MPWLDECTRL0, 0x002D003A,
280 MX6_MMDC_P0_MPWLDECTRL1, 0x0038002B,
281 MX6_MMDC_P0_MPDGCTRL0, 0x03340338,
282 MX6_MMDC_P0_MPDGCTRL1, 0x0334032C,
283 MX6_MMDC_P0_MPRDDLCTL, 0x4036383C,
284 MX6_MMDC_P0_MPWRDLCTL, 0x2E384038,
285 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
286 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
287 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
288 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
289 MX6_MMDC_P0_MPMUR0, 0x00000800,
290 MX6_MMDC_P0_MDPDC, 0x00020036,
291 MX6_MMDC_P0_MDOTC, 0x09444040,
292 MX6_MMDC_P0_MDCFG0, 0xB8BE7955,
293 MX6_MMDC_P0_MDCFG1, 0xFF328F64,
294 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
295 MX6_MMDC_P0_MDMISC, 0x00011740,
296 MX6_MMDC_P0_MDSCR, 0x00008000,
297 MX6_MMDC_P0_MDRWD, 0x000026D2,
298 MX6_MMDC_P0_MDOR, 0x00BE1023,
299 MX6_MMDC_P0_MDASP, 0x00000047,
300 MX6_MMDC_P0_MDCTL, 0x85190000,
301 MX6_MMDC_P0_MDSCR, 0x00888032,
302 MX6_MMDC_P0_MDSCR, 0x00008033,
303 MX6_MMDC_P0_MDSCR, 0x00008031,
304 MX6_MMDC_P0_MDSCR, 0x19408030,
305 MX6_MMDC_P0_MDSCR, 0x04008040,
306 MX6_MMDC_P0_MDREF, 0x00007800,
307 MX6_MMDC_P0_MPODTCTRL, 0x00000007,
308 MX6_MMDC_P0_MDPDC, 0x00025576,
309 MX6_MMDC_P0_MAPSR, 0x00011006,
310 MX6_MMDC_P0_MDSCR, 0x00000000,
311 /* enable AXI cache for VDOA/VPU/IPU */
312
313 MX6_IOMUXC_GPR4, 0xF00000CF,
314 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
315 MX6_IOMUXC_GPR6, 0x007F007F,
316 MX6_IOMUXC_GPR7, 0x007F007F,
317};
318
319static void ddr_init(int *table, int size)
320{
321 int i;
322
323 for (i = 0; i < size / 2 ; i++)
324 writel(table[2 * i + 1], table[2 * i]);
325}
326
327static void spl_dram_init(void)
328{
329 if (is_mx6dq())
330 ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
331}
332
333void board_init_f(ulong dummy)
334{
335 /* DDR initialization */
336 spl_dram_init();
337
338 /* setup AIPS and disable watchdog */
339 arch_cpu_init();
340
341 ccgr_init();
342 gpr_init();
343
344 /* iomux and setup of uart and NAND pins */
345 board_early_init_f();
346
347 /* setup GP timer */
348 timer_init();
349
350 /* UART clocks enabled and gd valid - init serial console */
351 preloader_console_init();
352
353 /* Clear the BSS. */
354 memset(__bss_start, 0, __bss_end - __bss_start);
355
356 /* load/boot image from boot device */
357 board_init_r(NULL, 0);
358}
359#endif