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wdenkfe8c2802002-11-03 00:38:21 +00001/*
2 * (C) Copyright 2000
3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
4 *
5 * (C) Copyright 2000
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * (C) Copyright 2001
10 * Advent Networks, Inc. <http://www.adventnetworks.com>
11 * Jay Monkman <jtm@smoothsmoothie.com>
12 *
13 * Configuration settings for the WindRiver SBC8260 board.
14 * See http://www.windriver.com/products/html/sbc8260.html
15 *
16 * See file CREDITS for list of people who contributed to this
17 * project.
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * MA 02111-1307 USA
33 */
34
35#ifndef __CONFIG_H
36#define __CONFIG_H
37
wdenkfe8c2802002-11-03 00:38:21 +000038#undef DEBUG /* General debug */
39#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
40
wdenk78137c32003-09-15 18:00:00 +000041#undef CONFIG_LOGBUFFER /* External logbuffer support */
42
wdenkfe8c2802002-11-03 00:38:21 +000043/*****************************************************************************
44 *
45 * These settings must match the way _your_ board is set up
46 *
47 *****************************************************************************/
48
49/* What is the oscillator's (UX2) frequency in Hz? */
50#define CONFIG_8260_CLKIN 66666600
51
52/*-----------------------------------------------------------------------
53 * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
54 *-----------------------------------------------------------------------
55 * What should MODCK_H be? It is dependent on the oscillator
56 * frequency, MODCK[1-3], and desired CPM and core frequencies.
57 * Here are some example values (all frequencies are in MHz):
58 *
59 * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8
60 * ------- ---------- --- --- ---- ----- ----- -----
61 * 0x1 0x5 33 100 133 Open Close Open
62 * 0x1 0x6 33 100 166 Open Open Close
63 * 0x1 0x7 33 100 200 Open Open Open
64 *
65 * 0x2 0x2 33 133 133 Close Open Close
66 * 0x2 0x3 33 133 166 Close Open Open
67 * 0x2 0x4 33 133 200 Open Close Close
68 * 0x2 0x5 33 133 233 Open Close Open
69 * 0x2 0x6 33 133 266 Open Open Close
70 *
71 * 0x5 0x5 66 133 133 Open Close Open
72 * 0x5 0x6 66 133 166 Open Open Close
73 * 0x5 0x7 66 133 200 Open Open Open
74 * 0x6 0x0 66 133 233 Close Close Close
75 * 0x6 0x1 66 133 266 Close Close Open
76 * 0x6 0x2 66 133 300 Close Open Close
77 */
78#define CFG_SBC_MODCK_H 0x05
79
80/* Define this if you want to boot from 0x00000100. If you don't define
81 * this, you will need to program the bootloader to 0xfff00000, and
82 * get the hardware reset config words at 0xfe000000. The simplest
83 * way to do that is to program the bootloader at both addresses.
84 * It is suggested that you just let U-Boot live at 0x00000000.
85 */
86#define CFG_SBC_BOOT_LOW 1
87
88/* What should the base address of the main FLASH be and how big is
89 * it (in MBytes)? This must contain TEXT_BASE from board/sacsng/config.mk
90 * The main FLASH is whichever is connected to *CS0.
91 */
92#define CFG_FLASH0_BASE 0x40000000
93#define CFG_FLASH0_SIZE 2
94
95/* What should the base address of the secondary FLASH be and how big
96 * is it (in Mbytes)? The secondary FLASH is whichever is connected
97 * to *CS6.
98 */
99#define CFG_FLASH1_BASE 0x60000000
100#define CFG_FLASH1_SIZE 2
101
102/* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes
103 */
104#define CONFIG_VERY_BIG_RAM 1
105
106/* What should be the base address of SDRAM DIMM and how big is
107 * it (in Mbytes)? This will normally auto-configure via the SPD.
108*/
109#define CFG_SDRAM0_BASE 0x00000000
110#define CFG_SDRAM0_SIZE 64
111
112/*
113 * Memory map example with 64 MB DIMM:
114 *
115 * 0x0000 0000 Exception Vector code, 8k
116 * :
117 * 0x0000 1FFF
118 * 0x0000 2000 Free for Application Use
119 * :
120 * :
121 *
122 * :
123 * :
124 * 0x03F5 FF30 Monitor Stack (Growing downward)
125 * Monitor Stack Buffer (0x80)
126 * 0x03F5 FFB0 Board Info Data
127 * 0x03F6 0000 Malloc Arena
128 * : CFG_ENV_SECT_SIZE, 16k
129 * : CFG_MALLOC_LEN, 128k
130 * 0x03FC 0000 RAM Copy of Monitor Code
131 * : CFG_MONITOR_LEN, 256k
132 * 0x03FF FFFF [End of RAM], CFG_SDRAM_SIZE - 1
133 */
134
135#define CONFIG_POST (CFG_POST_MEMORY | \
136 CFG_POST_CPU)
137
138
139/*
140 * select serial console configuration
141 *
142 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
143 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
144 * for SCC).
145 *
146 * if CONFIG_CONS_NONE is defined, then the serial console routines must
147 * defined elsewhere.
148 */
149#define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */
150#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
151#undef CONFIG_CONS_NONE /* define if console on neither */
152#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
153
154/*
155 * select ethernet configuration
156 *
157 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
158 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
159 * for FCC)
160 *
161 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
162 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
163 * from CONFIG_COMMANDS to remove support for networking.
164 */
165
166#undef CONFIG_ETHER_ON_SCC
167#define CONFIG_ETHER_ON_FCC
168#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
169
170#ifdef CONFIG_ETHER_ON_SCC
171#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
172#endif /* CONFIG_ETHER_ON_SCC */
173
174#ifdef CONFIG_ETHER_ON_FCC
175#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
wdenk78137c32003-09-15 18:00:00 +0000176#undef CONFIG_ETHER_LOOPBACK_TEST /* Ethernet external loopback test */
wdenkfe8c2802002-11-03 00:38:21 +0000177#define CONFIG_MII /* MII PHY management */
178#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
179/*
180 * Port pins used for bit-banged MII communictions (if applicable).
181 */
182
183#define MDIO_PORT 2 /* Port A=0, B=1, C=2, D=3 */
184#define MDIO_ACTIVE (iop->pdir |= 0x40000000)
185#define MDIO_TRISTATE (iop->pdir &= ~0x40000000)
186#define MDIO_READ ((iop->pdat & 0x40000000) != 0)
187
188#define MDIO(bit) if(bit) iop->pdat |= 0x40000000; \
189 else iop->pdat &= ~0x40000000
190
191#define MDC(bit) if(bit) iop->pdat |= 0x80000000; \
192 else iop->pdat &= ~0x80000000
193
194#define MIIDELAY udelay(50)
195#endif /* CONFIG_ETHER_ON_FCC */
196
197#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
198
199/*
200 * - RX clk is CLK11
201 * - TX clk is CLK12
202 */
203# define CFG_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
204
205#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
206
207/*
208 * - Rx-CLK is CLK13
209 * - Tx-CLK is CLK14
210 * - Select bus for bd/buffers (see 28-13)
211 * - Enable Full Duplex in FSMR
212 */
213# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
214# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
215# define CFG_CPMFCR_RAMTYPE 0
216# define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
217
218#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
219
220#define CONFIG_SHOW_BOOT_PROGRESS 1 /* boot progress enabled */
221
222/*
223 * Configure for RAM tests.
224 */
225#undef CFG_DRAM_TEST /* calls other tests in board.c */
226
227
228/*
229 * Status LED for power up status feedback.
230 */
231#define CONFIG_STATUS_LED 1 /* Status LED enabled */
232
233#define STATUS_LED_PAR im_ioport.iop_ppara
234#define STATUS_LED_DIR im_ioport.iop_pdira
235#define STATUS_LED_ODR im_ioport.iop_podra
236#define STATUS_LED_DAT im_ioport.iop_pdata
237
238#define STATUS_LED_BIT 0x00000800 /* LED 0 is on PA.20 */
239#define STATUS_LED_PERIOD (CFG_HZ)
240#define STATUS_LED_STATE STATUS_LED_OFF
241#define STATUS_LED_BIT1 0x00001000 /* LED 1 is on PA.19 */
242#define STATUS_LED_PERIOD1 (CFG_HZ)
243#define STATUS_LED_STATE1 STATUS_LED_OFF
244#define STATUS_LED_BIT2 0x00002000 /* LED 2 is on PA.18 */
245#define STATUS_LED_PERIOD2 (CFG_HZ/2)
246#define STATUS_LED_STATE2 STATUS_LED_ON
247
248#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
249
250#define STATUS_LED_YELLOW 0
251#define STATUS_LED_GREEN 1
252#define STATUS_LED_RED 2
253#define STATUS_LED_BOOT 1
254
255
256/*
wdenk1d0350e2002-11-11 21:14:20 +0000257 * Select SPI support configuration
wdenkfe8c2802002-11-03 00:38:21 +0000258 */
wdenk1d0350e2002-11-11 21:14:20 +0000259#define CONFIG_SOFT_SPI /* Enable SPI driver */
260#define MAX_SPI_BYTES 4 /* Maximum number of bytes we can handle */
wdenk8bde7f72003-06-27 21:31:46 +0000261#undef DEBUG_SPI /* Disable SPI debugging */
262
wdenkfe8c2802002-11-03 00:38:21 +0000263/*
264 * Software (bit-bang) SPI driver configuration
265 */
266#ifdef CONFIG_SOFT_SPI
267
268/*
269 * Software (bit-bang) SPI driver configuration
270 */
271#define I2C_SCLK 0x00002000 /* PD 18: Shift clock */
272#define I2C_MOSI 0x00004000 /* PD 17: Master Out, Slave In */
273#define I2C_MISO 0x00008000 /* PD 16: Master In, Slave Out */
274
275#undef SPI_INIT /* no port initialization needed */
276#define SPI_READ ((immr->im_ioport.iop_pdatd & I2C_MISO) != 0)
277#define SPI_SDA(bit) if(bit) immr->im_ioport.iop_pdatd |= I2C_MOSI; \
wdenk8bde7f72003-06-27 21:31:46 +0000278 else immr->im_ioport.iop_pdatd &= ~I2C_MOSI
wdenkfe8c2802002-11-03 00:38:21 +0000279#define SPI_SCL(bit) if(bit) immr->im_ioport.iop_pdatd |= I2C_SCLK; \
wdenk8bde7f72003-06-27 21:31:46 +0000280 else immr->im_ioport.iop_pdatd &= ~I2C_SCLK
wdenk1d0350e2002-11-11 21:14:20 +0000281#define SPI_DELAY /* No delay is needed */
wdenkfe8c2802002-11-03 00:38:21 +0000282#endif /* CONFIG_SOFT_SPI */
283
284
285/*
286 * select I2C support configuration
287 *
288 * Supported configurations are {none, software, hardware} drivers.
289 * If the software driver is chosen, there are some additional
290 * configuration items that the driver uses to drive the port pins.
291 */
292#undef CONFIG_HARD_I2C /* I2C with hardware support */
293#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
294#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
295#define CFG_I2C_SLAVE 0x7F
296
297/*
298 * Software (bit-bang) I2C driver configuration
299 */
300#ifdef CONFIG_SOFT_I2C
301#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
302#define I2C_ACTIVE (iop->pdir |= 0x00010000)
303#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
304#define I2C_READ ((iop->pdat & 0x00010000) != 0)
305#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
306 else iop->pdat &= ~0x00010000
307#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
308 else iop->pdat &= ~0x00020000
309#define I2C_DELAY udelay(20) /* 1/4 I2C clock duration */
310#endif /* CONFIG_SOFT_I2C */
311
312/* Define this to reserve an entire FLASH sector for
313 * environment variables. Otherwise, the environment will be
314 * put in the same sector as U-Boot, and changing variables
315 * will erase U-Boot temporarily
316 */
317#define CFG_ENV_IN_OWN_SECT 1
318
319/* Define this to contain any number of null terminated strings that
320 * will be part of the default enviroment compiled into the boot image.
321 */
322#define CONFIG_EXTRA_ENV_SETTINGS \
wdenk78137c32003-09-15 18:00:00 +0000323"quiet=0\0" \
324"serverip=192.168.123.205\0" \
wdenkfe8c2802002-11-03 00:38:21 +0000325"ipaddr=192.168.123.203\0" \
326"checkhostname=VR8500\0" \
327"reprog="\
wdenk78137c32003-09-15 18:00:00 +0000328 "bootp; " \
wdenkfe8c2802002-11-03 00:38:21 +0000329 "tftpboot 0x140000 /bdi2000/u-boot.bin; " \
330 "protect off 60000000 6003FFFF; " \
331 "erase 60000000 6003FFFF; " \
332 "cp.b 140000 60000000 $(filesize); " \
333 "protect on 60000000 6003FFFF\0" \
334"copyenv="\
335 "protect off 60040000 6004FFFF; " \
336 "erase 60040000 6004FFFF; " \
337 "cp.b 40040000 60040000 10000; " \
338 "protect on 60040000 6004FFFF\0" \
339"copyprog="\
340 "protect off 60000000 6003FFFF; " \
341 "erase 60000000 6003FFFF; " \
342 "cp.b 40000000 60000000 40000; " \
343 "protect on 60000000 6003FFFF\0" \
344"zapenv="\
345 "protect off 40040000 4004FFFF; " \
346 "erase 40040000 4004FFFF; " \
347 "protect on 40040000 4004FFFF\0" \
348"zapotherenv="\
349 "protect off 60040000 6004FFFF; " \
350 "erase 60040000 6004FFFF; " \
351 "protect on 60040000 6004FFFF\0" \
352"root-on-initrd="\
353 "setenv bootcmd "\
354 "version\\;" \
355 "echo\\;" \
356 "bootp\\;" \
357 "setenv bootargs root=/dev/ram0 rw quiet " \
358 "ip=\\$(ipaddr):\\$(serverip):\\$(gatewayip):\\$(netmask):\\$(hostname)::off\\;" \
359 "run boot-hook\\;" \
360 "bootm\0" \
361"root-on-initrd-debug="\
362 "setenv bootcmd "\
363 "version\\;" \
364 "echo\\;" \
365 "bootp\\;" \
366 "setenv bootargs root=/dev/ram0 rw debug " \
367 "ip=\\$(ipaddr):\\$(serverip):\\$(gatewayip):\\$(netmask):\\$(hostname)::off\\;" \
368 "run debug-hook\\;" \
369 "run boot-hook\\;" \
370 "bootm\0" \
371"root-on-nfs="\
372 "setenv bootcmd "\
373 "version\\;" \
374 "echo\\;" \
375 "bootp\\;" \
376 "setenv bootargs root=/dev/nfs rw quiet " \
377 "nfsroot=\\$(serverip):\\$(rootpath) " \
378 "ip=\\$(ipaddr):\\$(serverip):\\$(gatewayip):\\$(netmask):\\$(hostname)::off\\;" \
379 "run boot-hook\\;" \
380 "bootm\0" \
381"root-on-nfs-debug="\
382 "setenv bootcmd "\
383 "version\\;" \
384 "echo\\;" \
385 "bootp\\;" \
386 "setenv bootargs root=/dev/nfs rw debug " \
387 "nfsroot=\\$(serverip):\\$(rootpath) " \
388 "ip=\\$(ipaddr):\\$(serverip):\\$(gatewayip):\\$(netmask):\\$(hostname)::off\\;" \
389 "run debug-hook\\;" \
390 "run boot-hook\\;" \
391 "bootm\0" \
392"debug-checkout="\
393 "setenv checkhostname;" \
394 "setenv ethaddr 00:09:70:00:00:01;" \
395 "bootp;" \
396 "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) debug " \
397 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
398 "run debug-hook;" \
399 "run boot-hook;" \
400 "bootm\0" \
401"debug-hook="\
402 "echo ipaddr $(ipaddr);" \
403 "echo serverip $(serverip);" \
404 "echo gatewayip $(gatewayip);" \
405 "echo netmask $(netmask);" \
406 "echo hostname $(hostname)\0" \
407"ana=run adc ; run dac\0" \
408"adc=run adc-12 ; run adc-34\0" \
409"adc-12=echo ### ADC-12 ; imd.b e 81 e\0" \
410"adc-34=echo ### ADC-34 ; imd.b f 81 e\0" \
411"dac=echo ### DAC ; imd.b 11 81 5\0" \
wdenk78137c32003-09-15 18:00:00 +0000412"boot-hook=echo\0"
wdenkfe8c2802002-11-03 00:38:21 +0000413
414/* What should the console's baud rate be? */
415#define CONFIG_BAUDRATE 9600
416
417/* Ethernet MAC address */
418#define CONFIG_ETHADDR 00:09:70:00:00:00
419
420/* The default Ethernet MAC address can be overwritten just once */
421#ifdef CONFIG_ETHADDR
422#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
423#endif
424
425/*
426 * Define this to do some miscellaneous board-specific initialization.
427 */
428#define CONFIG_MISC_INIT_R
429
430/* Set to a positive value to delay for running BOOTCOMMAND */
431#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
432
433/* Be selective on what keys can delay or stop the autoboot process
434 * To stop use: " "
435 */
436#define CONFIG_AUTOBOOT_KEYED
437#define CONFIG_AUTOBOOT_PROMPT "Autobooting...\n"
438#define CONFIG_AUTOBOOT_STOP_STR " "
439#undef CONFIG_AUTOBOOT_DELAY_STR
440#define CONFIG_ZERO_BOOTDELAY_CHECK
441#define DEBUG_BOOTKEYS 0
442
443/* Define a command string that is automatically executed when no character
444 * is read on the console interface withing "Boot Delay" after reset.
445 */
446#define CONFIG_BOOT_ROOT_INITRD 0 /* Use ram disk for the root file system */
447#define CONFIG_BOOT_ROOT_NFS 1 /* Use a NFS mounted root file system */
448
449#if CONFIG_BOOT_ROOT_INITRD
450#define CONFIG_BOOTCOMMAND \
451 "version;" \
452 "echo;" \
453 "bootp;" \
454 "setenv bootargs root=/dev/ram0 rw quiet " \
455 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
456 "run boot-hook;" \
457 "bootm"
458#endif /* CONFIG_BOOT_ROOT_INITRD */
459
460#if CONFIG_BOOT_ROOT_NFS
461#define CONFIG_BOOTCOMMAND \
462 "version;" \
463 "echo;" \
464 "bootp;" \
465 "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) quiet " \
466 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
467 "run boot-hook;" \
468 "bootm"
469#endif /* CONFIG_BOOT_ROOT_NFS */
470
471#define CONFIG_BOOTP_RANDOM_DELAY /* Randomize the BOOTP retry delay */
472
wdenkfe8c2802002-11-03 00:38:21 +0000473/* Add support for a few extra bootp options like:
474 * - File size
wdenk78137c32003-09-15 18:00:00 +0000475 * - DNS (up to 2 servers)
wdenk42d1f032003-10-15 23:53:47 +0000476 * - Send hostname to DHCP server
wdenkfe8c2802002-11-03 00:38:21 +0000477 */
478#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
479 CONFIG_BOOTP_BOOTFILESIZE | \
wdenk78137c32003-09-15 18:00:00 +0000480 CONFIG_BOOTP_DNS | \
wdenk42d1f032003-10-15 23:53:47 +0000481 CONFIG_BOOTP_DNS2 | \
482 CONFIG_BOOTP_SEND_HOSTNAME)
wdenkfe8c2802002-11-03 00:38:21 +0000483
484/* undef this to save memory */
485#define CFG_LONGHELP
486
487/* Monitor Command Prompt */
488#define CFG_PROMPT "=> "
489
490#undef CFG_HUSH_PARSER
491#ifdef CFG_HUSH_PARSER
492#define CFG_PROMPT_HUSH_PS2 "> "
493#endif
494
wdenk1d0350e2002-11-11 21:14:20 +0000495/* When CONFIG_TIMESTAMP is selected, the timestamp (date and time)
496 * of an image is printed by image commands like bootm or iminfo.
497 */
498#define CONFIG_TIMESTAMP
499
wdenk42d1f032003-10-15 23:53:47 +0000500/* If this variable is defined, an environment variable named "ver"
wdenk78137c32003-09-15 18:00:00 +0000501 * is created by U-Boot showing the U-Boot version.
502 */
503#define CONFIG_VERSION_VARIABLE
504
wdenkfe8c2802002-11-03 00:38:21 +0000505/* What U-Boot subsytems do you want enabled? */
506#ifdef CONFIG_ETHER_ON_FCC
507# define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
508 CFG_CMD_ELF | \
509 CFG_CMD_ASKENV | \
510 CFG_CMD_ECHO | \
511 CFG_CMD_I2C | \
512 CFG_CMD_SPI | \
513 CFG_CMD_SDRAM | \
514 CFG_CMD_REGINFO | \
515 CFG_CMD_IMMAP | \
wdenk78137c32003-09-15 18:00:00 +0000516 CFG_CMD_IRQ | \
517 CFG_CMD_PING | \
wdenkfe8c2802002-11-03 00:38:21 +0000518 CFG_CMD_MII )
519#else
520# define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
521 CFG_CMD_ELF | \
522 CFG_CMD_ASKENV | \
523 CFG_CMD_ECHO | \
524 CFG_CMD_I2C | \
525 CFG_CMD_SPI | \
526 CFG_CMD_SDRAM | \
527 CFG_CMD_REGINFO | \
wdenk78137c32003-09-15 18:00:00 +0000528 CFG_CMD_IMMAP | \
529 CFG_CMD_IRQ | \
530 CFG_CMD_PING )
wdenkfe8c2802002-11-03 00:38:21 +0000531#endif /* CONFIG_ETHER_ON_FCC */
532
533/* Where do the internal registers live? */
534#define CFG_IMMR 0xF0000000
535
wdenk78137c32003-09-15 18:00:00 +0000536#undef CONFIG_WATCHDOG /* disable the watchdog */
537
wdenkfe8c2802002-11-03 00:38:21 +0000538/*****************************************************************************
539 *
540 * You should not have to modify any of the following settings
541 *
542 *****************************************************************************/
543
544#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
545#define CONFIG_SBC8260 1 /* on an EST SBC8260 Board */
546#define CONFIG_SACSng 1 /* munged for the SACSng */
547
548/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
549#include <cmd_confdefs.h>
550
wdenk78137c32003-09-15 18:00:00 +0000551
wdenkfe8c2802002-11-03 00:38:21 +0000552/*
553 * Miscellaneous configurable options
554 */
wdenk78137c32003-09-15 18:00:00 +0000555#define CFG_BOOTM_HEADER_QUIET 1 /* Suppress the image header dump */
wdenk42d1f032003-10-15 23:53:47 +0000556 /* in the bootm command. */
wdenk78137c32003-09-15 18:00:00 +0000557#define CFG_BOOTM_PROGESS_QUIET 1 /* Suppress the progress displays, */
wdenk42d1f032003-10-15 23:53:47 +0000558 /* "## <message>" from the bootm cmd */
wdenk78137c32003-09-15 18:00:00 +0000559#define CFG_BOOTP_CHECK_HOSTNAME 1 /* If checkhostname environment is */
wdenk42d1f032003-10-15 23:53:47 +0000560 /* defined, then the hostname param */
561 /* validated against checkhostname. */
wdenk78137c32003-09-15 18:00:00 +0000562#define CFG_BOOTP_RETRY_COUNT 0x40000000 /* # of timeouts before giving up */
563#define CFG_BOOTP_SHORT_RANDOM_DELAY 1 /* Use a short random delay value */
wdenk42d1f032003-10-15 23:53:47 +0000564 /* (limited to maximum of 1024 msec) */
wdenk78137c32003-09-15 18:00:00 +0000565#define CFG_CHK_FOR_ABORT_AT_LEAST_ONCE 1
wdenk42d1f032003-10-15 23:53:47 +0000566 /* Check for abort key presses */
567 /* at least once in dependent of the */
568 /* CONFIG_BOOTDELAY value. */
wdenk78137c32003-09-15 18:00:00 +0000569#define CFG_CONSOLE_INFO_QUIET 1 /* Don't print console @ startup */
570#define CFG_FAULT_ECHO_LINK_DOWN 1 /* Echo the inverted Ethernet link */
wdenk42d1f032003-10-15 23:53:47 +0000571 /* state to the fault LED. */
wdenk78137c32003-09-15 18:00:00 +0000572#define CFG_FAULT_MII_ADDR 0x02 /* MII addr of the PHY to check for */
wdenk42d1f032003-10-15 23:53:47 +0000573 /* the Ethernet link state. */
wdenk78137c32003-09-15 18:00:00 +0000574#define CFG_STATUS_FLASH_UNTIL_TFTP_OK 1 /* Keeping the status LED flashing */
wdenk42d1f032003-10-15 23:53:47 +0000575 /* until the TFTP is successful. */
wdenk78137c32003-09-15 18:00:00 +0000576#define CFG_STATUS_OFF_AFTER_NETBOOT 1 /* After a successful netboot, */
wdenk42d1f032003-10-15 23:53:47 +0000577 /* turn off the STATUS LEDs. */
wdenk78137c32003-09-15 18:00:00 +0000578#define CFG_TFTP_BLINK_STATUS_ON_DATA_IN 1 /* Blink status LED based on */
wdenk42d1f032003-10-15 23:53:47 +0000579 /* incoming data. */
wdenk78137c32003-09-15 18:00:00 +0000580#define CFG_TFTP_BLOCKS_PER_HASH 100 /* For every XX blocks, output a '#' */
wdenk42d1f032003-10-15 23:53:47 +0000581 /* to signify that tftp is moving. */
wdenk78137c32003-09-15 18:00:00 +0000582#define CFG_TFTP_HASHES_PER_FLASH 200 /* For every '#' hashes, */
wdenk42d1f032003-10-15 23:53:47 +0000583 /* flash the status LED. */
wdenk78137c32003-09-15 18:00:00 +0000584#define CFG_TFTP_HASHES_PER_LINE 65 /* Only output XX '#'s per line */
wdenk42d1f032003-10-15 23:53:47 +0000585 /* during the tftp file transfer. */
wdenk78137c32003-09-15 18:00:00 +0000586#define CFG_TFTP_PROGESS_QUIET 1 /* Suppress the progress displays */
wdenk42d1f032003-10-15 23:53:47 +0000587 /* '#'s from the tftp command. */
wdenk78137c32003-09-15 18:00:00 +0000588#define CFG_TFTP_STATUS_QUIET 1 /* Suppress the status displays */
wdenk42d1f032003-10-15 23:53:47 +0000589 /* issued during the tftp command. */
wdenk78137c32003-09-15 18:00:00 +0000590#define CFG_TFTP_TIMEOUT_COUNT 5 /* How many timeouts TFTP will allow */
591 /* before it gives up. */
592
wdenkfe8c2802002-11-03 00:38:21 +0000593#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
594# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
595#else
596# define CFG_CBSIZE 256 /* Console I/O Buffer Size */
597#endif
598
599/* Print Buffer Size */
600#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
601
602#define CFG_MAXARGS 32 /* max number of command args */
603
604#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
605
606#define CFG_LOAD_ADDR 0x400000 /* default load address */
607#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
608
wdenk1d0350e2002-11-11 21:14:20 +0000609#define CFG_ALT_MEMTEST /* Select full-featured memory test */
wdenkfe8c2802002-11-03 00:38:21 +0000610#define CFG_MEMTEST_START 0x2000 /* memtest works from the end of */
611 /* the exception vector table */
612 /* to the end of the DRAM */
613 /* less monitor and malloc area */
614#define CFG_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
615#define CFG_MEM_END_USAGE ( CFG_MONITOR_LEN \
616 + CFG_MALLOC_LEN \
617 + CFG_ENV_SECT_SIZE \
618 + CFG_STACK_USAGE )
619
620#define CFG_MEMTEST_END ( CFG_SDRAM_SIZE * 1024 * 1024 \
621 - CFG_MEM_END_USAGE )
622
623/* valid baudrates */
624#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
625
626/*
627 * Low Level Configuration Settings
628 * (address mappings, register initial values, etc.)
629 * You should know what you are doing if you make changes here.
630 */
631
632#define CFG_FLASH_BASE CFG_FLASH0_BASE
633#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
634#define CFG_SDRAM_BASE CFG_SDRAM0_BASE
635#define CFG_SDRAM_SIZE CFG_SDRAM0_SIZE
636
637/*-----------------------------------------------------------------------
638 * Hard Reset Configuration Words
639 */
640#if defined(CFG_SBC_BOOT_LOW)
641# define CFG_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
642#else
643# define CFG_SBC_HRCW_BOOT_FLAGS (0)
644#endif /* defined(CFG_SBC_BOOT_LOW) */
645
646/* get the HRCW ISB field from CFG_IMMR */
647#define CFG_SBC_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) | \
648 ((CFG_IMMR & 0x01000000) >> 7) | \
649 ((CFG_IMMR & 0x00100000) >> 4) )
650
651#define CFG_HRCW_MASTER ( HRCW_BPS10 | \
652 HRCW_DPPC11 | \
653 CFG_SBC_HRCW_IMMR | \
654 HRCW_MMR00 | \
655 HRCW_LBPC11 | \
656 HRCW_APPC10 | \
657 HRCW_CS10PC00 | \
658 (CFG_SBC_MODCK_H & HRCW_MODCK_H1111) | \
659 CFG_SBC_HRCW_BOOT_FLAGS )
660
661/* no slaves */
662#define CFG_HRCW_SLAVE1 0
663#define CFG_HRCW_SLAVE2 0
664#define CFG_HRCW_SLAVE3 0
665#define CFG_HRCW_SLAVE4 0
666#define CFG_HRCW_SLAVE5 0
667#define CFG_HRCW_SLAVE6 0
668#define CFG_HRCW_SLAVE7 0
669
670/*-----------------------------------------------------------------------
671 * Definitions for initial stack pointer and data area (in DPRAM)
672 */
673#define CFG_INIT_RAM_ADDR CFG_IMMR
674#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
675#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
676#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
677#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
678
679/*-----------------------------------------------------------------------
680 * Start addresses for the final memory configuration
681 * (Set up by the startup code)
682 * Please note that CFG_SDRAM_BASE _must_ start at 0
683 * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
684 */
685#define CFG_MONITOR_BASE CFG_FLASH0_BASE
686
687#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
688# define CFG_RAMBOOT
689#endif
690
691#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
692#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
693
694/*
695 * For booting Linux, the board info and command line data
696 * have to be in the first 8 MB of memory, since this is
697 * the maximum mapped by the Linux kernel during initialization.
698 */
699#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
700
701/*-----------------------------------------------------------------------
702 * FLASH and environment organization
703 */
704
705#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
706#undef CFG_FLASH_PROTECTION /* use hardware protection */
707#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
708#define CFG_MAX_FLASH_SECT (64+4) /* max number of sectors on one chip */
709
710#define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
711#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
712
713#ifndef CFG_RAMBOOT
714# define CFG_ENV_IS_IN_FLASH 1
715
716# ifdef CFG_ENV_IN_OWN_SECT
717# define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
718# define CFG_ENV_SECT_SIZE 0x10000
719# else
720# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
721# define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
722# define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
723# endif /* CFG_ENV_IN_OWN_SECT */
724
725#else
726# define CFG_ENV_IS_IN_NVRAM 1
727# define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
728# define CFG_ENV_SIZE 0x200
729#endif /* CFG_RAMBOOT */
730
731/*-----------------------------------------------------------------------
732 * Cache Configuration
733 */
734#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
735
736#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
737# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
738#endif
739
740/*-----------------------------------------------------------------------
741 * HIDx - Hardware Implementation-dependent Registers 2-11
742 *-----------------------------------------------------------------------
743 * HID0 also contains cache control - initially enable both caches and
744 * invalidate contents, then the final state leaves only the instruction
745 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
746 * but Soft reset does not.
747 *
748 * HID1 has only read-only information - nothing to set.
749 */
750#define CFG_HID0_INIT (HID0_ICE |\
751 HID0_DCE |\
752 HID0_ICFI |\
753 HID0_DCI |\
754 HID0_IFEM |\
755 HID0_ABE)
756
757#define CFG_HID0_FINAL (HID0_ICE |\
758 HID0_IFEM |\
759 HID0_ABE |\
760 HID0_EMCP)
761#define CFG_HID2 0
762
763/*-----------------------------------------------------------------------
764 * RMR - Reset Mode Register
765 *-----------------------------------------------------------------------
766 */
767#define CFG_RMR 0
768
769/*-----------------------------------------------------------------------
770 * BCR - Bus Configuration 4-25
771 *-----------------------------------------------------------------------
772 */
773#define CFG_BCR (BCR_ETM)
774
775/*-----------------------------------------------------------------------
776 * SIUMCR - SIU Module Configuration 4-31
777 *-----------------------------------------------------------------------
778 */
779
780#define CFG_SIUMCR (SIUMCR_DPPC11 |\
781 SIUMCR_L2CPC00 |\
782 SIUMCR_APPC10 |\
783 SIUMCR_MMR00)
784
785
786/*-----------------------------------------------------------------------
787 * SYPCR - System Protection Control 11-9
788 * SYPCR can only be written once after reset!
789 *-----------------------------------------------------------------------
790 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
791 */
wdenk78137c32003-09-15 18:00:00 +0000792#if defined(CONFIG_WATCHDOG)
793#define CFG_SYPCR (SYPCR_SWTC |\
794 SYPCR_BMT |\
795 SYPCR_PBME |\
796 SYPCR_LBME |\
797 SYPCR_SWRI |\
798 SYPCR_SWP |\
wdenk42d1f032003-10-15 23:53:47 +0000799 SYPCR_SWE)
wdenk78137c32003-09-15 18:00:00 +0000800#else
wdenkfe8c2802002-11-03 00:38:21 +0000801#define CFG_SYPCR (SYPCR_SWTC |\
802 SYPCR_BMT |\
803 SYPCR_PBME |\
804 SYPCR_LBME |\
805 SYPCR_SWRI |\
806 SYPCR_SWP)
wdenk78137c32003-09-15 18:00:00 +0000807#endif /* CONFIG_WATCHDOG */
wdenkfe8c2802002-11-03 00:38:21 +0000808
809/*-----------------------------------------------------------------------
810 * TMCNTSC - Time Counter Status and Control 4-40
811 *-----------------------------------------------------------------------
812 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
813 * and enable Time Counter
814 */
815#define CFG_TMCNTSC (TMCNTSC_SEC |\
816 TMCNTSC_ALR |\
817 TMCNTSC_TCF |\
818 TMCNTSC_TCE)
819
820/*-----------------------------------------------------------------------
821 * PISCR - Periodic Interrupt Status and Control 4-42
822 *-----------------------------------------------------------------------
823 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
824 * Periodic timer
825 */
826#define CFG_PISCR (PISCR_PS |\
827 PISCR_PTF |\
828 PISCR_PTE)
829
830/*-----------------------------------------------------------------------
831 * SCCR - System Clock Control 9-8
832 *-----------------------------------------------------------------------
833 */
834#define CFG_SCCR 0
835
836/*-----------------------------------------------------------------------
837 * RCCR - RISC Controller Configuration 13-7
838 *-----------------------------------------------------------------------
839 */
840#define CFG_RCCR 0
841
842/*
843 * Initialize Memory Controller:
844 *
845 * Bank Bus Machine PortSz Device
846 * ---- --- ------- ------ ------
847 * 0 60x GPCM 16 bit FLASH (primary flash - 2MB)
848 * 1 60x GPCM -- bit (Unused)
849 * 2 60x SDRAM 64 bit SDRAM (DIMM)
850 * 3 60x SDRAM 64 bit SDRAM (DIMM)
851 * 4 60x GPCM -- bit (Unused)
852 * 5 60x GPCM -- bit (Unused)
853 * 6 60x GPCM 16 bit FLASH (secondary flash - 2MB)
854 */
855
856/*-----------------------------------------------------------------------
857 * BR0,BR1 - Base Register
858 * Ref: Section 10.3.1 on page 10-14
859 * OR0,OR1 - Option Register
860 * Ref: Section 10.3.2 on page 10-18
861 *-----------------------------------------------------------------------
862 */
863
864/* Bank 0 - Primary FLASH
865 */
866
867/* BR0 is configured as follows:
868 *
869 * - Base address of 0x40000000
870 * - 16 bit port size
871 * - Data errors checking is disabled
872 * - Read and write access
873 * - GPCM 60x bus
874 * - Access are handled by the memory controller according to MSEL
875 * - Not used for atomic operations
876 * - No data pipelining is done
877 * - Valid
878 */
879#define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
880 BRx_PS_16 |\
881 BRx_MS_GPCM_P |\
882 BRx_V)
883
884/* OR0 is configured as follows:
885 *
886 * - 4 MB
887 * - *BCTL0 is asserted upon access to the current memory bank
888 * - *CW / *WE are negated a quarter of a clock earlier
889 * - *CS is output at the same time as the address lines
890 * - Uses a clock cycle length of 5
891 * - *PSDVAL is generated internally by the memory controller
892 * unless *GTA is asserted earlier externally.
893 * - Relaxed timing is generated by the GPCM for accesses
894 * initiated to this memory region.
895 * - One idle clock is inserted between a read access from the
896 * current bank and the next access.
897 */
898#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE) |\
899 ORxG_CSNT |\
900 ORxG_ACS_DIV1 |\
901 ORxG_SCY_5_CLK |\
902 ORxG_TRLX |\
903 ORxG_EHTR)
904
905/*-----------------------------------------------------------------------
906 * BR2,BR3 - Base Register
907 * Ref: Section 10.3.1 on page 10-14
908 * OR2,OR3 - Option Register
909 * Ref: Section 10.3.2 on page 10-16
910 *-----------------------------------------------------------------------
911 */
912
913/* Bank 2,3 - SDRAM DIMM
914 */
915
916/* The BR2 is configured as follows:
917 *
918 * - Base address of 0x00000000
919 * - 64 bit port size (60x bus only)
920 * - Data errors checking is disabled
921 * - Read and write access
922 * - SDRAM 60x bus
923 * - Access are handled by the memory controller according to MSEL
924 * - Not used for atomic operations
925 * - No data pipelining is done
926 * - Valid
927 */
928#define CFG_BR2_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
929 BRx_PS_64 |\
930 BRx_MS_SDRAM_P |\
931 BRx_V)
932
933#define CFG_BR3_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
934 BRx_PS_64 |\
935 BRx_MS_SDRAM_P |\
936 BRx_V)
937
938/* With a 64 MB DIMM, the OR2 is configured as follows:
939 *
940 * - 64 MB
941 * - 4 internal banks per device
942 * - Row start address bit is A8 with PSDMR[PBI] = 0
943 * - 12 row address lines
944 * - Back-to-back page mode
945 * - Internal bank interleaving within save device enabled
946 */
947#if (CFG_SDRAM0_SIZE == 64)
948#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE) |\
949 ORxS_BPD_4 |\
950 ORxS_ROWST_PBI0_A8 |\
951 ORxS_NUMR_12)
952#else
953#error "INVALID SDRAM CONFIGURATION"
954#endif
955
956/*-----------------------------------------------------------------------
957 * PSDMR - 60x Bus SDRAM Mode Register
958 * Ref: Section 10.3.3 on page 10-21
959 *-----------------------------------------------------------------------
960 */
961
962/* Address that the DIMM SPD memory lives at.
963 */
964#define SDRAM_SPD_ADDR 0x50
965
966#if (CFG_SDRAM0_SIZE == 64)
967/* With a 64 MB DIMM, the PSDMR is configured as follows:
968 *
969 * - Bank Based Interleaving,
970 * - Refresh Enable,
971 * - Address Multiplexing where A5 is output on A14 pin
972 * (A6 on A15, and so on),
973 * - use address pins A14-A16 as bank select,
974 * - A9 is output on SDA10 during an ACTIVATE command,
975 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
976 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
977 * is 3 clocks,
978 * - earliest timing for READ/WRITE command after ACTIVATE command is
979 * 2 clocks,
980 * - earliest timing for PRECHARGE after last data was read is 1 clock,
981 * - earliest timing for PRECHARGE after last data was written is 1 clock,
982 * - CAS Latency is 2.
983 */
984#define CFG_PSDMR (PSDMR_RFEN |\
985 PSDMR_SDAM_A14_IS_A5 |\
986 PSDMR_BSMA_A14_A16 |\
987 PSDMR_SDA10_PBI0_A9 |\
988 PSDMR_RFRC_7_CLK |\
989 PSDMR_PRETOACT_3W |\
990 PSDMR_ACTTORW_2W |\
991 PSDMR_LDOTOPRE_1C |\
992 PSDMR_WRC_1C |\
993 PSDMR_CL_2)
994#else
995#error "INVALID SDRAM CONFIGURATION"
996#endif
997
998/*
999 * Shoot for approximately 1MHz on the prescaler.
1000 */
1001#if (CONFIG_8260_CLKIN >= (60 * 1000 * 1000))
1002#define CFG_MPTPR MPTPR_PTP_DIV64
1003#elif (CONFIG_8260_CLKIN >= (30 * 1000 * 1000))
1004#define CFG_MPTPR MPTPR_PTP_DIV32
1005#else
1006#warning "Unconfigured bus clock freq: check CFG_MPTPR and CFG_PSRT are OK"
1007#define CFG_MPTPR MPTPR_PTP_DIV32
1008#endif
1009#define CFG_PSRT 14
1010
1011
1012/*-----------------------------------------------------------------------
1013 * BR6 - Base Register
1014 * Ref: Section 10.3.1 on page 10-14
1015 * OR6 - Option Register
1016 * Ref: Section 10.3.2 on page 10-18
1017 *-----------------------------------------------------------------------
1018 */
1019
1020/* Bank 6 - Secondary FLASH
1021 *
1022 * The secondary FLASH is connected to *CS6
1023 */
1024#if (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE))
1025
1026/* BR6 is configured as follows:
1027 *
1028 * - Base address of 0x60000000
1029 * - 16 bit port size
1030 * - Data errors checking is disabled
1031 * - Read and write access
1032 * - GPCM 60x bus
1033 * - Access are handled by the memory controller according to MSEL
1034 * - Not used for atomic operations
1035 * - No data pipelining is done
1036 * - Valid
1037 */
1038# define CFG_BR6_PRELIM ((CFG_FLASH1_BASE & BRx_BA_MSK) |\
1039 BRx_PS_16 |\
1040 BRx_MS_GPCM_P |\
1041 BRx_V)
1042
1043/* OR6 is configured as follows:
1044 *
1045 * - 2 MB
1046 * - *BCTL0 is asserted upon access to the current memory bank
1047 * - *CW / *WE are negated a quarter of a clock earlier
1048 * - *CS is output at the same time as the address lines
1049 * - Uses a clock cycle length of 5
1050 * - *PSDVAL is generated internally by the memory controller
1051 * unless *GTA is asserted earlier externally.
1052 * - Relaxed timing is generated by the GPCM for accesses
1053 * initiated to this memory region.
1054 * - One idle clock is inserted between a read access from the
1055 * current bank and the next access.
1056 */
1057# define CFG_OR6_PRELIM (MEG_TO_AM(CFG_FLASH1_SIZE) |\
1058 ORxG_CSNT |\
1059 ORxG_ACS_DIV1 |\
1060 ORxG_SCY_5_CLK |\
1061 ORxG_TRLX |\
1062 ORxG_EHTR)
1063#endif /* (defined(CFG_FLASH1_BASE) && defined(CFG_FLASH1_SIZE)) */
1064
1065/*
1066 * Internal Definitions
1067 *
1068 * Boot Flags
1069 */
1070#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
1071#define BOOTFLAG_WARM 0x02 /* Software reboot */
1072
1073#endif /* __CONFIG_H */