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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * armboot - Startup Code for XScale
3 *
4 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
5 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
6 * Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
wdenka8c7c702003-12-06 19:49:23 +00007 * Copyright (C) 2001 Alex Zuepke <azu@sysgo.de>
wdenk1cb8e982003-03-06 21:55:29 +00008 * Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
Wolfgang Denk951a9542006-03-06 23:18:48 +01009 * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
10 * Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
wdenkc6097192002-11-03 00:24:07 +000011 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenk384ae022002-11-05 00:17:55 +000022 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenkc6097192002-11-03 00:24:07 +000023 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30
wdenkc6097192002-11-03 00:24:07 +000031#include <config.h>
32#include <version.h>
Markus Klotzbüchere8cd0082006-02-28 23:11:07 +010033#include <asm/arch/pxa-regs.h>
wdenkc6097192002-11-03 00:24:07 +000034
35.globl _start
wdenk384ae022002-11-05 00:17:55 +000036_start: b reset
wdenkc6097192002-11-03 00:24:07 +000037 ldr pc, _undefined_instruction
38 ldr pc, _software_interrupt
39 ldr pc, _prefetch_abort
40 ldr pc, _data_abort
41 ldr pc, _not_used
42 ldr pc, _irq
43 ldr pc, _fiq
44
wdenk384ae022002-11-05 00:17:55 +000045_undefined_instruction: .word undefined_instruction
wdenkc6097192002-11-03 00:24:07 +000046_software_interrupt: .word software_interrupt
47_prefetch_abort: .word prefetch_abort
48_data_abort: .word data_abort
49_not_used: .word not_used
50_irq: .word irq
51_fiq: .word fiq
52
53 .balignl 16,0xdeadbeef
54
55
56/*
57 * Startup Code (reset vector)
58 *
wdenka8c7c702003-12-06 19:49:23 +000059 * do important init only if we don't start from RAM!
wdenkc6097192002-11-03 00:24:07 +000060 * - relocate armboot to ram
61 * - setup stack
62 * - jump to second stage
63 */
64
wdenkc6097192002-11-03 00:24:07 +000065_TEXT_BASE:
66 .word TEXT_BASE
67
68.globl _armboot_start
69_armboot_start:
70 .word _start
71
72/*
wdenkf6e20fc2004-02-08 19:38:38 +000073 * These are defined in the board-specific linker script.
wdenk47cd00f2003-03-06 13:39:27 +000074 */
wdenk8bde7f72003-06-27 21:31:46 +000075.globl _bss_start
76_bss_start:
wdenkf6e20fc2004-02-08 19:38:38 +000077 .word __bss_start
wdenk47cd00f2003-03-06 13:39:27 +000078
79.globl _bss_end
80_bss_end:
wdenkf6e20fc2004-02-08 19:38:38 +000081 .word _end
wdenk47cd00f2003-03-06 13:39:27 +000082
wdenkc6097192002-11-03 00:24:07 +000083#ifdef CONFIG_USE_IRQ
84/* IRQ stack memory (calculated at run-time) */
85.globl IRQ_STACK_START
86IRQ_STACK_START:
87 .word 0x0badc0de
88
89/* IRQ stack memory (calculated at run-time) */
90.globl FIQ_STACK_START
91FIQ_STACK_START:
92 .word 0x0badc0de
93#endif
94
95
96/****************************************************************************/
wdenk384ae022002-11-05 00:17:55 +000097/* */
98/* the actual reset code */
99/* */
wdenkc6097192002-11-03 00:24:07 +0000100/****************************************************************************/
101
102reset:
wdenk384ae022002-11-05 00:17:55 +0000103 mrs r0,cpsr /* set the cpu to SVC32 mode */
104 bic r0,r0,#0x1f /* (superviser mode, M=10011) */
wdenkc6097192002-11-03 00:24:07 +0000105 orr r0,r0,#0x13
106 msr cpsr,r0
107
wdenka8c7c702003-12-06 19:49:23 +0000108 /*
109 * we do sys-critical inits only at reboot,
110 * not when booting from ram!
111 */
wdenk8aa1a2d2005-04-04 12:44:11 +0000112#ifndef CONFIG_SKIP_LOWLEVEL_INIT
wdenk384ae022002-11-05 00:17:55 +0000113 bl cpu_init_crit /* we do sys-critical inits */
wdenka8c7c702003-12-06 19:49:23 +0000114#endif
wdenkc6097192002-11-03 00:24:07 +0000115
wdenk8aa1a2d2005-04-04 12:44:11 +0000116#ifndef CONFIG_SKIP_RELOCATE_UBOOT
wdenk1cb8e982003-03-06 21:55:29 +0000117relocate: /* relocate U-Boot to RAM */
118 adr r0, _start /* r0 <- current position of code */
wdenk8bde7f72003-06-27 21:31:46 +0000119 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
Wolfgang Denk951a9542006-03-06 23:18:48 +0100120 cmp r0, r1 /* don't reloc during debug */
121 beq stack_setup
wdenk1cb8e982003-03-06 21:55:29 +0000122
wdenkc6097192002-11-03 00:24:07 +0000123 ldr r2, _armboot_start
wdenkf6e20fc2004-02-08 19:38:38 +0000124 ldr r3, _bss_start
Wolfgang Denk951a9542006-03-06 23:18:48 +0100125 sub r2, r3, r2 /* r2 <- size of armboot */
126 add r2, r0, r2 /* r2 <- source end address */
wdenkc6097192002-11-03 00:24:07 +0000127
128copy_loop:
129 ldmia r0!, {r3-r10} /* copy from source address [r0] */
130 stmia r1!, {r3-r10} /* copy to target address [r1] */
131 cmp r0, r2 /* until source end addreee [r2] */
132 ble copy_loop
wdenk8aa1a2d2005-04-04 12:44:11 +0000133#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
wdenkc6097192002-11-03 00:24:07 +0000134
wdenk384ae022002-11-05 00:17:55 +0000135 /* Set up the stack */
wdenk1cb8e982003-03-06 21:55:29 +0000136stack_setup:
wdenka8c7c702003-12-06 19:49:23 +0000137 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
Wolfgang Denk951a9542006-03-06 23:18:48 +0100138 sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
139 sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
wdenka8c7c702003-12-06 19:49:23 +0000140#ifdef CONFIG_USE_IRQ
141 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
142#endif
wdenk47cd00f2003-03-06 13:39:27 +0000143 sub sp, r0, #12 /* leave 3 words for abort-stack */
144
145clear_bss:
Wolfgang Denk951a9542006-03-06 23:18:48 +0100146 ldr r0, _bss_start /* find start of bss segment */
147 ldr r1, _bss_end /* stop here */
148 mov r2, #0x00000000 /* clear */
wdenk47cd00f2003-03-06 13:39:27 +0000149
Wolfgang Denk951a9542006-03-06 23:18:48 +0100150clbss_l:str r2, [r0] /* clear loop... */
wdenk47cd00f2003-03-06 13:39:27 +0000151 add r0, r0, #4
152 cmp r0, r1
wdenka1191902005-01-09 17:12:27 +0000153 ble clbss_l
wdenk47cd00f2003-03-06 13:39:27 +0000154
wdenkc6097192002-11-03 00:24:07 +0000155 ldr pc, _start_armboot
156
wdenk384ae022002-11-05 00:17:55 +0000157_start_armboot: .word start_armboot
wdenkc6097192002-11-03 00:24:07 +0000158
159
160/****************************************************************************/
wdenk384ae022002-11-05 00:17:55 +0000161/* */
162/* CPU_init_critical registers */
163/* */
164/* - setup important registers */
165/* - setup memory timing */
166/* */
wdenkc6097192002-11-03 00:24:07 +0000167/****************************************************************************/
Markus Klotzbücher43638c62006-03-06 15:04:25 +0100168/* mk@tbd: Fix this! */
169#ifdef CONFIG_CPU_MONAHANS
170#undef ICMR
171#undef OSMR3
172#undef OSCR
173#undef OWER
174#undef OIER
175#endif
wdenkc6097192002-11-03 00:24:07 +0000176
Wolfgang Denk951a9542006-03-06 23:18:48 +0100177/* Interrupt-Controller base address */
wdenkc6097192002-11-03 00:24:07 +0000178IC_BASE: .word 0x40d00000
179#define ICMR 0x04
180
181/* Reset-Controller */
wdenk384ae022002-11-05 00:17:55 +0000182RST_BASE: .word 0x40f00030
wdenkc6097192002-11-03 00:24:07 +0000183#define RCSR 0x00
184
wdenk1cb8e982003-03-06 21:55:29 +0000185/* Operating System Timer */
wdenk384ae022002-11-05 00:17:55 +0000186OSTIMER_BASE: .word 0x40a00000
187#define OSMR3 0x0C
188#define OSCR 0x10
189#define OWER 0x18
190#define OIER 0x1C
wdenkc6097192002-11-03 00:24:07 +0000191
Wolfgang Denk951a9542006-03-06 23:18:48 +0100192/* Clock Manager Registers */
Markus Klotzbuecher40b0baf2006-03-24 14:35:25 +0100193#ifdef CONFIG_CPU_MONAHANS
194# ifndef CFG_MONAHANS_RUN_MODE_OSC_RATIO
195# error "You have to define CFG_MONAHANS_RUN_MODE_OSC_RATIO!!"
196# endif
197# ifndef CFG_MONAHANS_TURBO_RUN_MODE_RATIO
198# define CFG_MONAHANS_TURBO_RUN_MODE_RATIO 0x1
199# endif
200#else /* ! CONFIG_CPU_MONAHANS */
wdenka8c7c702003-12-06 19:49:23 +0000201#ifdef CFG_CPUSPEED
wdenk384ae022002-11-05 00:17:55 +0000202CC_BASE: .word 0x41300000
203#define CCCR 0x00
204cpuspeed: .word CFG_CPUSPEED
wdenka8c7c702003-12-06 19:49:23 +0000205#else
206#error "You have to define CFG_CPUSPEED!!"
207#endif
Markus Klotzbuecher40b0baf2006-03-24 14:35:25 +0100208#endif /* CONFIG_CPU_MONAHANS */
wdenk1cb8e982003-03-06 21:55:29 +0000209
Markus Klotzbüchere0269572006-02-07 20:04:48 +0100210 /* takes care the CP15 update has taken place */
211 .macro CPWAIT reg
212 mrc p15,0,\reg,c2,c0,0
213 mov \reg,\reg
wdenkc6097192002-11-03 00:24:07 +0000214 sub pc,pc,#4
215 .endm
216
wdenkc6097192002-11-03 00:24:07 +0000217cpu_init_crit:
218
wdenk384ae022002-11-05 00:17:55 +0000219 /* mask all IRQs */
Markus Klotzbüchere0269572006-02-07 20:04:48 +0100220#ifndef CONFIG_CPU_MONAHANS
wdenkc6097192002-11-03 00:24:07 +0000221 ldr r0, IC_BASE
222 mov r1, #0x00
223 str r1, [r0, #ICMR]
Markus Klotzbüchere0269572006-02-07 20:04:48 +0100224#else
225 /* Step 1 - Enable CP6 permission */
Wolfgang Denk951a9542006-03-06 23:18:48 +0100226 mrc p15, 0, r1, c15, c1, 0 @ read CPAR
227 orr r1, r1, #0x40
228 mcr p15, 0, r1, c15, c1, 0
229 CPWAIT r1
wdenkc6097192002-11-03 00:24:07 +0000230
Wolfgang Denk951a9542006-03-06 23:18:48 +0100231 /* Step 2 - Mask ICMR & ICMR2 */
232 mov r1, #0
233 mcr p6, 0, r1, c1, c0, 0 @ ICMR
234 mcr p6, 0, r1, c7, c0, 0 @ ICMR2
Markus Klotzbüchere8cd0082006-02-28 23:11:07 +0100235
236 /* turn off all clocks but the ones we will definitly require */
Wolfgang Denk951a9542006-03-06 23:18:48 +0100237 ldr r1, =CKENA
238 ldr r2, =(CKENA_22_FFUART | CKENA_10_SRAM | CKENA_9_SMC | CKENA_8_DMC)
239 str r2, [r1]
240 ldr r1, =CKENB
241 ldr r2, =(CKENB_6_IRQ)
242 str r2, [r1]
Markus Klotzbüchere0269572006-02-07 20:04:48 +0100243#endif
wdenk1cb8e982003-03-06 21:55:29 +0000244
Markus Klotzbuecher40b0baf2006-03-24 14:35:25 +0100245 /* set clock speed */
246#ifdef CONFIG_CPU_MONAHANS
247 ldr r0, =ACCR
248 ldr r1, =(((CFG_MONAHANS_TURBO_RUN_MODE_RATIO<<8) & ACCR_XN_MASK) | (CFG_MONAHANS_RUN_MODE_OSC_RATIO & ACCR_XL_MASK))
249 str r1, [r0]
250#else /* ! CONFIG_CPU_MONAHANS */
Markus Klotzbüchere0269572006-02-07 20:04:48 +0100251#ifdef CFG_CPUSPEED
wdenkc6097192002-11-03 00:24:07 +0000252 ldr r0, CC_BASE
253 ldr r1, cpuspeed
254 str r1, [r0, #CCCR]
wdenk1cb8e982003-03-06 21:55:29 +0000255 mov r0, #2
wdenk7f6c2cb2002-11-10 22:06:23 +0000256 mcr p14, 0, r0, c6, c0, 0
wdenk1cb8e982003-03-06 21:55:29 +0000257
258setspeed_done:
Wolfgang Denk951a9542006-03-06 23:18:48 +0100259
Markus Klotzbüchere0269572006-02-07 20:04:48 +0100260#endif /* CFG_CPUSPEED */
261#endif /* CONFIG_CPU_MONAHANS */
wdenkc6097192002-11-03 00:24:07 +0000262
263 /*
264 * before relocating, we have to setup RAM timing
265 * because memory timing is board-dependend, you will
wdenk400558b2005-04-02 23:52:25 +0000266 * find a lowlevel_init.S in your board directory.
wdenkc6097192002-11-03 00:24:07 +0000267 */
268 mov ip, lr
wdenk400558b2005-04-02 23:52:25 +0000269 bl lowlevel_init
wdenkc6097192002-11-03 00:24:07 +0000270 mov lr, ip
271
272 /* Memory interfaces are working. Disable MMU and enable I-cache. */
Wolfgang Denk951a9542006-03-06 23:18:48 +0100273 /* mk: hmm, this is not in the monahans docs, leave it now but
Markus Klotzbüchere0269572006-02-07 20:04:48 +0100274 * check here if it doesn't work :-) */
wdenkc6097192002-11-03 00:24:07 +0000275
wdenk384ae022002-11-05 00:17:55 +0000276 ldr r0, =0x2001 /* enable access to all coproc. */
wdenkc6097192002-11-03 00:24:07 +0000277 mcr p15, 0, r0, c15, c1, 0
Markus Klotzbüchere0269572006-02-07 20:04:48 +0100278 CPWAIT r0
wdenkc6097192002-11-03 00:24:07 +0000279
280 mcr p15, 0, r0, c7, c10, 4 /* drain the write & fill buffers */
Markus Klotzbüchere0269572006-02-07 20:04:48 +0100281 CPWAIT r0
wdenkc6097192002-11-03 00:24:07 +0000282
wdenk384ae022002-11-05 00:17:55 +0000283 mcr p15, 0, r0, c7, c7, 0 /* flush Icache, Dcache and BTB */
Markus Klotzbüchere0269572006-02-07 20:04:48 +0100284 CPWAIT r0
wdenkc6097192002-11-03 00:24:07 +0000285
286 mcr p15, 0, r0, c8, c7, 0 /* flush instuction and data TLBs */
Markus Klotzbüchere0269572006-02-07 20:04:48 +0100287 CPWAIT r0
wdenkc6097192002-11-03 00:24:07 +0000288
wdenk384ae022002-11-05 00:17:55 +0000289 /* Enable the Icache */
wdenkc6097192002-11-03 00:24:07 +0000290/*
291 mrc p15, 0, r0, c1, c0, 0
292 orr r0, r0, #0x1800
293 mcr p15, 0, r0, c1, c0, 0
wdenk699b13a2002-11-03 18:03:52 +0000294 CPWAIT
wdenkc6097192002-11-03 00:24:07 +0000295*/
296 mov pc, lr
297
298
299/****************************************************************************/
wdenk384ae022002-11-05 00:17:55 +0000300/* */
301/* Interrupt handling */
302/* */
wdenkc6097192002-11-03 00:24:07 +0000303/****************************************************************************/
304
wdenk384ae022002-11-05 00:17:55 +0000305/* IRQ stack frame */
wdenkc6097192002-11-03 00:24:07 +0000306
307#define S_FRAME_SIZE 72
308
309#define S_OLD_R0 68
310#define S_PSR 64
311#define S_PC 60
312#define S_LR 56
313#define S_SP 52
314
315#define S_IP 48
316#define S_FP 44
317#define S_R10 40
318#define S_R9 36
319#define S_R8 32
320#define S_R7 28
321#define S_R6 24
322#define S_R5 20
323#define S_R4 16
324#define S_R3 12
325#define S_R2 8
326#define S_R1 4
327#define S_R0 0
328
329#define MODE_SVC 0x13
330
wdenk384ae022002-11-05 00:17:55 +0000331 /* use bad_save_user_regs for abort/prefetch/undef/swi ... */
wdenkc6097192002-11-03 00:24:07 +0000332
333 .macro bad_save_user_regs
334 sub sp, sp, #S_FRAME_SIZE
wdenk384ae022002-11-05 00:17:55 +0000335 stmia sp, {r0 - r12} /* Calling r0-r12 */
336 add r8, sp, #S_PC
wdenkc6097192002-11-03 00:24:07 +0000337
wdenkf6e20fc2004-02-08 19:38:38 +0000338 ldr r2, _armboot_start
339 sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
Wolfgang Denk951a9542006-03-06 23:18:48 +0100340 sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
wdenk384ae022002-11-05 00:17:55 +0000341 ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
342 add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
wdenkc6097192002-11-03 00:24:07 +0000343
344 add r5, sp, #S_SP
345 mov r1, lr
wdenk384ae022002-11-05 00:17:55 +0000346 stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
wdenkc6097192002-11-03 00:24:07 +0000347 mov r0, sp
348 .endm
349
350
wdenk384ae022002-11-05 00:17:55 +0000351 /* use irq_save_user_regs / irq_restore_user_regs for */
352 /* IRQ/FIQ handling */
wdenkc6097192002-11-03 00:24:07 +0000353
354 .macro irq_save_user_regs
355 sub sp, sp, #S_FRAME_SIZE
wdenk384ae022002-11-05 00:17:55 +0000356 stmia sp, {r0 - r12} /* Calling r0-r12 */
357 add r8, sp, #S_PC
358 stmdb r8, {sp, lr}^ /* Calling SP, LR */
359 str lr, [r8, #0] /* Save calling PC */
360 mrs r6, spsr
361 str r6, [r8, #4] /* Save CPSR */
362 str r0, [r8, #8] /* Save OLD_R0 */
wdenkc6097192002-11-03 00:24:07 +0000363 mov r0, sp
364 .endm
365
366 .macro irq_restore_user_regs
367 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
368 mov r0, r0
369 ldr lr, [sp, #S_PC] @ Get PC
370 add sp, sp, #S_FRAME_SIZE
371 subs pc, lr, #4 @ return & move spsr_svc into cpsr
372 .endm
373
374 .macro get_bad_stack
wdenkf6e20fc2004-02-08 19:38:38 +0000375 ldr r13, _armboot_start @ setup our mode stack
376 sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
377 sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
wdenkc6097192002-11-03 00:24:07 +0000378
379 str lr, [r13] @ save caller lr / spsr
380 mrs lr, spsr
wdenk384ae022002-11-05 00:17:55 +0000381 str lr, [r13, #4]
wdenkc6097192002-11-03 00:24:07 +0000382
383 mov r13, #MODE_SVC @ prepare SVC-Mode
384 msr spsr_c, r13
385 mov lr, pc
386 movs pc, lr
387 .endm
388
389 .macro get_irq_stack @ setup IRQ stack
390 ldr sp, IRQ_STACK_START
391 .endm
392
393 .macro get_fiq_stack @ setup FIQ stack
394 ldr sp, FIQ_STACK_START
395 .endm
396
397
398/****************************************************************************/
wdenk384ae022002-11-05 00:17:55 +0000399/* */
400/* exception handlers */
401/* */
wdenkc6097192002-11-03 00:24:07 +0000402/****************************************************************************/
403
wdenk384ae022002-11-05 00:17:55 +0000404 .align 5
wdenkc6097192002-11-03 00:24:07 +0000405undefined_instruction:
406 get_bad_stack
407 bad_save_user_regs
wdenk384ae022002-11-05 00:17:55 +0000408 bl do_undefined_instruction
wdenkc6097192002-11-03 00:24:07 +0000409
410 .align 5
411software_interrupt:
412 get_bad_stack
413 bad_save_user_regs
wdenk384ae022002-11-05 00:17:55 +0000414 bl do_software_interrupt
wdenkc6097192002-11-03 00:24:07 +0000415
416 .align 5
417prefetch_abort:
418 get_bad_stack
419 bad_save_user_regs
wdenk384ae022002-11-05 00:17:55 +0000420 bl do_prefetch_abort
wdenkc6097192002-11-03 00:24:07 +0000421
422 .align 5
423data_abort:
424 get_bad_stack
425 bad_save_user_regs
wdenk384ae022002-11-05 00:17:55 +0000426 bl do_data_abort
wdenkc6097192002-11-03 00:24:07 +0000427
428 .align 5
429not_used:
430 get_bad_stack
431 bad_save_user_regs
wdenk384ae022002-11-05 00:17:55 +0000432 bl do_not_used
wdenkc6097192002-11-03 00:24:07 +0000433
434#ifdef CONFIG_USE_IRQ
435
436 .align 5
437irq:
438 get_irq_stack
439 irq_save_user_regs
wdenk384ae022002-11-05 00:17:55 +0000440 bl do_irq
wdenkc6097192002-11-03 00:24:07 +0000441 irq_restore_user_regs
442
443 .align 5
444fiq:
445 get_fiq_stack
446 irq_save_user_regs /* someone ought to write a more */
wdenk384ae022002-11-05 00:17:55 +0000447 bl do_fiq /* effiction fiq_save_user_regs */
wdenkc6097192002-11-03 00:24:07 +0000448 irq_restore_user_regs
449
450#else
451
452 .align 5
453irq:
454 get_bad_stack
455 bad_save_user_regs
wdenk384ae022002-11-05 00:17:55 +0000456 bl do_irq
wdenkc6097192002-11-03 00:24:07 +0000457
458 .align 5
459fiq:
460 get_bad_stack
461 bad_save_user_regs
wdenk384ae022002-11-05 00:17:55 +0000462 bl do_fiq
wdenkc6097192002-11-03 00:24:07 +0000463
464#endif
465
wdenk1cb8e982003-03-06 21:55:29 +0000466/****************************************************************************/
Wolfgang Denk951a9542006-03-06 23:18:48 +0100467/* */
wdenk1cb8e982003-03-06 21:55:29 +0000468/* Reset function: the PXA250 doesn't have a reset function, so we have to */
Wolfgang Denk951a9542006-03-06 23:18:48 +0100469/* perform a watchdog timeout for a soft reset. */
470/* */
wdenk1cb8e982003-03-06 21:55:29 +0000471/****************************************************************************/
472
wdenkc6097192002-11-03 00:24:07 +0000473 .align 5
474.globl reset_cpu
wdenk1cb8e982003-03-06 21:55:29 +0000475
Wolfgang Denk951a9542006-03-06 23:18:48 +0100476 /* FIXME: this code is PXA250 specific. How is this handled on */
477 /* other XScale processors? */
wdenk1cb8e982003-03-06 21:55:29 +0000478
wdenkc6097192002-11-03 00:24:07 +0000479reset_cpu:
wdenk1cb8e982003-03-06 21:55:29 +0000480
wdenk384ae022002-11-05 00:17:55 +0000481 /* We set OWE:WME (watchdog enable) and wait until timeout happens */
wdenkc6097192002-11-03 00:24:07 +0000482
wdenk384ae022002-11-05 00:17:55 +0000483 ldr r0, OSTIMER_BASE
484 ldr r1, [r0, #OWER]
Wolfgang Denk951a9542006-03-06 23:18:48 +0100485 orr r1, r1, #0x0001 /* bit0: WME */
wdenk384ae022002-11-05 00:17:55 +0000486 str r1, [r0, #OWER]
487
488 /* OS timer does only wrap every 1165 seconds, so we have to set */
Wolfgang Denk951a9542006-03-06 23:18:48 +0100489 /* the match register as well. */
wdenk384ae022002-11-05 00:17:55 +0000490
Wolfgang Denk951a9542006-03-06 23:18:48 +0100491 ldr r1, [r0, #OSCR] /* read OS timer */
wdenk384ae022002-11-05 00:17:55 +0000492 add r1, r1, #0x800 /* let OSMR3 match after */
493 add r1, r1, #0x800 /* 4096*(1/3.6864MHz)=1ms */
494 str r1, [r0, #OSMR3]
495
496reset_endless:
497
498 b reset_endless