blob: 42fdb370a784648ac706fae3a04e29c8218abe4d [file] [log] [blame]
Stefan Roese211ea912007-10-22 07:34:34 +02001/*
Grant Erickson8a24c072008-05-22 14:44:24 -07002 * Copyright (c) 2008 Nuovation System Designs, LLC
3 * Grant Erickson <gerickson@nuovations.com>
4 *
Stefan Roese869d14b2008-05-10 10:30:36 +02005 * (C) Copyright 2007-2008
Stefan Roese211ea912007-10-22 07:34:34 +02006 * Stefan Roese, DENX Software Engineering, sr@denx.de.
7 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02008 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese211ea912007-10-22 07:34:34 +02009 */
10
11/************************************************************************
12 * makalu.h - configuration for AMCC Makalu (405EX)
13 ***********************************************************************/
14
15#ifndef __CONFIG_H
16#define __CONFIG_H
17
18/*-----------------------------------------------------------------------
19 * High Level Configuration Options
20 *----------------------------------------------------------------------*/
21#define CONFIG_MAKALU 1 /* Board is Makalu */
Stefan Roese211ea912007-10-22 07:34:34 +020022#define CONFIG_405EX 1 /* Specifc 405EX support*/
23#define CONFIG_SYS_CLK_FREQ 33330000 /* ext frequency to pll */
24
Wolfgang Denk2ae18242010-10-06 09:05:45 +020025#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
26
Stefan Roese490f2042008-06-06 15:55:03 +020027/*
28 * Include common defines/options for all AMCC eval boards
29 */
30#define CONFIG_HOSTNAME makalu
31#define CONFIG_ADDMISC "addmisc=setenv bootargs ${bootargs} rtc-x1205.probe=0,0x6f\0"
32#include "amcc-common.h"
33
Stefan Roese211ea912007-10-22 07:34:34 +020034#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
35
36/*-----------------------------------------------------------------------
37 * Base addresses -- Note these are effective addresses where the
38 * actual resources get mapped (not physical addresses)
39 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020040#define CONFIG_SYS_FLASH_BASE 0xFC000000
41#define CONFIG_SYS_FPGA_BASE 0xF0000000
Stefan Roese211ea912007-10-22 07:34:34 +020042
43/*-----------------------------------------------------------------------
Grant Erickson8a24c072008-05-22 14:44:24 -070044 * Initial RAM & Stack Pointer Configuration Options
45 *
46 * There are traditionally three options for the primordial
47 * (i.e. initial) stack usage on the 405-series:
48 *
49 * 1) On-chip Memory (OCM) (i.e. SRAM)
50 * 2) Data cache
51 * 3) SDRAM
52 *
53 * For the 405EX(r), there is no OCM, so we are left with (2) or (3)
54 * the latter of which is less than desireable since it requires
55 * setting up the SDRAM and ECC in assembly code.
56 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057 * To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip
Grant Erickson8a24c072008-05-22 14:44:24 -070058 * select on the External Bus Controller (EBC) and then select a
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059 * value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid,
60 * physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and
61 * select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid,
Grant Erickson8a24c072008-05-22 14:44:24 -070062 * physical SDRAM to use (3).
63 *-----------------------------------------------------------------------*/
64
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065#define CONFIG_SYS_INIT_DCACHE_CS 4
Grant Erickson8a24c072008-05-22 14:44:24 -070066
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067#if defined(CONFIG_SYS_INIT_DCACHE_CS)
68#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + ( 1 << 30)) /* 1 GiB */
Grant Erickson8a24c072008-05-22 14:44:24 -070069#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_SDRAM_BASE + (32 << 20)) /* 32 MiB */
71#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
Grant Erickson8a24c072008-05-22 14:44:24 -070072
Wolfgang Denk553f0982010-10-26 13:32:32 +020073#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10) /* 4 KiB */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020074#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Stefan Roese211ea912007-10-22 07:34:34 +020075
Grant Erickson8a24c072008-05-22 14:44:24 -070076/*
77 * If the data cache is being used for the primordial stack and global
78 * data area, the POST word must be placed somewhere else. The General
79 * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
80 * its compare and mask register contents across reset, so it is used
81 * for the POST word.
82 */
83
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#if defined(CONFIG_SYS_INIT_DCACHE_CS)
85# define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Michael Zaidman800eb092010-09-20 08:51:53 +020086# define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
Grant Erickson8a24c072008-05-22 14:44:24 -070087#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088# define CONFIG_SYS_INIT_EXTRA_SIZE 16
89# define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090# define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_INIT_RAM_ADDR
91#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
Stefan Roese211ea912007-10-22 07:34:34 +020092
93/*-----------------------------------------------------------------------
94 * Serial Port
95 *----------------------------------------------------------------------*/
Stefan Roese550650d2010-09-20 16:05:31 +020096#define CONFIG_CONS_INDEX 1 /* Use UART0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no ext. clk */
Stefan Roese211ea912007-10-22 07:34:34 +020098
Stefan Roese211ea912007-10-22 07:34:34 +020099/*-----------------------------------------------------------------------
100 * Environment
101 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200102#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Stefan Roese211ea912007-10-22 07:34:34 +0200103
104/*-----------------------------------------------------------------------
105 * FLASH related
106 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200108#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Stefan Roese211ea912007-10-22 07:34:34 +0200109
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
111#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
112#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
Stefan Roese211ea912007-10-22 07:34:34 +0200113
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
115#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Stefan Roese211ea912007-10-22 07:34:34 +0200116
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
118#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Stefan Roese211ea912007-10-22 07:34:34 +0200119
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200120#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200121#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200123#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
Stefan Roese211ea912007-10-22 07:34:34 +0200124
125/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200126#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
127#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200128#endif /* CONFIG_ENV_IS_IN_FLASH */
Stefan Roese211ea912007-10-22 07:34:34 +0200129
130/*-----------------------------------------------------------------------
131 * DDR SDRAM
132 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */
Grant Erickson8a24c072008-05-22 14:44:24 -0700134
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_SDRAM0_MB0CF_BASE (( 0 << 20) + CONFIG_SYS_SDRAM_BASE)
136#define CONFIG_SYS_SDRAM0_MB1CF_BASE ((128 << 20) + CONFIG_SYS_SDRAM_BASE)
Grant Erickson8a24c072008-05-22 14:44:24 -0700137
138/* DDR1/2 SDRAM Device Control Register Data Values */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_SDRAM0_MB0CF ((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3) | \
Grant Erickson8a24c072008-05-22 14:44:24 -0700140 SDRAM_RXBAS_SDSZ_128MB | \
141 SDRAM_RXBAS_SDAM_MODE2 | \
142 SDRAM_RXBAS_SDBE_ENABLE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_SDRAM0_MB1CF ((CONFIG_SYS_SDRAM0_MB1CF_BASE >> 3) | \
Grant Erickson8a24c072008-05-22 14:44:24 -0700144 SDRAM_RXBAS_SDSZ_128MB | \
145 SDRAM_RXBAS_SDAM_MODE2 | \
146 SDRAM_RXBAS_SDBE_ENABLE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
148#define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
149#define CONFIG_SYS_SDRAM0_MCOPT1 0x04322000
150#define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000
151#define CONFIG_SYS_SDRAM0_MODT0 0x01800000
152#define CONFIG_SYS_SDRAM0_MODT1 0x00000000
153#define CONFIG_SYS_SDRAM0_CODT 0x0080f837
154#define CONFIG_SYS_SDRAM0_RTR 0x06180000
155#define CONFIG_SYS_SDRAM0_INITPLR0 0xa8380000
156#define CONFIG_SYS_SDRAM0_INITPLR1 0x81900400
157#define CONFIG_SYS_SDRAM0_INITPLR2 0x81020000
158#define CONFIG_SYS_SDRAM0_INITPLR3 0x81030000
159#define CONFIG_SYS_SDRAM0_INITPLR4 0x81010404
160#define CONFIG_SYS_SDRAM0_INITPLR5 0x81000542
161#define CONFIG_SYS_SDRAM0_INITPLR6 0x81900400
162#define CONFIG_SYS_SDRAM0_INITPLR7 0x8D080000
163#define CONFIG_SYS_SDRAM0_INITPLR8 0x8D080000
164#define CONFIG_SYS_SDRAM0_INITPLR9 0x8D080000
165#define CONFIG_SYS_SDRAM0_INITPLR10 0x8D080000
166#define CONFIG_SYS_SDRAM0_INITPLR11 0x81000442
167#define CONFIG_SYS_SDRAM0_INITPLR12 0x81010780
168#define CONFIG_SYS_SDRAM0_INITPLR13 0x81010400
169#define CONFIG_SYS_SDRAM0_INITPLR14 0x00000000
170#define CONFIG_SYS_SDRAM0_INITPLR15 0x00000000
171#define CONFIG_SYS_SDRAM0_RQDC 0x80000038
172#define CONFIG_SYS_SDRAM0_RFDC 0x00000209
173#define CONFIG_SYS_SDRAM0_RDCC 0x40000000
174#define CONFIG_SYS_SDRAM0_DLCR 0x030000a5
175#define CONFIG_SYS_SDRAM0_CLKTR 0x80000000
176#define CONFIG_SYS_SDRAM0_WRDTR 0x00000000
177#define CONFIG_SYS_SDRAM0_SDTR1 0x80201000
178#define CONFIG_SYS_SDRAM0_SDTR2 0x32204232
179#define CONFIG_SYS_SDRAM0_SDTR3 0x080b0d1a
180#define CONFIG_SYS_SDRAM0_MMODE 0x00000442
181#define CONFIG_SYS_SDRAM0_MEMODE 0x00000404
Stefan Roese211ea912007-10-22 07:34:34 +0200182
183/*-----------------------------------------------------------------------
184 * I2C
185 *----------------------------------------------------------------------*/
Dirk Eibach880540d2013-04-25 02:40:01 +0000186#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
Stefan Roese211ea912007-10-22 07:34:34 +0200187
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
189#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */
190#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
Stefan Roese211ea912007-10-22 07:34:34 +0200191
192/* Standard DTT sensor configuration */
193#define CONFIG_DTT_DS1775 1
194#define CONFIG_DTT_SENSORS { 0 }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_I2C_DTT_ADDR 0x48
Stefan Roese211ea912007-10-22 07:34:34 +0200196
197/* RTC configuration */
198#define CONFIG_RTC_X1205 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_I2C_RTC_ADDR 0x6f
Stefan Roese211ea912007-10-22 07:34:34 +0200200
201/*-----------------------------------------------------------------------
202 * Ethernet
203 *----------------------------------------------------------------------*/
204#define CONFIG_M88E1111_PHY 1
205#define CONFIG_IBM_EMAC4_V4 1
Grant Erickson1740c1b2008-07-08 08:35:00 -0700206#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_RGMII_RGMII
Stefan Roese211ea912007-10-22 07:34:34 +0200207#define CONFIG_PHY_ADDR 6 /* PHY address, See schematics */
208
209#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
210#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
211
212#define CONFIG_HAS_ETH0 1
213
Stefan Roese211ea912007-10-22 07:34:34 +0200214#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
Stefan Roeseecdcbd42007-11-16 14:00:59 +0100215#define CONFIG_PHY1_ADDR 0
Stefan Roese211ea912007-10-22 07:34:34 +0200216
Stefan Roese490f2042008-06-06 15:55:03 +0200217/*
218 * Default environment variables
219 */
Stefan Roese211ea912007-10-22 07:34:34 +0200220#define CONFIG_EXTRA_ENV_SETTINGS \
Stefan Roese490f2042008-06-06 15:55:03 +0200221 CONFIG_AMCC_DEF_ENV \
222 CONFIG_AMCC_DEF_ENV_POWERPC \
223 CONFIG_AMCC_DEF_ENV_PPC_OLD \
224 CONFIG_AMCC_DEF_ENV_NOR_UPD \
Stefan Roeseecdcbd42007-11-16 14:00:59 +0100225 "kernel_addr=fc000000\0" \
Stefan Roese869d14b2008-05-10 10:30:36 +0200226 "fdt_addr=fc1e0000\0" \
Stefan Roeseecdcbd42007-11-16 14:00:59 +0100227 "ramdisk_addr=fc200000\0" \
Stefan Roese211ea912007-10-22 07:34:34 +0200228 "pciconfighost=1\0" \
229 "pcie_mode=RP:RP\0" \
230 ""
Stefan Roese211ea912007-10-22 07:34:34 +0200231
232/*
Stefan Roese490f2042008-06-06 15:55:03 +0200233 * Commands additional to the ones defined in amcc-common.h
Stefan Roese211ea912007-10-22 07:34:34 +0200234 */
Stefan Roese211ea912007-10-22 07:34:34 +0200235#define CONFIG_CMD_DATE
Stefan Roese211ea912007-10-22 07:34:34 +0200236#define CONFIG_CMD_DTT
Stefan Roese211ea912007-10-22 07:34:34 +0200237#define CONFIG_CMD_PCI
Stefan Roese211ea912007-10-22 07:34:34 +0200238
239/* POST support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
241 CONFIG_SYS_POST_CPU | \
242 CONFIG_SYS_POST_ETHER | \
243 CONFIG_SYS_POST_I2C | \
244 CONFIG_SYS_POST_MEMORY | \
245 CONFIG_SYS_POST_UART)
Stefan Roese211ea912007-10-22 07:34:34 +0200246
247/* Define here the base-addresses of the UARTs to test in POST */
Stefan Roese5d7c73e2010-09-29 16:58:38 +0200248#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \
249 CONFIG_SYS_NS16550_COM2 }
Stefan Roese211ea912007-10-22 07:34:34 +0200250
251#define CONFIG_LOGBUFFER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */
Stefan Roese211ea912007-10-22 07:34:34 +0200253
Stefan Roese211ea912007-10-22 07:34:34 +0200254/*-----------------------------------------------------------------------
255 * PCI stuff
256 *----------------------------------------------------------------------*/
Gabor Juhos842033e2013-05-30 07:06:12 +0000257#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Stefan Roese211ea912007-10-22 07:34:34 +0200258#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
259#define CONFIG_PCI_CONFIG_HOST_BRIDGE
260
261/*-----------------------------------------------------------------------
262 * PCIe stuff
263 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_PCIE_MEMBASE 0x90000000 /* mapped PCIe memory */
265#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* 128 Meg, smallest incr per port */
Stefan Roese211ea912007-10-22 07:34:34 +0200266
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_PCIE0_CFGBASE 0xa0000000 /* remote access */
268#define CONFIG_SYS_PCIE0_XCFGBASE 0xb0000000 /* local access */
269#define CONFIG_SYS_PCIE0_CFGMASK 0xe0000001 /* 512 Meg */
Stefan Roese211ea912007-10-22 07:34:34 +0200270
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_PCIE1_CFGBASE 0xc0000000 /* remote access */
272#define CONFIG_SYS_PCIE1_XCFGBASE 0xd0000000 /* local access */
273#define CONFIG_SYS_PCIE1_CFGMASK 0xe0000001 /* 512 Meg */
Stefan Roese211ea912007-10-22 07:34:34 +0200274
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_PCIE0_UTLBASE 0xef502000
276#define CONFIG_SYS_PCIE1_UTLBASE 0xef503000
Stefan Roese211ea912007-10-22 07:34:34 +0200277
278/* base address of inbound PCIe window */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_PCIE_INBOUND_BASE 0x0000000000000000ULL
Stefan Roese211ea912007-10-22 07:34:34 +0200280
Stefan Roese211ea912007-10-22 07:34:34 +0200281/*-----------------------------------------------------------------------
Stefan Roese211ea912007-10-22 07:34:34 +0200282 * External Bus Controller (EBC) Setup
283 *----------------------------------------------------------------------*/
284/* Memory Bank 0 (NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_EBC_PB0AP 0x08033700
286#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xda000)
Stefan Roese211ea912007-10-22 07:34:34 +0200287
288/* Memory Bank 2 (CPLD) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_EBC_PB2AP 0x9400C800
290#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0x800,BS=1MB,BU=R/W,BW=8bit */
Stefan Roese211ea912007-10-22 07:34:34 +0200291
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292#define CONFIG_SYS_EBC_CFG 0x7FC00000 /* EBC0_CFG */
Stefan Roese211ea912007-10-22 07:34:34 +0200293
294/*-----------------------------------------------------------------------
295 * GPIO Setup
296 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
Stefan Roeseecdcbd42007-11-16 14:00:59 +0100298{ \
299/* GPIO Core 0 */ \
300{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO0 EBC_DATA_PAR(0) */ \
301{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO1 EBC_DATA_PAR(1) */ \
302{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO2 EBC_DATA_PAR(2) */ \
303{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO3 EBC_DATA_PAR(3) */ \
Stefan Roese7cfc12a2007-12-08 14:47:34 +0100304{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO4 EBC_DATA(20) USB2_DATA(4) */ \
305{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO5 EBC_DATA(21) USB2_DATA(5) */ \
306{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO6 EBC_DATA(22) USB2_DATA(6) */ \
307{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO7 EBC_DATA(23) USB2_DATA(7) */ \
Stefan Roese8be76092007-11-27 11:57:35 +0100308{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 CS(1)/NFCE(1) IRQ(7) */ \
309{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 CS(2)/NFCE(2) IRQ(8) */ \
310{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 CS(3)/NFCE(3) IRQ(9) */ \
Stefan Roeseecdcbd42007-11-16 14:00:59 +0100311{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 IRQ(6) */ \
Stefan Roese7cfc12a2007-12-08 14:47:34 +0100312{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16) USB2_DATA(0) */ \
313{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17) USB2_DATA(1) */ \
314{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 EBC_DATA(18) USB2_DATA(2) */ \
315{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 EBC_DATA(19) USB2_DATA(3) */ \
Stefan Roeseecdcbd42007-11-16 14:00:59 +0100316{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD UART1_CTS */ \
317{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR UART1_RTS */ \
318{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS */ \
319{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS */ \
320{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO20 UART0_DTR UART1_TX */ \
321{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO21 UART0_RI UART1_RX */ \
322{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ DMA_ACK2 */ \
323{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK DMA_REQ2 */ \
324{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ DMA_EOT2 IRQ(4) */ \
325{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK DMA_ACK3 IRQ(3) */ \
326{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5) DMA_EOT0 TS(3) */ \
327{GPIO0_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ DMA_EOT3 IRQ(5) */ \
328{GPIO0_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 */ \
Stefan Roese8be76092007-11-27 11:57:35 +0100329{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO29 DMA_EOT1 IRQ(2) */ \
330{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO30 DMA_REQ1 IRQ(1) */ \
331{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0}, /* GPIO31 DMA_ACK1 IRQ(0) */ \
Stefan Roeseecdcbd42007-11-16 14:00:59 +0100332} \
333}
334
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_GPIO_PCIE_RST 23
336#define CONFIG_SYS_GPIO_PCIE_CLKREQ 27
337#define CONFIG_SYS_GPIO_PCIE_WAKE 28
Stefan Roese211ea912007-10-22 07:34:34 +0200338
Stefan Roese211ea912007-10-22 07:34:34 +0200339#endif /* __CONFIG_H */