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Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +02001/*
2 * (C) Copyright 2009
3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +02007 */
8
9#include <common.h>
10#include <netdev.h>
11#include <asm/cache.h>
12#include <u-boot/md5.h>
Lei Wena7efd712011-10-18 20:11:42 +053013#include <asm/io.h>
14#include <asm/arch/cpu.h>
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020015#include <asm/arch/kirkwood.h>
DrEagle3fe3b4f2014-07-25 21:07:30 +020016#include <mvebu_mmc.h>
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020017
18#define BUFLEN 16
19
20void reset_cpu(unsigned long ignored)
21{
22 struct kwcpu_registers *cpureg =
23 (struct kwcpu_registers *)KW_CPU_REG_BASE;
24
25 writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
26 &cpureg->rstoutn_mask);
27 writel(readl(&cpureg->sys_soft_rst) | 1,
28 &cpureg->sys_soft_rst);
29 while (1) ;
30}
31
32/*
33 * Generates Ramdom hex number reading some time varient system registers
34 * and using md5 algorithm
35 */
36unsigned char get_random_hex(void)
37{
38 int i;
39 u32 inbuf[BUFLEN];
40 u8 outbuf[BUFLEN];
41
42 /*
Prafulla Wadaskarc0cd0202010-09-20 17:19:42 +053043 * in case of 88F6281/88F6282/88F6192 A0,
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020044 * Bit7 need to reset to generate random values in KW_REG_UNDOC_0x1470
Prafulla Wadaskarc0cd0202010-09-20 17:19:42 +053045 * Soc reg offsets KW_REG_UNDOC_0x1470 and KW_REG_UNDOC_0x1478 are
46 * reserved regs and does not have names at this moment
47 * (no errata available)
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020048 */
49 writel(readl(KW_REG_UNDOC_0x1478) & ~(1 << 7), KW_REG_UNDOC_0x1478);
50 for (i = 0; i < BUFLEN; i++) {
51 inbuf[i] = readl(KW_REG_UNDOC_0x1470);
52 }
53 md5((u8 *) inbuf, (BUFLEN * sizeof(u32)), outbuf);
54 return outbuf[outbuf[7] % 0x0f];
55}
56
57/*
58 * Window Size
59 * Used with the Base register to set the address window size and location.
60 * Must be programmed from LSB to MSB as sequence of ones followed by
61 * sequence of zeros. The number of ones specifies the size of the window in
62 * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
63 * NOTE: A value of 0x0 specifies 64-KByte size.
64 */
Prafulla Wadaskar78eabb92009-06-29 20:55:54 +053065unsigned int kw_winctrl_calcsize(unsigned int sizeval)
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020066{
67 int i;
68 unsigned int j = 0;
69 u32 val = sizeval >> 1;
70
Prafulla Wadaskarf1060562010-08-26 14:43:55 +053071 for (i = 0; val >= 0x10000; i++) {
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020072 j |= (1 << i);
73 val = val >> 1;
74 }
75 return (0x0000ffff & j);
76}
77
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020078/*
79 * kw_config_adr_windows - Configure address Windows
80 *
81 * There are 8 address windows supported by Kirkwood Soc to addess different
82 * devices. Each window can be configured for size, BAR and remap addr
83 * Below configuration is standard for most of the cases
84 *
85 * If remap function not used, remap_lo must be set as base
86 *
87 * Reference Documentation:
88 * Mbus-L to Mbus Bridge Registers Configuration.
89 * (Sec 25.1 and 25.3 of Datasheet)
90 */
91int kw_config_adr_windows(void)
92{
93 struct kwwin_registers *winregs =
94 (struct kwwin_registers *)KW_CPU_WIN_BASE;
95
96 /* Window 0: PCIE MEM address space */
97 writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 256, KWCPU_TARGET_PCIE,
98 KWCPU_ATTR_PCIE_MEM, KWCPU_WIN_ENABLE), &winregs[0].ctrl);
99
100 writel(KW_DEFADR_PCI_MEM, &winregs[0].base);
101 writel(KW_DEFADR_PCI_MEM, &winregs[0].remap_lo);
102 writel(0x0, &winregs[0].remap_hi);
103
104 /* Window 1: PCIE IO address space */
105 writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_PCIE,
106 KWCPU_ATTR_PCIE_IO, KWCPU_WIN_ENABLE), &winregs[1].ctrl);
107 writel(KW_DEFADR_PCI_IO, &winregs[1].base);
108 writel(KW_DEFADR_PCI_IO_REMAP, &winregs[1].remap_lo);
109 writel(0x0, &winregs[1].remap_hi);
110
111 /* Window 2: NAND Flash address space */
112 writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
113 KWCPU_ATTR_NANDFLASH, KWCPU_WIN_ENABLE), &winregs[2].ctrl);
114 writel(KW_DEFADR_NANDF, &winregs[2].base);
115 writel(KW_DEFADR_NANDF, &winregs[2].remap_lo);
116 writel(0x0, &winregs[2].remap_hi);
117
118 /* Window 3: SPI Flash address space */
119 writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
120 KWCPU_ATTR_SPIFLASH, KWCPU_WIN_ENABLE), &winregs[3].ctrl);
121 writel(KW_DEFADR_SPIF, &winregs[3].base);
122 writel(KW_DEFADR_SPIF, &winregs[3].remap_lo);
123 writel(0x0, &winregs[3].remap_hi);
124
125 /* Window 4: BOOT Memory address space */
126 writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
127 KWCPU_ATTR_BOOTROM, KWCPU_WIN_ENABLE), &winregs[4].ctrl);
128 writel(KW_DEFADR_BOOTROM, &winregs[4].base);
129
130 /* Window 5: Security SRAM address space */
131 writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_SASRAM,
132 KWCPU_ATTR_SASRAM, KWCPU_WIN_ENABLE), &winregs[5].ctrl);
133 writel(KW_DEFADR_SASRAM, &winregs[5].base);
134
135 /* Window 6-7: Disabled */
136 writel(KWCPU_WIN_DISABLE, &winregs[6].ctrl);
137 writel(KWCPU_WIN_DISABLE, &winregs[7].ctrl);
138
139 return 0;
140}
141
142/*
143 * kw_config_gpio - GPIO configuration
144 */
145void kw_config_gpio(u32 gpp0_oe_val, u32 gpp1_oe_val, u32 gpp0_oe, u32 gpp1_oe)
146{
147 struct kwgpio_registers *gpio0reg =
148 (struct kwgpio_registers *)KW_GPIO0_BASE;
149 struct kwgpio_registers *gpio1reg =
150 (struct kwgpio_registers *)KW_GPIO1_BASE;
151
152 /* Init GPIOS to default values as per board requirement */
153 writel(gpp0_oe_val, &gpio0reg->dout);
154 writel(gpp1_oe_val, &gpio1reg->dout);
155 writel(gpp0_oe, &gpio0reg->oe);
156 writel(gpp1_oe, &gpio1reg->oe);
157}
158
159/*
160 * kw_config_mpp - Multi-Purpose Pins Functionality configuration
161 *
162 * Each MPP can be configured to different functionality through
163 * MPP control register, ref (sec 6.1 of kirkwood h/w specification)
164 *
165 * There are maximum 64 Multi-Pourpose Pins on Kirkwood
166 * Each MPP functionality can be configuration by a 4bit value
167 * of MPP control reg, the value and associated functionality depends
168 * upon used SoC varient
169 */
170int kw_config_mpp(u32 mpp0_7, u32 mpp8_15, u32 mpp16_23, u32 mpp24_31,
171 u32 mpp32_39, u32 mpp40_47, u32 mpp48_55)
172{
173 u32 *mppreg = (u32 *) KW_MPP_BASE;
174
175 /* program mpp registers */
176 writel(mpp0_7, &mppreg[0]);
177 writel(mpp8_15, &mppreg[1]);
178 writel(mpp16_23, &mppreg[2]);
179 writel(mpp24_31, &mppreg[3]);
180 writel(mpp32_39, &mppreg[4]);
181 writel(mpp40_47, &mppreg[5]);
182 writel(mpp48_55, &mppreg[6]);
183 return 0;
184}
185
Prafulla Wadaskar49d2cb42009-08-20 20:59:28 +0530186/*
187 * SYSRSTn Duration Counter Support
188 *
189 * Kirkwood SoC implements a hardware-based SYSRSTn duration counter.
190 * When SYSRSTn is asserted low, a SYSRSTn duration counter is running.
191 * The SYSRSTn duration counter is useful for implementing a manufacturer
192 * or factory reset. Upon a long reset assertion that is greater than a
193 * pre-configured environment variable value for sysrstdelay,
194 * The counter value is stored in the SYSRSTn Length Counter Register
195 * The counter is based on the 25-MHz reference clock (40ns)
196 * It is a 29-bit counter, yielding a maximum counting duration of
197 * 2^29/25 MHz (21.4 seconds). When the counter reach its maximum value,
198 * it remains at this value until counter reset is triggered by setting
199 * bit 31 of KW_REG_SYSRST_CNT
200 */
201static void kw_sysrst_action(void)
202{
203 int ret;
204 char *s = getenv("sysrstcmd");
205
206 if (!s) {
207 debug("Error.. %s failed, check sysrstcmd\n",
208 __FUNCTION__);
209 return;
210 }
211
212 debug("Starting %s process...\n", __FUNCTION__);
Simon Glass53071532012-02-14 19:59:21 +0000213 ret = run_command(s, 0);
Thomas Betker73671da2014-06-05 20:07:56 +0200214 if (ret != 0)
Prafulla Wadaskar49d2cb42009-08-20 20:59:28 +0530215 debug("Error.. %s failed\n", __FUNCTION__);
216 else
217 debug("%s process finished\n", __FUNCTION__);
218}
219
220static void kw_sysrst_check(void)
221{
222 u32 sysrst_cnt, sysrst_dly;
223 char *s;
224
225 /*
226 * no action if sysrstdelay environment variable is not defined
227 */
228 s = getenv("sysrstdelay");
229 if (s == NULL)
230 return;
231
232 /* read sysrstdelay value */
233 sysrst_dly = (u32) simple_strtoul(s, NULL, 10);
234
235 /* read SysRst Length counter register (bits 28:0) */
236 sysrst_cnt = (0x1fffffff & readl(KW_REG_SYSRST_CNT));
237 debug("H/w Rst hold time: %d.%d secs\n",
238 sysrst_cnt / SYSRST_CNT_1SEC_VAL,
239 sysrst_cnt % SYSRST_CNT_1SEC_VAL);
240
241 /* clear the counter for next valid read*/
242 writel(1 << 31, KW_REG_SYSRST_CNT);
243
244 /*
245 * sysrst_action:
246 * if H/w Reset key is pressed and hold for time
247 * more than sysrst_dly in seconds
248 */
249 if (sysrst_cnt >= SYSRST_CNT_1SEC_VAL * sysrst_dly)
250 kw_sysrst_action();
251}
252
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +0200253#if defined(CONFIG_DISPLAY_CPUINFO)
254int print_cpuinfo(void)
255{
Prafulla Wadaskarc0cd0202010-09-20 17:19:42 +0530256 char *rev;
257 u16 devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff;
258 u8 revid = readl(KW_REG_PCIE_REVID) & 0xff;
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +0200259
Prafulla Wadaskarc0cd0202010-09-20 17:19:42 +0530260 if ((readl(KW_REG_DEVICE_ID) & 0x03) > 2) {
261 printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n", __FUNCTION__, devid);
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +0200262 return -1;
263 }
Prafulla Wadaskarc0cd0202010-09-20 17:19:42 +0530264
265 switch (revid) {
266 case 0:
267 rev = "Z0";
268 break;
269 case 2:
270 rev = "A0";
271 break;
272 case 3:
273 rev = "A1";
274 break;
275 default:
276 rev = "??";
277 break;
278 }
279
280 printf("SoC: Kirkwood 88F%04x_%s\n", devid, rev);
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +0200281 return 0;
282}
283#endif /* CONFIG_DISPLAY_CPUINFO */
284
285#ifdef CONFIG_ARCH_CPU_INIT
286int arch_cpu_init(void)
287{
288 u32 reg;
289 struct kwcpu_registers *cpureg =
290 (struct kwcpu_registers *)KW_CPU_REG_BASE;
291
292 /* Linux expects` the internal registers to be at 0xf1000000 */
293 writel(KW_REGS_PHY_BASE, KW_OFFSET_REG);
294
295 /* Enable and invalidate L2 cache in write through mode */
296 writel(readl(&cpureg->l2_cfg) | 0x18, &cpureg->l2_cfg);
297 invalidate_l2_cache();
298
299 kw_config_adr_windows();
300
301#ifdef CONFIG_KIRKWOOD_RGMII_PAD_1V8
302 /*
303 * Configures the I/O voltage of the pads connected to Egigabit
304 * Ethernet interface to 1.8V
Robert P. J. Day1bce2ae2013-09-16 07:15:45 -0400305 * By default it is set to 3.3V
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +0200306 */
307 reg = readl(KW_REG_MPP_OUT_DRV_REG);
308 reg |= (1 << 7);
309 writel(reg, KW_REG_MPP_OUT_DRV_REG);
310#endif
311#ifdef CONFIG_KIRKWOOD_EGIGA_INIT
312 /*
313 * Set egiga port0/1 in normal functional mode
314 * This is required becasue on kirkwood by default ports are in reset mode
315 * OS egiga driver may not have provision to set them in normal mode
316 * and if u-boot is build without network support, network may fail at OS level
317 */
318 reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(0));
319 reg &= ~(1 << 4); /* Clear PortReset Bit */
320 writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(0)));
321 reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(1));
322 reg &= ~(1 << 4); /* Clear PortReset Bit */
323 writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(1)));
324#endif
325#ifdef CONFIG_KIRKWOOD_PCIE_INIT
326 /*
327 * Enable PCI Express Port0
328 */
329 reg = readl(&cpureg->ctrl_stat);
330 reg |= (1 << 0); /* Set PEX0En Bit */
331 writel(reg, &cpureg->ctrl_stat);
332#endif
333 return 0;
334}
335#endif /* CONFIG_ARCH_CPU_INIT */
336
337/*
338 * SOC specific misc init
339 */
340#if defined(CONFIG_ARCH_MISC_INIT)
341int arch_misc_init(void)
342{
343 volatile u32 temp;
344
345 /*CPU streaming & write allocate */
346 temp = readfr_extra_feature_reg();
347 temp &= ~(1 << 28); /* disable wr alloc */
348 writefr_extra_feature_reg(temp);
349
350 temp = readfr_extra_feature_reg();
351 temp &= ~(1 << 29); /* streaming disabled */
352 writefr_extra_feature_reg(temp);
353
354 /* L2Cache settings */
355 temp = readfr_extra_feature_reg();
356 /* Disable L2C pre fetch - Set bit 24 */
357 temp |= (1 << 24);
358 /* enable L2C - Set bit 22 */
359 temp |= (1 << 22);
360 writefr_extra_feature_reg(temp);
361
362 icache_enable();
363 /* Change reset vector to address 0x0 */
364 temp = get_cr();
365 set_cr(temp & ~CR_V);
366
Prafulla Wadaskar49d2cb42009-08-20 20:59:28 +0530367 /* checks and execute resset to factory event */
368 kw_sysrst_check();
369
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +0200370 return 0;
371}
372#endif /* CONFIG_ARCH_MISC_INIT */
373
Albert Aribaudd44265a2010-07-12 22:24:28 +0200374#ifdef CONFIG_MVGBE
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +0200375int cpu_eth_init(bd_t *bis)
376{
Albert Aribaudd44265a2010-07-12 22:24:28 +0200377 mvgbe_initialize(bis);
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +0200378 return 0;
379}
380#endif
DrEagle3fe3b4f2014-07-25 21:07:30 +0200381
382#ifdef CONFIG_MVEBU_MMC
383int board_mmc_init(bd_t *bis)
384{
385 mvebu_mmc_init(bis);
386 return 0;
387}
388#endif /* CONFIG_MVEBU_MMC */