| Paweł Anikiel | 6129827 | 2022-06-17 12:47:20 +0200 | [diff] [blame] | 1 | CONFIG_ARM=y |
| Philip Oberfichtner | 1116888 | 2022-08-17 15:07:12 +0200 | [diff] [blame] | 2 | CONFIG_SYS_L2_PL310=y |
| Paweł Anikiel | 6129827 | 2022-06-17 12:47:20 +0200 | [diff] [blame] | 3 | CONFIG_ARCH_SOCFPGA=y |
| Paweł Anikiel | 6129827 | 2022-06-17 12:47:20 +0200 | [diff] [blame] | 4 | CONFIG_ENV_SIZE=0x10000 |
| 5 | CONFIG_ENV_OFFSET=0x4400 |
| Tom Rini | d98a6a9 | 2022-07-04 08:15:34 -0400 | [diff] [blame] | 6 | CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_chameleonv3_480_2" |
| 7 | CONFIG_SPL_TEXT_BASE=0xFFE00000 |
| 8 | CONFIG_SPL_DRIVERS_MISC=y |
| Michał Barnaś | adb6420 | 2024-03-19 18:18:14 +0000 | [diff] [blame] | 9 | CONFIG_SOCFPGA_ARRIA10_ALWAYS_REPROGRAM=y |
| Tom Rini | 18e791c | 2024-04-22 17:24:09 -0600 | [diff] [blame] | 10 | CONFIG_TARGET_SOCFPGA_CHAMELEONV3=y |
| Tom Rini | d98a6a9 | 2022-07-04 08:15:34 -0400 | [diff] [blame] | 11 | CONFIG_SPL_FS_FAT=y |
| Tom Rini | d98a6a9 | 2022-07-04 08:15:34 -0400 | [diff] [blame] | 12 | CONFIG_FIT=y |
| 13 | CONFIG_SPL_FIT=y |
| Tom Rini | 42fb448 | 2024-01-03 09:26:16 -0500 | [diff] [blame] | 14 | CONFIG_SYS_BOOTM_LEN=0x2000000 |
| Tom Rini | c358af8 | 2023-03-27 13:39:17 -0400 | [diff] [blame] | 15 | CONFIG_DISTRO_DEFAULTS=y |
| Tom Rini | d98a6a9 | 2022-07-04 08:15:34 -0400 | [diff] [blame] | 16 | CONFIG_MISC_INIT_R=y |
| Tom Rini | 2a433a5 | 2023-02-27 09:11:57 -0500 | [diff] [blame] | 17 | CONFIG_SPL_MAX_SIZE=0x40000 |
| Tom Rini | 36b661d | 2022-07-11 10:18:13 -0400 | [diff] [blame] | 18 | CONFIG_SPL_NO_BSS_LIMIT=y |
| Simon Glass | 82e26e0 | 2023-09-26 08:14:16 -0600 | [diff] [blame] | 19 | CONFIG_SPL_SYS_MALLOC=y |
| 20 | CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y |
| 21 | CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0xffe2b000 |
| 22 | CONFIG_SPL_SYS_MALLOC_SIZE=0x15000 |
| Tom Rini | d98a6a9 | 2022-07-04 08:15:34 -0400 | [diff] [blame] | 23 | CONFIG_SPL_ENV_SUPPORT=y |
| Tom Rini | 2a433a5 | 2023-02-27 09:11:57 -0500 | [diff] [blame] | 24 | CONFIG_SPL_FS_EXT4=y |
| Tom Rini | d98a6a9 | 2022-07-04 08:15:34 -0400 | [diff] [blame] | 25 | CONFIG_SPL_FPGA=y |
| Tom Rini | db04ff4 | 2024-01-10 13:46:10 -0500 | [diff] [blame] | 26 | # CONFIG_CMD_MTDPARTS is not set |
| Tom Rini | d98a6a9 | 2022-07-04 08:15:34 -0400 | [diff] [blame] | 27 | CONFIG_ENV_IS_IN_MMC=y |
| 28 | CONFIG_SYS_I2C_DW=y |
| 29 | CONFIG_MISC=y |
| 30 | CONFIG_ATSHA204A=y |
| 31 | CONFIG_FS_LOADER=y |
| 32 | CONFIG_SPL_FS_LOADER=y |
| 33 | CONFIG_MMC_DW=y |
| Paweł Anikiel | 6129827 | 2022-06-17 12:47:20 +0200 | [diff] [blame] | 34 | CONFIG_ETH_DESIGNWARE=y |
| Tom Rini | 9591b63 | 2022-12-04 09:39:03 -0500 | [diff] [blame] | 35 | CONFIG_SYS_NS16550_MEM32=y |
| Paweł Anikiel | 6129827 | 2022-06-17 12:47:20 +0200 | [diff] [blame] | 36 | CONFIG_TIMER=y |
| 37 | CONFIG_SPL_TIMER=y |
| 38 | CONFIG_DESIGNWARE_APB_TIMER=y |