Jean-Christophe PLAGNIOL-VILLARD | c8aa7df | 2008-10-31 12:26:55 +0100 | [diff] [blame] | 1 | # |
| 2 | # (C) Copyright 2008 |
| 3 | # Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | # |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | # SPDX-License-Identifier: GPL-2.0+ |
Jean-Christophe PLAGNIOL-VILLARD | c8aa7df | 2008-10-31 12:26:55 +0100 | [diff] [blame] | 6 | # |
| 7 | |
Masahiro Yamada | 710f1d3 | 2013-10-17 17:34:57 +0900 | [diff] [blame] | 8 | obj-y += fpga.o |
| 9 | obj-$(CONFIG_FPGA_SPARTAN2) += spartan2.o |
| 10 | obj-$(CONFIG_FPGA_SPARTAN3) += spartan3.o |
| 11 | obj-$(CONFIG_FPGA_VIRTEX2) += virtex2.o |
| 12 | obj-$(CONFIG_FPGA_ZYNQPL) += zynqpl.o |
| 13 | obj-$(CONFIG_FPGA_XILINX) += xilinx.o |
| 14 | obj-$(CONFIG_FPGA_LATTICE) += ivm_core.o lattice.o |
Jean-Christophe PLAGNIOL-VILLARD | c8aa7df | 2008-10-31 12:26:55 +0100 | [diff] [blame] | 15 | ifdef CONFIG_FPGA_ALTERA |
Masahiro Yamada | 710f1d3 | 2013-10-17 17:34:57 +0900 | [diff] [blame] | 16 | obj-y += altera.o |
| 17 | obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o |
| 18 | obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o |
| 19 | obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o |
Jean-Christophe PLAGNIOL-VILLARD | c8aa7df | 2008-10-31 12:26:55 +0100 | [diff] [blame] | 20 | endif |