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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
wdenka562e1b2005-01-09 18:21:42 +00002/*
3 * Configuation settings for the Sentec Cobra Board.
4 *
5 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
wdenka562e1b2005-01-09 18:21:42 +00006 */
7
8/* ---
Bin Menga1875592016-02-05 19:30:11 -08009 * Version: U-Boot 1.0.0 - initial release for Sentec COBRA5272 board
wdenka562e1b2005-01-09 18:21:42 +000010 * Date: 2004-03-29
11 * Author: Florian Schlote
12 *
13 * For a description of configuration options please refer also to the
14 * general u-boot-1.x.x/README file
15 * ---
16 */
17
18/* ---
19 * board/config.h - configuration options, board specific
20 * ---
21 */
22
23#ifndef _CONFIG_COBRA5272_H
24#define _CONFIG_COBRA5272_H
25
26/* ---
wdenka562e1b2005-01-09 18:21:42 +000027 * Defines processor clock - important for correct timings concerning serial
28 * interface etc.
wdenka562e1b2005-01-09 18:21:42 +000029 * ---
30 */
31
Tom Rini65cc0e22022-11-16 13:10:41 -050032#define CFG_SYS_CLK 66000000
Tom Riniaa6e94d2022-11-16 13:10:37 -050033#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
wdenka562e1b2005-01-09 18:21:42 +000034
wdenka562e1b2005-01-09 18:21:42 +000035/* ---
36 * Define baudrate for UART1 (console output, tftp, ...)
37 * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
Tom Rini65cc0e22022-11-16 13:10:41 -050038 * CFG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command
wdenka562e1b2005-01-09 18:21:42 +000039 * interface
40 * ---
41 */
42
Tom Rini65cc0e22022-11-16 13:10:41 -050043#define CFG_SYS_UART_PORT (0)
wdenka562e1b2005-01-09 18:21:42 +000044
45/* ---
wdenka562e1b2005-01-09 18:21:42 +000046 * CONFIG_MONITOR_IS_IN_RAM defines if u-boot is started from a different
47 * bootloader residing in flash ('chainloading'); if you want to use
48 * chainloading or want to compile a u-boot binary that can be loaded into
49 * RAM via BDM set
Wolfgang Denk53677ef2008-05-20 16:00:29 +020050 * "#if 0" to "#if 1"
wdenka562e1b2005-01-09 18:21:42 +000051 * You will need a first stage bootloader then, e. g. colilo or a working BDM
52 * cable (Background Debug Mode)
53 *
54 * Setting #if 0: u-boot will start from flash and relocate itself to RAM
55 *
Simon Glass98463902022-10-20 18:22:39 -060056 * Please do not forget to modify the setting of CONFIG_TEXT_BASE
wdenka562e1b2005-01-09 18:21:42 +000057 * in board/cobra5272/config.mk accordingly (#if 0: 0xffe00000; #if 1: 0x20000)
58 *
59 * ---
60 */
61
62#if 0
63#define CONFIG_MONITOR_IS_IN_RAM /* monitor is started from a preloader */
64#endif
65
66/* ---
67 * Configuration for environment
68 * Environment is embedded in u-boot in the second sector of the flash
69 * ---
70 */
71
angelo@sysam.it5296cb12015-03-29 22:54:16 +020072#define LDS_BOARD_TEXT \
Simon Glass0649cd02017-08-03 12:21:49 -060073 . = DEFINED(env_offset) ? env_offset : .; \
74 env/embedded.o(.text);
Jon Loeliger37e4f242007-07-04 22:31:56 -050075
wdenka562e1b2005-01-09 18:21:42 +000076/*
77 *-----------------------------------------------------------------------------
78 * Define user parameters that have to be customized most likely
79 *-----------------------------------------------------------------------------
80 */
81
82/*AUTOBOOT settings - booting images automatically by u-boot after power on*/
83
wdenka562e1b2005-01-09 18:21:42 +000084/* The following settings will be contained in the environment block ; if you
85want to use a neutral environment all those settings can be manually set in
86u-boot: 'set' command */
87
88#if 0
89
wdenka562e1b2005-01-09 18:21:42 +000090enter a valid image address in flash */
91
wdenka562e1b2005-01-09 18:21:42 +000092/* User network settings */
93
wdenka562e1b2005-01-09 18:21:42 +000094#define CONFIG_IPADDR 192.168.100.2 /* default board IP address */
95#define CONFIG_SERVERIP 192.168.100.1 /* default tftp server IP address */
96
97#endif
98
wdenka562e1b2005-01-09 18:21:42 +000099/*---*/
100
wdenka562e1b2005-01-09 18:21:42 +0000101/*
102 *-----------------------------------------------------------------------------
103 * End of user parameters to be customized
104 *-----------------------------------------------------------------------------
105 */
106
107/* ---
108 * Defines memory range for test
109 * ---
110 */
111
wdenka562e1b2005-01-09 18:21:42 +0000112/* ---
113 * Low Level Configuration Settings
114 * (address mappings, register initial values, etc.)
115 * You should know what you are doing if you make changes here.
116 * ---
117 */
118
119/* ---
120 * Base register address
121 * ---
122 */
123
Tom Rini65cc0e22022-11-16 13:10:41 -0500124#define CFG_SYS_MBAR 0x10000000 /* Register Base Addrs */
wdenka562e1b2005-01-09 18:21:42 +0000125
126/* ---
127 * System Conf. Reg. & System Protection Reg.
128 * ---
129 */
130
Tom Rini65cc0e22022-11-16 13:10:41 -0500131#define CFG_SYS_SCR 0x0003
132#define CFG_SYS_SPR 0xffff
wdenka562e1b2005-01-09 18:21:42 +0000133
wdenka562e1b2005-01-09 18:21:42 +0000134/*-----------------------------------------------------------------------
135 * Definitions for initial stack pointer and data area (in internal SRAM)
136 */
Tom Rini65cc0e22022-11-16 13:10:41 -0500137#define CFG_SYS_INIT_RAM_ADDR 0x20000000
138#define CFG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
wdenka562e1b2005-01-09 18:21:42 +0000139
140/*-----------------------------------------------------------------------
141 * Start addresses for the final memory configuration
142 * (Set up by the startup code)
Tom Riniaa6e94d2022-11-16 13:10:37 -0500143 * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
wdenka562e1b2005-01-09 18:21:42 +0000144 */
Tom Riniaa6e94d2022-11-16 13:10:37 -0500145#define CFG_SYS_SDRAM_BASE 0x00000000
wdenka562e1b2005-01-09 18:21:42 +0000146
147/*
148 *-------------------------------------------------------------------------
149 * RAM SIZE (is defined above)
150 *-----------------------------------------------------------------------
151 */
152
Tom Riniaa6e94d2022-11-16 13:10:37 -0500153/* #define CFG_SYS_SDRAM_SIZE 16 */
wdenka562e1b2005-01-09 18:21:42 +0000154
155/*
156 *-----------------------------------------------------------------------
157 */
158
Tom Rini65cc0e22022-11-16 13:10:41 -0500159#define CFG_SYS_FLASH_BASE 0xffe00000
wdenka562e1b2005-01-09 18:21:42 +0000160
wdenka562e1b2005-01-09 18:21:42 +0000161/*
162 * For booting Linux, the board info and command line data
163 * have to be in the first 8 MB of memory, since this is
164 * the maximum mapped by the Linux kernel during initialization ??
165 */
Tom Rini65cc0e22022-11-16 13:10:41 -0500166#define CFG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenka562e1b2005-01-09 18:21:42 +0000167
168/*-----------------------------------------------------------------------
wdenka562e1b2005-01-09 18:21:42 +0000169 * Cache Configuration
170 */
wdenka562e1b2005-01-09 18:21:42 +0000171
Tom Rini65cc0e22022-11-16 13:10:41 -0500172#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
173 CFG_SYS_INIT_RAM_SIZE - 8)
174#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
175 CFG_SYS_INIT_RAM_SIZE - 4)
176#define CFG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
177#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
Tom Riniaa6e94d2022-11-16 13:10:37 -0500178 CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600179 CF_ACR_EN | CF_ACR_SM_ALL)
Tom Rini65cc0e22022-11-16 13:10:41 -0500180#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600181 CF_CACR_DISD | CF_CACR_INVI | \
182 CF_CACR_CEIB | CF_CACR_DCM | \
183 CF_CACR_EUSP)
184
wdenka562e1b2005-01-09 18:21:42 +0000185/*-----------------------------------------------------------------------
wdenka562e1b2005-01-09 18:21:42 +0000186 * LED config
187 */
188#define LED_STAT_0 0xffff /*all LEDs off*/
189#define LED_STAT_1 0xfffe
190#define LED_STAT_2 0xfffd
191#define LED_STAT_3 0xfffb
192#define LED_STAT_4 0xfff7
193#define LED_STAT_5 0xffef
194#define LED_STAT_6 0xffdf
195#define LED_STAT_7 0xff00 /*all LEDs on*/
196
197/*-----------------------------------------------------------------------
198 * Port configuration (GPIO)
199 */
Tom Rini65cc0e22022-11-16 13:10:41 -0500200#define CFG_SYS_PACNT 0x00000000 /* PortA control reg.: All pins are external
wdenka562e1b2005-01-09 18:21:42 +0000201GPIO*/
Tom Rini65cc0e22022-11-16 13:10:41 -0500202#define CFG_SYS_PADDR 0x00FF /* PortA direction reg.: PA7 to PA0 are outputs
wdenka562e1b2005-01-09 18:21:42 +0000203(1^=output, 0^=input) */
Tom Rini65cc0e22022-11-16 13:10:41 -0500204#define CFG_SYS_PADAT LED_STAT_0 /* PortA value reg.: Turn all LED off */
205#define CFG_SYS_PBCNT 0x55554155 /* PortB control reg.: Ethernet/UART
wdenka562e1b2005-01-09 18:21:42 +0000206configuration */
Tom Rini65cc0e22022-11-16 13:10:41 -0500207#define CFG_SYS_PBDDR 0x0000 /* PortB direction: All pins configured as inputs */
208#define CFG_SYS_PBDAT 0x0000 /* PortB value reg. */
209#define CFG_SYS_PDCNT 0x00000000 /* PortD control reg. */
wdenka562e1b2005-01-09 18:21:42 +0000210
211#endif /* _CONFIG_COBRA5272_H */