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wdenk42d1f032003-10-15 23:53:47 +00001/*
wdenk97d80fc2004-06-09 00:34:46 +00002 * Freescale Three Speed Ethernet Controller driver
wdenk42d1f032003-10-15 23:53:47 +00003 *
4 * This software may be used and distributed according to the
5 * terms of the GNU Public License, Version 2, incorporated
6 * herein by reference.
7 *
Andy Fleming81f481c2007-04-23 02:24:28 -05008 * Copyright 2004, 2007 Freescale Semiconductor, Inc.
wdenk42d1f032003-10-15 23:53:47 +00009 * (C) Copyright 2003, Motorola, Inc.
wdenk42d1f032003-10-15 23:53:47 +000010 * author Andy Fleming
11 *
12 */
13
14#include <config.h>
wdenk42d1f032003-10-15 23:53:47 +000015#include <common.h>
16#include <malloc.h>
17#include <net.h>
18#include <command.h>
19
20#if defined(CONFIG_TSEC_ENET)
21#include "tsec.h"
Marian Balakowicz63ff0042005-10-28 22:30:33 +020022#include "miiphy.h"
wdenk42d1f032003-10-15 23:53:47 +000023
Wolfgang Denkd87080b2006-03-31 18:32:53 +020024DECLARE_GLOBAL_DATA_PTR;
25
Marian Balakowicz63ff0042005-10-28 22:30:33 +020026#define TX_BUF_CNT 2
wdenk42d1f032003-10-15 23:53:47 +000027
Jon Loeliger89875e92006-10-10 17:03:43 -050028static uint rxIdx; /* index of the current RX buffer */
29static uint txIdx; /* index of the current TX buffer */
wdenk42d1f032003-10-15 23:53:47 +000030
31typedef volatile struct rtxbd {
32 txbd8_t txbd[TX_BUF_CNT];
33 rxbd8_t rxbd[PKTBUFSRX];
Jon Loeliger89875e92006-10-10 17:03:43 -050034} RTXBD;
wdenk42d1f032003-10-15 23:53:47 +000035
wdenk97d80fc2004-06-09 00:34:46 +000036struct tsec_info_struct {
37 unsigned int phyaddr;
Jon Loeligerd9b94f22005-07-25 14:05:07 -050038 u32 flags;
wdenk97d80fc2004-06-09 00:34:46 +000039 unsigned int phyregidx;
40};
41
wdenk97d80fc2004-06-09 00:34:46 +000042/* The tsec_info structure contains 3 values which the
43 * driver uses to determine how to operate a given ethernet
Andy Fleming09f3e092006-09-13 10:34:18 -050044 * device. The information needed is:
wdenk97d80fc2004-06-09 00:34:46 +000045 * phyaddr - The address of the PHY which is attached to
wdenk9d46ea42005-03-14 23:56:42 +000046 * the given device.
wdenk97d80fc2004-06-09 00:34:46 +000047 *
Jon Loeligerd9b94f22005-07-25 14:05:07 -050048 * flags - This variable indicates whether the device
49 * supports gigabit speed ethernet, and whether it should be
50 * in reduced mode.
wdenk97d80fc2004-06-09 00:34:46 +000051 *
52 * phyregidx - This variable specifies which ethernet device
wdenk9d46ea42005-03-14 23:56:42 +000053 * controls the MII Management registers which are connected
Andy Fleming09f3e092006-09-13 10:34:18 -050054 * to the PHY. For now, only TSEC1 (index 0) has
wdenk9d46ea42005-03-14 23:56:42 +000055 * access to the PHYs, so all of the entries have "0".
wdenk97d80fc2004-06-09 00:34:46 +000056 *
57 * The values specified in the table are taken from the board's
58 * config file in include/configs/. When implementing a new
59 * board with ethernet capability, it is necessary to define:
Andy Fleming09f3e092006-09-13 10:34:18 -050060 * TSECn_PHY_ADDR
61 * TSECn_PHYIDX
wdenk97d80fc2004-06-09 00:34:46 +000062 *
Andy Fleming09f3e092006-09-13 10:34:18 -050063 * for n = 1,2,3, etc. And for FEC:
wdenk97d80fc2004-06-09 00:34:46 +000064 * FEC_PHY_ADDR
65 * FEC_PHYIDX
66 */
67static struct tsec_info_struct tsec_info[] = {
Eran Libertyf046ccd2005-07-28 10:08:46 -050068#if defined(CONFIG_MPC85XX_TSEC1) || defined(CONFIG_MPC83XX_TSEC1)
Andy Fleming81f481c2007-04-23 02:24:28 -050069#if defined(CONFIG_MPC8544DS)
Wolfgang Denk2f152782007-05-05 18:23:11 +020070 {TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX},
Andy Fleming81f481c2007-04-23 02:24:28 -050071#else
Jon Loeligerd9b94f22005-07-25 14:05:07 -050072 {TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX},
Andy Fleming81f481c2007-04-23 02:24:28 -050073#endif
Jon Loeligerdebb7352006-04-26 17:58:56 -050074#elif defined(CONFIG_MPC86XX_TSEC1)
75 {TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX},
wdenk9d46ea42005-03-14 23:56:42 +000076#else
Jon Loeliger89875e92006-10-10 17:03:43 -050077 {0, 0, 0},
wdenk97d80fc2004-06-09 00:34:46 +000078#endif
Eran Libertyf046ccd2005-07-28 10:08:46 -050079#if defined(CONFIG_MPC85XX_TSEC2) || defined(CONFIG_MPC83XX_TSEC2)
Jon Loeligerd9b94f22005-07-25 14:05:07 -050080 {TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX},
Jon Loeligerdebb7352006-04-26 17:58:56 -050081#elif defined(CONFIG_MPC86XX_TSEC2)
Jon Loeliger89875e92006-10-10 17:03:43 -050082 {TSEC2_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC2_PHYIDX},
wdenk9d46ea42005-03-14 23:56:42 +000083#else
Jon Loeliger89875e92006-10-10 17:03:43 -050084 {0, 0, 0},
wdenk97d80fc2004-06-09 00:34:46 +000085#endif
86#ifdef CONFIG_MPC85XX_FEC
87 {FEC_PHY_ADDR, 0, FEC_PHYIDX},
wdenk9d46ea42005-03-14 23:56:42 +000088#else
Jon Loeligerdebb7352006-04-26 17:58:56 -050089#if defined(CONFIG_MPC85XX_TSEC3) || defined(CONFIG_MPC83XX_TSEC3) || defined(CONFIG_MPC86XX_TSEC3)
Jon Loeligerd9b94f22005-07-25 14:05:07 -050090 {TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX},
Jon Loeligerdebb7352006-04-26 17:58:56 -050091#else
Jon Loeliger89875e92006-10-10 17:03:43 -050092 {0, 0, 0},
Jon Loeligerdebb7352006-04-26 17:58:56 -050093#endif
Jon Loeliger504b5cd2006-09-19 10:02:20 -050094#if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4) || defined(CONFIG_MPC86XX_TSEC4)
Andy Fleming09f3e092006-09-13 10:34:18 -050095 {TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX},
Jon Loeligerdebb7352006-04-26 17:58:56 -050096#else
Jon Loeliger89875e92006-10-10 17:03:43 -050097 {0, 0, 0},
Jon Loeligerdebb7352006-04-26 17:58:56 -050098#endif
wdenk97d80fc2004-06-09 00:34:46 +000099#endif
100};
101
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500102#define MAXCONTROLLERS (4)
wdenk97d80fc2004-06-09 00:34:46 +0000103
104static int relocated = 0;
105
106static struct tsec_private *privlist[MAXCONTROLLERS];
107
wdenk42d1f032003-10-15 23:53:47 +0000108#ifdef __GNUC__
109static RTXBD rtx __attribute__ ((aligned(8)));
110#else
111#error "rtx must be 64-bit aligned"
112#endif
113
Jon Loeliger89875e92006-10-10 17:03:43 -0500114static int tsec_send(struct eth_device *dev,
115 volatile void *packet, int length);
116static int tsec_recv(struct eth_device *dev);
117static int tsec_init(struct eth_device *dev, bd_t * bd);
118static void tsec_halt(struct eth_device *dev);
119static void init_registers(volatile tsec_t * regs);
wdenk97d80fc2004-06-09 00:34:46 +0000120static void startup_tsec(struct eth_device *dev);
121static int init_phy(struct eth_device *dev);
122void write_phy_reg(struct tsec_private *priv, uint regnum, uint value);
123uint read_phy_reg(struct tsec_private *priv, uint regnum);
Jon Loeliger89875e92006-10-10 17:03:43 -0500124struct phy_info *get_phy_info(struct eth_device *dev);
wdenk97d80fc2004-06-09 00:34:46 +0000125void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd);
126static void adjust_link(struct eth_device *dev);
127static void relocate_cmds(void);
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200128static int tsec_miiphy_write(char *devname, unsigned char addr,
Jon Loeliger89875e92006-10-10 17:03:43 -0500129 unsigned char reg, unsigned short value);
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200130static int tsec_miiphy_read(char *devname, unsigned char addr,
Jon Loeliger89875e92006-10-10 17:03:43 -0500131 unsigned char reg, unsigned short *value);
wdenk7abf0c52004-04-18 21:45:42 +0000132
wdenk97d80fc2004-06-09 00:34:46 +0000133/* Initialize device structure. Returns success if PHY
134 * initialization succeeded (i.e. if it recognizes the PHY)
135 */
Jon Loeliger89875e92006-10-10 17:03:43 -0500136int tsec_initialize(bd_t * bis, int index, char *devname)
wdenk42d1f032003-10-15 23:53:47 +0000137{
Jon Loeliger89875e92006-10-10 17:03:43 -0500138 struct eth_device *dev;
wdenk42d1f032003-10-15 23:53:47 +0000139 int i;
wdenk97d80fc2004-06-09 00:34:46 +0000140 struct tsec_private *priv;
wdenk42d1f032003-10-15 23:53:47 +0000141
Jon Loeliger89875e92006-10-10 17:03:43 -0500142 dev = (struct eth_device *)malloc(sizeof *dev);
wdenk42d1f032003-10-15 23:53:47 +0000143
Jon Loeliger89875e92006-10-10 17:03:43 -0500144 if (NULL == dev)
wdenk42d1f032003-10-15 23:53:47 +0000145 return 0;
146
147 memset(dev, 0, sizeof *dev);
148
Jon Loeliger89875e92006-10-10 17:03:43 -0500149 priv = (struct tsec_private *)malloc(sizeof(*priv));
wdenk97d80fc2004-06-09 00:34:46 +0000150
Jon Loeliger89875e92006-10-10 17:03:43 -0500151 if (NULL == priv)
wdenk97d80fc2004-06-09 00:34:46 +0000152 return 0;
153
154 privlist[index] = priv;
Jon Loeliger89875e92006-10-10 17:03:43 -0500155 priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index * TSEC_SIZE);
wdenk97d80fc2004-06-09 00:34:46 +0000156 priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR +
Jon Loeliger89875e92006-10-10 17:03:43 -0500157 tsec_info[index].phyregidx *
158 TSEC_SIZE);
wdenk97d80fc2004-06-09 00:34:46 +0000159
160 priv->phyaddr = tsec_info[index].phyaddr;
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500161 priv->flags = tsec_info[index].flags;
wdenk97d80fc2004-06-09 00:34:46 +0000162
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500163 sprintf(dev->name, devname);
wdenk42d1f032003-10-15 23:53:47 +0000164 dev->iobase = 0;
Jon Loeliger89875e92006-10-10 17:03:43 -0500165 dev->priv = priv;
166 dev->init = tsec_init;
167 dev->halt = tsec_halt;
168 dev->send = tsec_send;
169 dev->recv = tsec_recv;
wdenk42d1f032003-10-15 23:53:47 +0000170
171 /* Tell u-boot to get the addr from the env */
Jon Loeliger89875e92006-10-10 17:03:43 -0500172 for (i = 0; i < 6; i++)
wdenk42d1f032003-10-15 23:53:47 +0000173 dev->enetaddr[i] = 0;
174
175 eth_register(dev);
176
wdenk97d80fc2004-06-09 00:34:46 +0000177 /* Reset the MAC */
178 priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
179 priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
wdenk7abf0c52004-04-18 21:45:42 +0000180
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200181#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) \
182 && !defined(BITBANGMII)
183 miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write);
184#endif
185
wdenk97d80fc2004-06-09 00:34:46 +0000186 /* Try to initialize PHY here, and return */
187 return init_phy(dev);
wdenk42d1f032003-10-15 23:53:47 +0000188}
189
wdenk42d1f032003-10-15 23:53:47 +0000190/* Initializes data structures and registers for the controller,
wdenk9d46ea42005-03-14 23:56:42 +0000191 * and brings the interface up. Returns the link status, meaning
wdenk97d80fc2004-06-09 00:34:46 +0000192 * that it returns success if the link is up, failure otherwise.
Jon Loeliger89875e92006-10-10 17:03:43 -0500193 * This allows u-boot to find the first active controller.
194 */
195int tsec_init(struct eth_device *dev, bd_t * bd)
wdenk42d1f032003-10-15 23:53:47 +0000196{
wdenk42d1f032003-10-15 23:53:47 +0000197 uint tempval;
198 char tmpbuf[MAC_ADDR_LEN];
199 int i;
wdenk97d80fc2004-06-09 00:34:46 +0000200 struct tsec_private *priv = (struct tsec_private *)dev->priv;
201 volatile tsec_t *regs = priv->regs;
wdenk42d1f032003-10-15 23:53:47 +0000202
203 /* Make sure the controller is stopped */
204 tsec_halt(dev);
205
wdenk97d80fc2004-06-09 00:34:46 +0000206 /* Init MACCFG2. Defaults to GMII */
wdenk42d1f032003-10-15 23:53:47 +0000207 regs->maccfg2 = MACCFG2_INIT_SETTINGS;
208
209 /* Init ECNTRL */
210 regs->ecntrl = ECNTRL_INIT_SETTINGS;
211
212 /* Copy the station address into the address registers.
213 * Backwards, because little endian MACS are dumb */
Jon Loeliger89875e92006-10-10 17:03:43 -0500214 for (i = 0; i < MAC_ADDR_LEN; i++) {
wdenk97d80fc2004-06-09 00:34:46 +0000215 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
wdenk42d1f032003-10-15 23:53:47 +0000216 }
Jon Loeliger89875e92006-10-10 17:03:43 -0500217 regs->macstnaddr1 = *((uint *) (tmpbuf));
wdenk42d1f032003-10-15 23:53:47 +0000218
Jon Loeliger89875e92006-10-10 17:03:43 -0500219 tempval = *((uint *) (tmpbuf + 4));
wdenk42d1f032003-10-15 23:53:47 +0000220
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200221 regs->macstnaddr2 = tempval;
wdenk42d1f032003-10-15 23:53:47 +0000222
wdenk42d1f032003-10-15 23:53:47 +0000223 /* reset the indices to zero */
224 rxIdx = 0;
225 txIdx = 0;
226
227 /* Clear out (for the most part) the other registers */
228 init_registers(regs);
229
230 /* Ready the device for tx/rx */
wdenk97d80fc2004-06-09 00:34:46 +0000231 startup_tsec(dev);
wdenk42d1f032003-10-15 23:53:47 +0000232
wdenk97d80fc2004-06-09 00:34:46 +0000233 /* If there's no link, fail */
234 return priv->link;
wdenk42d1f032003-10-15 23:53:47 +0000235
236}
237
wdenk97d80fc2004-06-09 00:34:46 +0000238/* Write value to the device's PHY through the registers
239 * specified in priv, modifying the register specified in regnum.
240 * It will wait for the write to be done (or for a timeout to
241 * expire) before exiting
242 */
243void write_phy_reg(struct tsec_private *priv, uint regnum, uint value)
244{
245 volatile tsec_t *regbase = priv->phyregs;
246 uint phyid = priv->phyaddr;
Jon Loeliger89875e92006-10-10 17:03:43 -0500247 int timeout = 1000000;
wdenk97d80fc2004-06-09 00:34:46 +0000248
249 regbase->miimadd = (phyid << 8) | regnum;
250 regbase->miimcon = value;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500251 asm("sync");
wdenk97d80fc2004-06-09 00:34:46 +0000252
Jon Loeliger89875e92006-10-10 17:03:43 -0500253 timeout = 1000000;
254 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
wdenk97d80fc2004-06-09 00:34:46 +0000255}
256
wdenk97d80fc2004-06-09 00:34:46 +0000257/* Reads register regnum on the device's PHY through the
wdenk9d46ea42005-03-14 23:56:42 +0000258 * registers specified in priv. It lowers and raises the read
wdenk97d80fc2004-06-09 00:34:46 +0000259 * command, and waits for the data to become valid (miimind
260 * notvalid bit cleared), and the bus to cease activity (miimind
261 * busy bit cleared), and then returns the value
262 */
263uint read_phy_reg(struct tsec_private *priv, uint regnum)
wdenk42d1f032003-10-15 23:53:47 +0000264{
265 uint value;
wdenk97d80fc2004-06-09 00:34:46 +0000266 volatile tsec_t *regbase = priv->phyregs;
267 uint phyid = priv->phyaddr;
wdenk42d1f032003-10-15 23:53:47 +0000268
wdenk97d80fc2004-06-09 00:34:46 +0000269 /* Put the address of the phy, and the register
270 * number into MIIMADD */
271 regbase->miimadd = (phyid << 8) | regnum;
wdenk42d1f032003-10-15 23:53:47 +0000272
273 /* Clear the command register, and wait */
274 regbase->miimcom = 0;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500275 asm("sync");
wdenk42d1f032003-10-15 23:53:47 +0000276
277 /* Initiate a read command, and wait */
278 regbase->miimcom = MIIM_READ_COMMAND;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500279 asm("sync");
wdenk42d1f032003-10-15 23:53:47 +0000280
281 /* Wait for the the indication that the read is done */
Jon Loeliger89875e92006-10-10 17:03:43 -0500282 while ((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ;
wdenk42d1f032003-10-15 23:53:47 +0000283
284 /* Grab the value read from the PHY */
285 value = regbase->miimstat;
286
287 return value;
288}
289
wdenk97d80fc2004-06-09 00:34:46 +0000290/* Discover which PHY is attached to the device, and configure it
291 * properly. If the PHY is not recognized, then return 0
292 * (failure). Otherwise, return 1
293 */
294static int init_phy(struct eth_device *dev)
wdenk42d1f032003-10-15 23:53:47 +0000295{
wdenk97d80fc2004-06-09 00:34:46 +0000296 struct tsec_private *priv = (struct tsec_private *)dev->priv;
297 struct phy_info *curphy;
Jon Loeliger89875e92006-10-10 17:03:43 -0500298 volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR);
wdenk42d1f032003-10-15 23:53:47 +0000299
300 /* Assign a Physical address to the TBI */
Jon Loeliger89875e92006-10-10 17:03:43 -0500301 regs->tbipa = TBIPA_VALUE;
302 regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE);
303 regs->tbipa = TBIPA_VALUE;
304 asm("sync");
wdenk3dd7f0f2005-04-04 23:43:44 +0000305
306 /* Reset MII (due to new addresses) */
307 priv->phyregs->miimcfg = MIIMCFG_RESET;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500308 asm("sync");
wdenk3dd7f0f2005-04-04 23:43:44 +0000309 priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500310 asm("sync");
Jon Loeliger89875e92006-10-10 17:03:43 -0500311 while (priv->phyregs->miimind & MIIMIND_BUSY) ;
wdenk42d1f032003-10-15 23:53:47 +0000312
Jon Loeliger89875e92006-10-10 17:03:43 -0500313 if (0 == relocated)
wdenk97d80fc2004-06-09 00:34:46 +0000314 relocate_cmds();
wdenk42d1f032003-10-15 23:53:47 +0000315
wdenk97d80fc2004-06-09 00:34:46 +0000316 /* Get the cmd structure corresponding to the attached
317 * PHY */
318 curphy = get_phy_info(dev);
wdenk42d1f032003-10-15 23:53:47 +0000319
Ben Warren4653f912006-10-26 14:38:25 -0400320 if (curphy == NULL) {
321 priv->phyinfo = NULL;
wdenk97d80fc2004-06-09 00:34:46 +0000322 printf("%s: No PHY found\n", dev->name);
wdenk42d1f032003-10-15 23:53:47 +0000323
wdenk97d80fc2004-06-09 00:34:46 +0000324 return 0;
wdenk42d1f032003-10-15 23:53:47 +0000325 }
326
wdenk97d80fc2004-06-09 00:34:46 +0000327 priv->phyinfo = curphy;
wdenk42d1f032003-10-15 23:53:47 +0000328
wdenk97d80fc2004-06-09 00:34:46 +0000329 phy_run_commands(priv, priv->phyinfo->config);
wdenk42d1f032003-10-15 23:53:47 +0000330
wdenk97d80fc2004-06-09 00:34:46 +0000331 return 1;
wdenk42d1f032003-10-15 23:53:47 +0000332}
333
Jon Loeliger89875e92006-10-10 17:03:43 -0500334/*
335 * Returns which value to write to the control register.
336 * For 10/100, the value is slightly different
337 */
338uint mii_cr_init(uint mii_reg, struct tsec_private * priv)
wdenk97d80fc2004-06-09 00:34:46 +0000339{
Jon Loeliger89875e92006-10-10 17:03:43 -0500340 if (priv->flags & TSEC_GIGABIT)
wdenk97d80fc2004-06-09 00:34:46 +0000341 return MIIM_CONTROL_INIT;
342 else
343 return MIIM_CR_INIT;
344}
345
wdenk97d80fc2004-06-09 00:34:46 +0000346/* Parse the status register for link, and then do
Jon Loeliger89875e92006-10-10 17:03:43 -0500347 * auto-negotiation
348 */
349uint mii_parse_sr(uint mii_reg, struct tsec_private * priv)
wdenk97d80fc2004-06-09 00:34:46 +0000350{
Stefan Roese5810dc32005-09-21 18:20:22 +0200351 /*
Jon Loeliger89875e92006-10-10 17:03:43 -0500352 * Wait if PHY is capable of autonegotiation and autonegotiation
353 * is not complete.
Stefan Roese5810dc32005-09-21 18:20:22 +0200354 */
355 mii_reg = read_phy_reg(priv, MIIM_STATUS);
Jon Loeliger89875e92006-10-10 17:03:43 -0500356 if ((mii_reg & PHY_BMSR_AUTN_ABLE)
357 && !(mii_reg & PHY_BMSR_AUTN_COMP)) {
Stefan Roese5810dc32005-09-21 18:20:22 +0200358 int i = 0;
wdenk97d80fc2004-06-09 00:34:46 +0000359
Jon Loeliger89875e92006-10-10 17:03:43 -0500360 puts("Waiting for PHY auto negotiation to complete");
361 while (!((mii_reg & PHY_BMSR_AUTN_COMP)
362 && (mii_reg & MIIM_STATUS_LINK))) {
Stefan Roese5810dc32005-09-21 18:20:22 +0200363 /*
364 * Timeout reached ?
365 */
366 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
Jon Loeliger89875e92006-10-10 17:03:43 -0500367 puts(" TIMEOUT !\n");
Stefan Roese5810dc32005-09-21 18:20:22 +0200368 priv->link = 0;
Jin Zhengxiong-R64188fcfb9a52006-06-27 18:12:23 +0800369 return 0;
Stefan Roese5810dc32005-09-21 18:20:22 +0200370 }
wdenk97d80fc2004-06-09 00:34:46 +0000371
Stefan Roese5810dc32005-09-21 18:20:22 +0200372 if ((i++ % 1000) == 0) {
Jon Loeliger89875e92006-10-10 17:03:43 -0500373 putc('.');
Stefan Roese5810dc32005-09-21 18:20:22 +0200374 }
Jon Loeliger89875e92006-10-10 17:03:43 -0500375 udelay(1000); /* 1 ms */
wdenk97d80fc2004-06-09 00:34:46 +0000376 mii_reg = read_phy_reg(priv, MIIM_STATUS);
Stefan Roese5810dc32005-09-21 18:20:22 +0200377 }
Jon Loeliger89875e92006-10-10 17:03:43 -0500378 puts(" done\n");
Stefan Roese5810dc32005-09-21 18:20:22 +0200379 priv->link = 1;
Jon Loeliger89875e92006-10-10 17:03:43 -0500380 udelay(500000); /* another 500 ms (results in faster booting) */
Stefan Roese5810dc32005-09-21 18:20:22 +0200381 } else {
382 priv->link = 1;
wdenk97d80fc2004-06-09 00:34:46 +0000383 }
384
385 return 0;
386}
387
David Updegraffaf1c2b82007-04-20 14:34:48 -0500388/* Generic function which updates the speed and duplex. If
389 * autonegotiation is enabled, it uses the AND of the link
390 * partner's advertised capabilities and our advertised
391 * capabilities. If autonegotiation is disabled, we use the
392 * appropriate bits in the control register.
393 *
394 * Stolen from Linux's mii.c and phy_device.c
395 */
396uint mii_parse_link(uint mii_reg, struct tsec_private *priv)
397{
398 /* We're using autonegotiation */
399 if (mii_reg & PHY_BMSR_AUTN_ABLE) {
400 uint lpa = 0;
401 uint gblpa = 0;
402
403 /* Check for gigabit capability */
404 if (mii_reg & PHY_BMSR_EXT) {
405 /* We want a list of states supported by
406 * both PHYs in the link
407 */
408 gblpa = read_phy_reg(priv, PHY_1000BTSR);
409 gblpa &= read_phy_reg(priv, PHY_1000BTCR) << 2;
410 }
411
412 /* Set the baseline so we only have to set them
413 * if they're different
414 */
415 priv->speed = 10;
416 priv->duplexity = 0;
417
418 /* Check the gigabit fields */
419 if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) {
420 priv->speed = 1000;
421
422 if (gblpa & PHY_1000BTSR_1000FD)
423 priv->duplexity = 1;
424
425 /* We're done! */
426 return 0;
427 }
428
429 lpa = read_phy_reg(priv, PHY_ANAR);
430 lpa &= read_phy_reg(priv, PHY_ANLPAR);
431
432 if (lpa & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) {
433 priv->speed = 100;
434
435 if (lpa & PHY_ANLPAR_TXFD)
436 priv->duplexity = 1;
437
438 } else if (lpa & PHY_ANLPAR_10FD)
439 priv->duplexity = 1;
440 } else {
441 uint bmcr = read_phy_reg(priv, PHY_BMCR);
442
443 priv->speed = 10;
444 priv->duplexity = 0;
445
446 if (bmcr & PHY_BMCR_DPLX)
447 priv->duplexity = 1;
448
449 if (bmcr & PHY_BMCR_1000_MBPS)
450 priv->speed = 1000;
451 else if (bmcr & PHY_BMCR_100_MBPS)
452 priv->speed = 100;
453 }
454
455 return 0;
456}
457
Paul Gortmaker91e25762007-01-16 11:38:14 -0500458/*
459 * Parse the BCM54xx status register for speed and duplex information.
460 * The linux sungem_phy has this information, but in a table format.
461 */
462uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv)
463{
464
465 switch((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT){
466
467 case 1:
468 printf("Enet starting in 10BT/HD\n");
469 priv->duplexity = 0;
470 priv->speed = 10;
471 break;
472
473 case 2:
474 printf("Enet starting in 10BT/FD\n");
475 priv->duplexity = 1;
476 priv->speed = 10;
477 break;
478
479 case 3:
480 printf("Enet starting in 100BT/HD\n");
481 priv->duplexity = 0;
482 priv->speed = 100;
483 break;
484
485 case 5:
486 printf("Enet starting in 100BT/FD\n");
487 priv->duplexity = 1;
488 priv->speed = 100;
489 break;
490
491 case 6:
492 printf("Enet starting in 1000BT/HD\n");
493 priv->duplexity = 0;
494 priv->speed = 1000;
495 break;
496
497 case 7:
498 printf("Enet starting in 1000BT/FD\n");
499 priv->duplexity = 1;
500 priv->speed = 1000;
501 break;
502
503 default:
504 printf("Auto-neg error, defaulting to 10BT/HD\n");
505 priv->duplexity = 0;
506 priv->speed = 10;
507 break;
508 }
509
510 return 0;
511
512}
wdenk97d80fc2004-06-09 00:34:46 +0000513/* Parse the 88E1011's status register for speed and duplex
Jon Loeliger89875e92006-10-10 17:03:43 -0500514 * information
515 */
516uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv)
wdenk97d80fc2004-06-09 00:34:46 +0000517{
518 uint speed;
519
Stefan Roese5810dc32005-09-21 18:20:22 +0200520 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
521
522 if (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) &&
523 (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) {
524 int i = 0;
525
Jon Loeliger89875e92006-10-10 17:03:43 -0500526 puts("Waiting for PHY realtime link");
Stefan Roese5810dc32005-09-21 18:20:22 +0200527 while (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) &&
528 (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) {
529 /*
530 * Timeout reached ?
531 */
532 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
Jon Loeliger89875e92006-10-10 17:03:43 -0500533 puts(" TIMEOUT !\n");
Stefan Roese5810dc32005-09-21 18:20:22 +0200534 priv->link = 0;
535 break;
536 }
537
538 if ((i++ % 1000) == 0) {
Jon Loeliger89875e92006-10-10 17:03:43 -0500539 putc('.');
Stefan Roese5810dc32005-09-21 18:20:22 +0200540 }
Jon Loeliger89875e92006-10-10 17:03:43 -0500541 udelay(1000); /* 1 ms */
Stefan Roese5810dc32005-09-21 18:20:22 +0200542 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
543 }
Jon Loeliger89875e92006-10-10 17:03:43 -0500544 puts(" done\n");
545 udelay(500000); /* another 500 ms (results in faster booting) */
Stefan Roese5810dc32005-09-21 18:20:22 +0200546 }
547
Jon Loeliger89875e92006-10-10 17:03:43 -0500548 if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
wdenk97d80fc2004-06-09 00:34:46 +0000549 priv->duplexity = 1;
550 else
551 priv->duplexity = 0;
552
Jon Loeliger89875e92006-10-10 17:03:43 -0500553 speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED);
wdenk97d80fc2004-06-09 00:34:46 +0000554
Jon Loeliger89875e92006-10-10 17:03:43 -0500555 switch (speed) {
556 case MIIM_88E1011_PHYSTAT_GBIT:
557 priv->speed = 1000;
558 break;
559 case MIIM_88E1011_PHYSTAT_100:
560 priv->speed = 100;
561 break;
562 default:
563 priv->speed = 10;
wdenk97d80fc2004-06-09 00:34:46 +0000564 }
565
566 return 0;
567}
568
wdenk97d80fc2004-06-09 00:34:46 +0000569/* Parse the cis8201's status register for speed and duplex
Jon Loeliger89875e92006-10-10 17:03:43 -0500570 * information
571 */
572uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv)
wdenk97d80fc2004-06-09 00:34:46 +0000573{
574 uint speed;
575
Jon Loeliger89875e92006-10-10 17:03:43 -0500576 if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX)
wdenk97d80fc2004-06-09 00:34:46 +0000577 priv->duplexity = 1;
578 else
579 priv->duplexity = 0;
580
581 speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED;
Jon Loeliger89875e92006-10-10 17:03:43 -0500582 switch (speed) {
583 case MIIM_CIS8201_AUXCONSTAT_GBIT:
584 priv->speed = 1000;
585 break;
586 case MIIM_CIS8201_AUXCONSTAT_100:
587 priv->speed = 100;
588 break;
589 default:
590 priv->speed = 10;
591 break;
wdenk97d80fc2004-06-09 00:34:46 +0000592 }
593
594 return 0;
595}
Jon Loeliger89875e92006-10-10 17:03:43 -0500596
Jon Loeligerdebb7352006-04-26 17:58:56 -0500597/* Parse the vsc8244's status register for speed and duplex
Jon Loeliger89875e92006-10-10 17:03:43 -0500598 * information
599 */
600uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500601{
Jon Loeliger89875e92006-10-10 17:03:43 -0500602 uint speed;
603
604 if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX)
605 priv->duplexity = 1;
606 else
607 priv->duplexity = 0;
608
609 speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED;
610 switch (speed) {
611 case MIIM_VSC8244_AUXCONSTAT_GBIT:
612 priv->speed = 1000;
613 break;
614 case MIIM_VSC8244_AUXCONSTAT_100:
615 priv->speed = 100;
616 break;
617 default:
618 priv->speed = 10;
619 break;
620 }
621
622 return 0;
Jon Loeligerdebb7352006-04-26 17:58:56 -0500623}
wdenk97d80fc2004-06-09 00:34:46 +0000624
wdenk97d80fc2004-06-09 00:34:46 +0000625/* Parse the DM9161's status register for speed and duplex
Jon Loeliger89875e92006-10-10 17:03:43 -0500626 * information
627 */
628uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv)
wdenk97d80fc2004-06-09 00:34:46 +0000629{
Jon Loeliger89875e92006-10-10 17:03:43 -0500630 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
wdenk97d80fc2004-06-09 00:34:46 +0000631 priv->speed = 100;
632 else
633 priv->speed = 10;
634
Jon Loeliger89875e92006-10-10 17:03:43 -0500635 if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
wdenk97d80fc2004-06-09 00:34:46 +0000636 priv->duplexity = 1;
637 else
638 priv->duplexity = 0;
639
640 return 0;
641}
642
Jon Loeliger89875e92006-10-10 17:03:43 -0500643/*
644 * Hack to write all 4 PHYs with the LED values
645 */
646uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv)
wdenk97d80fc2004-06-09 00:34:46 +0000647{
648 uint phyid;
649 volatile tsec_t *regbase = priv->phyregs;
Jon Loeliger89875e92006-10-10 17:03:43 -0500650 int timeout = 1000000;
wdenk97d80fc2004-06-09 00:34:46 +0000651
Jon Loeliger89875e92006-10-10 17:03:43 -0500652 for (phyid = 0; phyid < 4; phyid++) {
wdenk97d80fc2004-06-09 00:34:46 +0000653 regbase->miimadd = (phyid << 8) | mii_reg;
654 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500655 asm("sync");
wdenk97d80fc2004-06-09 00:34:46 +0000656
Jon Loeliger89875e92006-10-10 17:03:43 -0500657 timeout = 1000000;
658 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
wdenk97d80fc2004-06-09 00:34:46 +0000659 }
660
661 return MIIM_CIS8204_SLEDCON_INIT;
662}
663
Jon Loeliger89875e92006-10-10 17:03:43 -0500664uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv)
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500665{
666 if (priv->flags & TSEC_REDUCED)
667 return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII;
668 else
669 return MIIM_CIS8204_EPHYCON_INIT;
670}
wdenk97d80fc2004-06-09 00:34:46 +0000671
672/* Initialized required registers to appropriate values, zeroing
673 * those we don't care about (unless zero is bad, in which case,
Jon Loeliger89875e92006-10-10 17:03:43 -0500674 * choose a more appropriate value)
675 */
676static void init_registers(volatile tsec_t * regs)
wdenk42d1f032003-10-15 23:53:47 +0000677{
678 /* Clear IEVENT */
679 regs->ievent = IEVENT_INIT_CLEAR;
680
681 regs->imask = IMASK_INIT_CLEAR;
682
683 regs->hash.iaddr0 = 0;
684 regs->hash.iaddr1 = 0;
685 regs->hash.iaddr2 = 0;
686 regs->hash.iaddr3 = 0;
687 regs->hash.iaddr4 = 0;
688 regs->hash.iaddr5 = 0;
689 regs->hash.iaddr6 = 0;
690 regs->hash.iaddr7 = 0;
691
692 regs->hash.gaddr0 = 0;
693 regs->hash.gaddr1 = 0;
694 regs->hash.gaddr2 = 0;
695 regs->hash.gaddr3 = 0;
696 regs->hash.gaddr4 = 0;
697 regs->hash.gaddr5 = 0;
698 regs->hash.gaddr6 = 0;
699 regs->hash.gaddr7 = 0;
700
701 regs->rctrl = 0x00000000;
702
703 /* Init RMON mib registers */
704 memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
705
706 regs->rmon.cam1 = 0xffffffff;
707 regs->rmon.cam2 = 0xffffffff;
708
709 regs->mrblr = MRBLR_INIT_SETTINGS;
710
711 regs->minflr = MINFLR_INIT_SETTINGS;
712
713 regs->attr = ATTR_INIT_SETTINGS;
714 regs->attreli = ATTRELI_INIT_SETTINGS;
715
716}
717
wdenk97d80fc2004-06-09 00:34:46 +0000718/* Configure maccfg2 based on negotiated speed and duplex
Jon Loeliger89875e92006-10-10 17:03:43 -0500719 * reported by PHY handling code
720 */
wdenk97d80fc2004-06-09 00:34:46 +0000721static void adjust_link(struct eth_device *dev)
722{
723 struct tsec_private *priv = (struct tsec_private *)dev->priv;
724 volatile tsec_t *regs = priv->regs;
725
Jon Loeliger89875e92006-10-10 17:03:43 -0500726 if (priv->link) {
727 if (priv->duplexity != 0)
wdenk97d80fc2004-06-09 00:34:46 +0000728 regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
729 else
730 regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX);
731
Jon Loeliger89875e92006-10-10 17:03:43 -0500732 switch (priv->speed) {
733 case 1000:
734 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
735 | MACCFG2_GMII);
736 break;
737 case 100:
738 case 10:
739 regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
740 | MACCFG2_MII);
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500741
Nick Spencef484dc72006-09-07 07:39:46 -0700742 /* Set R100 bit in all modes although
743 * it is only used in RGMII mode
Jon Loeliger89875e92006-10-10 17:03:43 -0500744 */
Nick Spencef484dc72006-09-07 07:39:46 -0700745 if (priv->speed == 100)
Jon Loeliger89875e92006-10-10 17:03:43 -0500746 regs->ecntrl |= ECNTRL_R100;
747 else
748 regs->ecntrl &= ~(ECNTRL_R100);
749 break;
750 default:
751 printf("%s: Speed was bad\n", dev->name);
752 break;
wdenk97d80fc2004-06-09 00:34:46 +0000753 }
754
755 printf("Speed: %d, %s duplex\n", priv->speed,
Jon Loeliger89875e92006-10-10 17:03:43 -0500756 (priv->duplexity) ? "full" : "half");
wdenk97d80fc2004-06-09 00:34:46 +0000757
758 } else {
759 printf("%s: No link.\n", dev->name);
760 }
761}
762
wdenk97d80fc2004-06-09 00:34:46 +0000763/* Set up the buffers and their descriptors, and bring up the
Jon Loeliger89875e92006-10-10 17:03:43 -0500764 * interface
765 */
wdenk97d80fc2004-06-09 00:34:46 +0000766static void startup_tsec(struct eth_device *dev)
wdenk42d1f032003-10-15 23:53:47 +0000767{
768 int i;
wdenk97d80fc2004-06-09 00:34:46 +0000769 struct tsec_private *priv = (struct tsec_private *)dev->priv;
770 volatile tsec_t *regs = priv->regs;
wdenk42d1f032003-10-15 23:53:47 +0000771
772 /* Point to the buffer descriptors */
773 regs->tbase = (unsigned int)(&rtx.txbd[txIdx]);
774 regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
775
776 /* Initialize the Rx Buffer descriptors */
777 for (i = 0; i < PKTBUFSRX; i++) {
778 rtx.rxbd[i].status = RXBD_EMPTY;
779 rtx.rxbd[i].length = 0;
Jon Loeliger89875e92006-10-10 17:03:43 -0500780 rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i];
wdenk42d1f032003-10-15 23:53:47 +0000781 }
Jon Loeliger89875e92006-10-10 17:03:43 -0500782 rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP;
wdenk42d1f032003-10-15 23:53:47 +0000783
784 /* Initialize the TX Buffer Descriptors */
Jon Loeliger89875e92006-10-10 17:03:43 -0500785 for (i = 0; i < TX_BUF_CNT; i++) {
wdenk42d1f032003-10-15 23:53:47 +0000786 rtx.txbd[i].status = 0;
787 rtx.txbd[i].length = 0;
788 rtx.txbd[i].bufPtr = 0;
789 }
Jon Loeliger89875e92006-10-10 17:03:43 -0500790 rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP;
wdenk42d1f032003-10-15 23:53:47 +0000791
wdenk97d80fc2004-06-09 00:34:46 +0000792 /* Start up the PHY */
Ben Warren4653f912006-10-26 14:38:25 -0400793 if(priv->phyinfo)
794 phy_run_commands(priv, priv->phyinfo->startup);
David Updegraffaf1c2b82007-04-20 14:34:48 -0500795
wdenk97d80fc2004-06-09 00:34:46 +0000796 adjust_link(dev);
797
wdenk42d1f032003-10-15 23:53:47 +0000798 /* Enable Transmit and Receive */
799 regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
800
801 /* Tell the DMA it is clear to go */
802 regs->dmactrl |= DMACTRL_INIT_SETTINGS;
803 regs->tstat = TSTAT_CLEAR_THALT;
804 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
805}
806
wdenk9d46ea42005-03-14 23:56:42 +0000807/* This returns the status bits of the device. The return value
wdenk42d1f032003-10-15 23:53:47 +0000808 * is never checked, and this is what the 8260 driver did, so we
wdenk9d46ea42005-03-14 23:56:42 +0000809 * do the same. Presumably, this would be zero if there were no
Jon Loeliger89875e92006-10-10 17:03:43 -0500810 * errors
811 */
812static int tsec_send(struct eth_device *dev, volatile void *packet, int length)
wdenk42d1f032003-10-15 23:53:47 +0000813{
814 int i;
815 int result = 0;
wdenk97d80fc2004-06-09 00:34:46 +0000816 struct tsec_private *priv = (struct tsec_private *)dev->priv;
817 volatile tsec_t *regs = priv->regs;
wdenk42d1f032003-10-15 23:53:47 +0000818
819 /* Find an empty buffer descriptor */
Jon Loeliger89875e92006-10-10 17:03:43 -0500820 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
wdenk42d1f032003-10-15 23:53:47 +0000821 if (i >= TOUT_LOOP) {
Jon Loeliger89875e92006-10-10 17:03:43 -0500822 debug("%s: tsec: tx buffers full\n", dev->name);
wdenk42d1f032003-10-15 23:53:47 +0000823 return result;
824 }
825 }
826
Jon Loeliger89875e92006-10-10 17:03:43 -0500827 rtx.txbd[txIdx].bufPtr = (uint) packet;
wdenk42d1f032003-10-15 23:53:47 +0000828 rtx.txbd[txIdx].length = length;
Jon Loeliger89875e92006-10-10 17:03:43 -0500829 rtx.txbd[txIdx].status |=
830 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
wdenk42d1f032003-10-15 23:53:47 +0000831
832 /* Tell the DMA to go */
833 regs->tstat = TSTAT_CLEAR_THALT;
834
835 /* Wait for buffer to be transmitted */
Jon Loeliger89875e92006-10-10 17:03:43 -0500836 for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
wdenk42d1f032003-10-15 23:53:47 +0000837 if (i >= TOUT_LOOP) {
Jon Loeliger89875e92006-10-10 17:03:43 -0500838 debug("%s: tsec: tx error\n", dev->name);
wdenk42d1f032003-10-15 23:53:47 +0000839 return result;
840 }
841 }
842
843 txIdx = (txIdx + 1) % TX_BUF_CNT;
844 result = rtx.txbd[txIdx].status & TXBD_STATS;
845
846 return result;
847}
848
Jon Loeliger89875e92006-10-10 17:03:43 -0500849static int tsec_recv(struct eth_device *dev)
wdenk42d1f032003-10-15 23:53:47 +0000850{
851 int length;
wdenk97d80fc2004-06-09 00:34:46 +0000852 struct tsec_private *priv = (struct tsec_private *)dev->priv;
853 volatile tsec_t *regs = priv->regs;
wdenk42d1f032003-10-15 23:53:47 +0000854
Jon Loeliger89875e92006-10-10 17:03:43 -0500855 while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
wdenk42d1f032003-10-15 23:53:47 +0000856
857 length = rtx.rxbd[rxIdx].length;
858
859 /* Send the packet up if there were no errors */
860 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
861 NetReceive(NetRxPackets[rxIdx], length - 4);
wdenk97d80fc2004-06-09 00:34:46 +0000862 } else {
863 printf("Got error %x\n",
Jon Loeliger89875e92006-10-10 17:03:43 -0500864 (rtx.rxbd[rxIdx].status & RXBD_STATS));
wdenk42d1f032003-10-15 23:53:47 +0000865 }
866
867 rtx.rxbd[rxIdx].length = 0;
868
869 /* Set the wrap bit if this is the last element in the list */
Jon Loeliger89875e92006-10-10 17:03:43 -0500870 rtx.rxbd[rxIdx].status =
871 RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
wdenk42d1f032003-10-15 23:53:47 +0000872
873 rxIdx = (rxIdx + 1) % PKTBUFSRX;
874 }
875
Jon Loeliger89875e92006-10-10 17:03:43 -0500876 if (regs->ievent & IEVENT_BSY) {
wdenk42d1f032003-10-15 23:53:47 +0000877 regs->ievent = IEVENT_BSY;
878 regs->rstat = RSTAT_CLEAR_RHALT;
879 }
880
881 return -1;
882
883}
884
wdenk97d80fc2004-06-09 00:34:46 +0000885/* Stop the interface */
Jon Loeliger89875e92006-10-10 17:03:43 -0500886static void tsec_halt(struct eth_device *dev)
wdenk42d1f032003-10-15 23:53:47 +0000887{
wdenk97d80fc2004-06-09 00:34:46 +0000888 struct tsec_private *priv = (struct tsec_private *)dev->priv;
889 volatile tsec_t *regs = priv->regs;
wdenk42d1f032003-10-15 23:53:47 +0000890
891 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
892 regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS);
893
Jon Loeliger89875e92006-10-10 17:03:43 -0500894 while (!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))) ;
wdenk42d1f032003-10-15 23:53:47 +0000895
896 regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN);
897
wdenk97d80fc2004-06-09 00:34:46 +0000898 /* Shut down the PHY, as needed */
Ben Warren4653f912006-10-26 14:38:25 -0400899 if(priv->phyinfo)
900 phy_run_commands(priv, priv->phyinfo->shutdown);
wdenk42d1f032003-10-15 23:53:47 +0000901}
wdenk7abf0c52004-04-18 21:45:42 +0000902
Paul Gortmaker91e25762007-01-16 11:38:14 -0500903/* The 5411 id is 0x206070, the 5421 is 0x2060e0 */
904struct phy_info phy_info_BCM5461S = {
905 0x02060c1, /* 5461 ID */
906 "Broadcom BCM5461S",
907 0, /* not clear to me what minor revisions we can shift away */
908 (struct phy_cmd[]) { /* config */
909 /* Reset and configure the PHY */
910 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
911 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
912 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
913 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
914 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
915 {miim_end,}
916 },
917 (struct phy_cmd[]) { /* startup */
918 /* Status is read once to clear old link state */
919 {MIIM_STATUS, miim_read, NULL},
920 /* Auto-negotiate */
921 {MIIM_STATUS, miim_read, &mii_parse_sr},
922 /* Read the status */
923 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
924 {miim_end,}
925 },
926 (struct phy_cmd[]) { /* shutdown */
927 {miim_end,}
928 },
929};
930
wdenk97d80fc2004-06-09 00:34:46 +0000931struct phy_info phy_info_M88E1011S = {
932 0x01410c6,
933 "Marvell 88E1011S",
934 4,
Jon Loeliger89875e92006-10-10 17:03:43 -0500935 (struct phy_cmd[]){ /* config */
936 /* Reset and configure the PHY */
937 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
938 {0x1d, 0x1f, NULL},
939 {0x1e, 0x200c, NULL},
940 {0x1d, 0x5, NULL},
941 {0x1e, 0x0, NULL},
942 {0x1e, 0x100, NULL},
943 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
944 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
945 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
946 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
947 {miim_end,}
948 },
949 (struct phy_cmd[]){ /* startup */
950 /* Status is read once to clear old link state */
951 {MIIM_STATUS, miim_read, NULL},
952 /* Auto-negotiate */
953 {MIIM_STATUS, miim_read, &mii_parse_sr},
954 /* Read the status */
955 {MIIM_88E1011_PHY_STATUS, miim_read,
956 &mii_parse_88E1011_psr},
957 {miim_end,}
958 },
959 (struct phy_cmd[]){ /* shutdown */
960 {miim_end,}
961 },
wdenk97d80fc2004-06-09 00:34:46 +0000962};
963
wdenk9d46ea42005-03-14 23:56:42 +0000964struct phy_info phy_info_M88E1111S = {
965 0x01410cc,
966 "Marvell 88E1111S",
967 4,
Jon Loeliger89875e92006-10-10 17:03:43 -0500968 (struct phy_cmd[]){ /* config */
969 /* Reset and configure the PHY */
970 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
971 {0x1d, 0x1f, NULL},
972 {0x1e, 0x200c, NULL},
973 {0x1d, 0x5, NULL},
974 {0x1e, 0x0, NULL},
975 {0x1e, 0x100, NULL},
Nick Spencef484dc72006-09-07 07:39:46 -0700976 {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */
Jon Loeliger89875e92006-10-10 17:03:43 -0500977 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
978 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
979 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
980 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
981 {miim_end,}
982 },
983 (struct phy_cmd[]){ /* startup */
984 /* Status is read once to clear old link state */
985 {MIIM_STATUS, miim_read, NULL},
986 /* Auto-negotiate */
987 {MIIM_STATUS, miim_read, &mii_parse_sr},
988 /* Read the status */
989 {MIIM_88E1011_PHY_STATUS, miim_read,
990 &mii_parse_88E1011_psr},
991 {miim_end,}
992 },
993 (struct phy_cmd[]){ /* shutdown */
994 {miim_end,}
995 },
wdenk9d46ea42005-03-14 23:56:42 +0000996};
997
Andy Fleming09f3e092006-09-13 10:34:18 -0500998static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv)
999{
Andy Fleming09f3e092006-09-13 10:34:18 -05001000 uint mii_data = read_phy_reg(priv, mii_reg);
1001
Andy Fleming09f3e092006-09-13 10:34:18 -05001002 /* Setting MIIM_88E1145_PHY_EXT_CR */
1003 if (priv->flags & TSEC_REDUCED)
1004 return mii_data |
Jon Loeliger89875e92006-10-10 17:03:43 -05001005 MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY;
Andy Fleming09f3e092006-09-13 10:34:18 -05001006 else
1007 return mii_data;
1008}
1009
1010static struct phy_info phy_info_M88E1145 = {
1011 0x01410cd,
1012 "Marvell 88E1145",
1013 4,
Jon Loeliger89875e92006-10-10 17:03:43 -05001014 (struct phy_cmd[]){ /* config */
1015 /* Errata E0, E1 */
1016 {29, 0x001b, NULL},
1017 {30, 0x418f, NULL},
1018 {29, 0x0016, NULL},
1019 {30, 0xa2da, NULL},
Andy Fleming09f3e092006-09-13 10:34:18 -05001020
Jon Loeliger89875e92006-10-10 17:03:43 -05001021 /* Reset and configure the PHY */
1022 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1023 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1024 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1025 {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO,
1026 NULL},
1027 {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode},
1028 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1029 {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL},
1030 {miim_end,}
1031 },
1032 (struct phy_cmd[]){ /* startup */
1033 /* Status is read once to clear old link state */
1034 {MIIM_STATUS, miim_read, NULL},
1035 /* Auto-negotiate */
1036 {MIIM_STATUS, miim_read, &mii_parse_sr},
1037 {MIIM_88E1111_PHY_LED_CONTROL,
1038 MIIM_88E1111_PHY_LED_DIRECT, NULL},
1039 /* Read the Status */
1040 {MIIM_88E1011_PHY_STATUS, miim_read,
1041 &mii_parse_88E1011_psr},
1042 {miim_end,}
1043 },
1044 (struct phy_cmd[]){ /* shutdown */
1045 {miim_end,}
1046 },
Andy Fleming09f3e092006-09-13 10:34:18 -05001047};
1048
wdenk97d80fc2004-06-09 00:34:46 +00001049struct phy_info phy_info_cis8204 = {
1050 0x3f11,
1051 "Cicada Cis8204",
1052 6,
Jon Loeliger89875e92006-10-10 17:03:43 -05001053 (struct phy_cmd[]){ /* config */
1054 /* Override PHY config settings */
1055 {MIIM_CIS8201_AUX_CONSTAT,
1056 MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1057 /* Configure some basic stuff */
1058 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1059 {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT,
1060 &mii_cis8204_fixled},
1061 {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT,
1062 &mii_cis8204_setmode},
1063 {miim_end,}
1064 },
1065 (struct phy_cmd[]){ /* startup */
1066 /* Read the Status (2x to make sure link is right) */
1067 {MIIM_STATUS, miim_read, NULL},
1068 /* Auto-negotiate */
1069 {MIIM_STATUS, miim_read, &mii_parse_sr},
1070 /* Read the status */
1071 {MIIM_CIS8201_AUX_CONSTAT, miim_read,
1072 &mii_parse_cis8201},
1073 {miim_end,}
1074 },
1075 (struct phy_cmd[]){ /* shutdown */
1076 {miim_end,}
1077 },
wdenk97d80fc2004-06-09 00:34:46 +00001078};
1079
1080/* Cicada 8201 */
1081struct phy_info phy_info_cis8201 = {
1082 0xfc41,
1083 "CIS8201",
1084 4,
Jon Loeliger89875e92006-10-10 17:03:43 -05001085 (struct phy_cmd[]){ /* config */
1086 /* Override PHY config settings */
1087 {MIIM_CIS8201_AUX_CONSTAT,
1088 MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1089 /* Set up the interface mode */
1090 {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT,
1091 NULL},
1092 /* Configure some basic stuff */
1093 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1094 {miim_end,}
1095 },
1096 (struct phy_cmd[]){ /* startup */
1097 /* Read the Status (2x to make sure link is right) */
1098 {MIIM_STATUS, miim_read, NULL},
1099 /* Auto-negotiate */
1100 {MIIM_STATUS, miim_read, &mii_parse_sr},
1101 /* Read the status */
1102 {MIIM_CIS8201_AUX_CONSTAT, miim_read,
1103 &mii_parse_cis8201},
1104 {miim_end,}
1105 },
1106 (struct phy_cmd[]){ /* shutdown */
1107 {miim_end,}
1108 },
wdenk97d80fc2004-06-09 00:34:46 +00001109};
Jon Loeligerdebb7352006-04-26 17:58:56 -05001110struct phy_info phy_info_VSC8244 = {
Jon Loeliger89875e92006-10-10 17:03:43 -05001111 0x3f1b,
1112 "Vitesse VSC8244",
1113 6,
1114 (struct phy_cmd[]){ /* config */
1115 /* Override PHY config settings */
1116 /* Configure some basic stuff */
1117 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1118 {miim_end,}
1119 },
1120 (struct phy_cmd[]){ /* startup */
1121 /* Read the Status (2x to make sure link is right) */
1122 {MIIM_STATUS, miim_read, NULL},
1123 /* Auto-negotiate */
1124 {MIIM_STATUS, miim_read, &mii_parse_sr},
1125 /* Read the status */
1126 {MIIM_VSC8244_AUX_CONSTAT, miim_read,
1127 &mii_parse_vsc8244},
1128 {miim_end,}
1129 },
1130 (struct phy_cmd[]){ /* shutdown */
1131 {miim_end,}
1132 },
Jon Loeligerdebb7352006-04-26 17:58:56 -05001133};
wdenk97d80fc2004-06-09 00:34:46 +00001134
wdenk97d80fc2004-06-09 00:34:46 +00001135struct phy_info phy_info_dm9161 = {
1136 0x0181b88,
1137 "Davicom DM9161E",
1138 4,
Jon Loeliger89875e92006-10-10 17:03:43 -05001139 (struct phy_cmd[]){ /* config */
1140 {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL},
1141 /* Do not bypass the scrambler/descrambler */
1142 {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL},
1143 /* Clear 10BTCSR to default */
1144 {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT,
1145 NULL},
1146 /* Configure some basic stuff */
1147 {MIIM_CONTROL, MIIM_CR_INIT, NULL},
1148 /* Restart Auto Negotiation */
1149 {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL},
1150 {miim_end,}
1151 },
1152 (struct phy_cmd[]){ /* startup */
1153 /* Status is read once to clear old link state */
1154 {MIIM_STATUS, miim_read, NULL},
1155 /* Auto-negotiate */
1156 {MIIM_STATUS, miim_read, &mii_parse_sr},
1157 /* Read the status */
1158 {MIIM_DM9161_SCSR, miim_read,
1159 &mii_parse_dm9161_scsr},
1160 {miim_end,}
1161 },
1162 (struct phy_cmd[]){ /* shutdown */
1163 {miim_end,}
1164 },
wdenk97d80fc2004-06-09 00:34:46 +00001165};
David Updegraffaf1c2b82007-04-20 14:34:48 -05001166/* a generic flavor. */
1167struct phy_info phy_info_generic = {
1168 0,
1169 "Unknown/Generic PHY",
1170 32,
1171 (struct phy_cmd[]) { /* config */
1172 {PHY_BMCR, PHY_BMCR_RESET, NULL},
1173 {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL},
1174 {miim_end,}
1175 },
1176 (struct phy_cmd[]) { /* startup */
1177 {PHY_BMSR, miim_read, NULL},
1178 {PHY_BMSR, miim_read, &mii_parse_sr},
1179 {PHY_BMSR, miim_read, &mii_parse_link},
1180 {miim_end,}
1181 },
1182 (struct phy_cmd[]) { /* shutdown */
1183 {miim_end,}
1184 }
1185};
1186
wdenk97d80fc2004-06-09 00:34:46 +00001187
wdenk3dd7f0f2005-04-04 23:43:44 +00001188uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv)
1189{
wdenk3c2b3d42005-04-05 23:32:21 +00001190 unsigned int speed;
1191 if (priv->link) {
1192 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK;
wdenk3dd7f0f2005-04-04 23:43:44 +00001193
wdenk3c2b3d42005-04-05 23:32:21 +00001194 switch (speed) {
1195 case MIIM_LXT971_SR2_10HDX:
1196 priv->speed = 10;
1197 priv->duplexity = 0;
1198 break;
1199 case MIIM_LXT971_SR2_10FDX:
1200 priv->speed = 10;
1201 priv->duplexity = 1;
1202 break;
1203 case MIIM_LXT971_SR2_100HDX:
1204 priv->speed = 100;
1205 priv->duplexity = 0;
1206 default:
1207 priv->speed = 100;
1208 priv->duplexity = 1;
1209 break;
1210 }
1211 } else {
1212 priv->speed = 0;
1213 priv->duplexity = 0;
1214 }
wdenk3dd7f0f2005-04-04 23:43:44 +00001215
wdenk3c2b3d42005-04-05 23:32:21 +00001216 return 0;
wdenk3dd7f0f2005-04-04 23:43:44 +00001217}
1218
wdenk9d46ea42005-03-14 23:56:42 +00001219static struct phy_info phy_info_lxt971 = {
1220 0x0001378e,
1221 "LXT971",
1222 4,
Jon Loeliger89875e92006-10-10 17:03:43 -05001223 (struct phy_cmd[]){ /* config */
1224 {MIIM_CR, MIIM_CR_INIT, mii_cr_init}, /* autonegotiate */
1225 {miim_end,}
1226 },
1227 (struct phy_cmd[]){ /* startup - enable interrupts */
1228 /* { 0x12, 0x00f2, NULL }, */
1229 {MIIM_STATUS, miim_read, NULL},
1230 {MIIM_STATUS, miim_read, &mii_parse_sr},
1231 {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2},
1232 {miim_end,}
1233 },
1234 (struct phy_cmd[]){ /* shutdown - disable interrupts */
1235 {miim_end,}
1236 },
wdenk9d46ea42005-03-14 23:56:42 +00001237};
1238
Wolfgang Denkbe5048f2006-03-12 22:50:55 +01001239/* Parse the DP83865's link and auto-neg status register for speed and duplex
Jon Loeliger89875e92006-10-10 17:03:43 -05001240 * information
1241 */
Wolfgang Denkbe5048f2006-03-12 22:50:55 +01001242uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv)
1243{
1244 switch (mii_reg & MIIM_DP83865_SPD_MASK) {
1245
1246 case MIIM_DP83865_SPD_1000:
1247 priv->speed = 1000;
1248 break;
1249
1250 case MIIM_DP83865_SPD_100:
1251 priv->speed = 100;
1252 break;
1253
1254 default:
1255 priv->speed = 10;
1256 break;
1257
1258 }
1259
1260 if (mii_reg & MIIM_DP83865_DPX_FULL)
1261 priv->duplexity = 1;
1262 else
1263 priv->duplexity = 0;
1264
1265 return 0;
1266}
1267
1268struct phy_info phy_info_dp83865 = {
1269 0x20005c7,
1270 "NatSemi DP83865",
1271 4,
Jon Loeliger89875e92006-10-10 17:03:43 -05001272 (struct phy_cmd[]){ /* config */
1273 {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL},
1274 {miim_end,}
1275 },
1276 (struct phy_cmd[]){ /* startup */
1277 /* Status is read once to clear old link state */
1278 {MIIM_STATUS, miim_read, NULL},
1279 /* Auto-negotiate */
1280 {MIIM_STATUS, miim_read, &mii_parse_sr},
1281 /* Read the link and auto-neg status */
1282 {MIIM_DP83865_LANR, miim_read,
1283 &mii_parse_dp83865_lanr},
1284 {miim_end,}
1285 },
1286 (struct phy_cmd[]){ /* shutdown */
1287 {miim_end,}
1288 },
Wolfgang Denkbe5048f2006-03-12 22:50:55 +01001289};
1290
wdenk97d80fc2004-06-09 00:34:46 +00001291struct phy_info *phy_info[] = {
wdenk97d80fc2004-06-09 00:34:46 +00001292 &phy_info_cis8204,
Timur Tabi2ad6b512006-10-31 18:44:42 -06001293 &phy_info_cis8201,
Paul Gortmaker91e25762007-01-16 11:38:14 -05001294 &phy_info_BCM5461S,
wdenk97d80fc2004-06-09 00:34:46 +00001295 &phy_info_M88E1011S,
wdenk9d46ea42005-03-14 23:56:42 +00001296 &phy_info_M88E1111S,
Andy Fleming09f3e092006-09-13 10:34:18 -05001297 &phy_info_M88E1145,
wdenk97d80fc2004-06-09 00:34:46 +00001298 &phy_info_dm9161,
wdenk9d46ea42005-03-14 23:56:42 +00001299 &phy_info_lxt971,
Jon Loeligerdebb7352006-04-26 17:58:56 -05001300 &phy_info_VSC8244,
Wolfgang Denkbe5048f2006-03-12 22:50:55 +01001301 &phy_info_dp83865,
David Updegraffaf1c2b82007-04-20 14:34:48 -05001302 &phy_info_generic,
wdenk97d80fc2004-06-09 00:34:46 +00001303 NULL
1304};
1305
wdenk97d80fc2004-06-09 00:34:46 +00001306/* Grab the identifier of the device's PHY, and search through
wdenk9d46ea42005-03-14 23:56:42 +00001307 * all of the known PHYs to see if one matches. If so, return
Jon Loeliger89875e92006-10-10 17:03:43 -05001308 * it, if not, return NULL
1309 */
1310struct phy_info *get_phy_info(struct eth_device *dev)
wdenk97d80fc2004-06-09 00:34:46 +00001311{
1312 struct tsec_private *priv = (struct tsec_private *)dev->priv;
1313 uint phy_reg, phy_ID;
1314 int i;
1315 struct phy_info *theInfo = NULL;
1316
1317 /* Grab the bits from PHYIR1, and put them in the upper half */
1318 phy_reg = read_phy_reg(priv, MIIM_PHYIR1);
1319 phy_ID = (phy_reg & 0xffff) << 16;
1320
1321 /* Grab the bits from PHYIR2, and put them in the lower half */
1322 phy_reg = read_phy_reg(priv, MIIM_PHYIR2);
1323 phy_ID |= (phy_reg & 0xffff);
1324
1325 /* loop through all the known PHY types, and find one that */
1326 /* matches the ID we read from the PHY. */
Jon Loeliger89875e92006-10-10 17:03:43 -05001327 for (i = 0; phy_info[i]; i++) {
1328 if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift))
wdenk97d80fc2004-06-09 00:34:46 +00001329 theInfo = phy_info[i];
1330 }
1331
Jon Loeliger89875e92006-10-10 17:03:43 -05001332 if (theInfo == NULL) {
wdenk97d80fc2004-06-09 00:34:46 +00001333 printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID);
1334 return NULL;
1335 } else {
Stefan Roese5810dc32005-09-21 18:20:22 +02001336 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID);
wdenk97d80fc2004-06-09 00:34:46 +00001337 }
1338
1339 return theInfo;
1340}
1341
wdenk97d80fc2004-06-09 00:34:46 +00001342/* Execute the given series of commands on the given device's
Jon Loeliger89875e92006-10-10 17:03:43 -05001343 * PHY, running functions as necessary
1344 */
wdenk97d80fc2004-06-09 00:34:46 +00001345void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd)
1346{
1347 int i;
1348 uint result;
1349 volatile tsec_t *phyregs = priv->phyregs;
1350
1351 phyregs->miimcfg = MIIMCFG_RESET;
1352
1353 phyregs->miimcfg = MIIMCFG_INIT_VALUE;
1354
Jon Loeliger89875e92006-10-10 17:03:43 -05001355 while (phyregs->miimind & MIIMIND_BUSY) ;
wdenk97d80fc2004-06-09 00:34:46 +00001356
Jon Loeliger89875e92006-10-10 17:03:43 -05001357 for (i = 0; cmd->mii_reg != miim_end; i++) {
1358 if (cmd->mii_data == miim_read) {
wdenk97d80fc2004-06-09 00:34:46 +00001359 result = read_phy_reg(priv, cmd->mii_reg);
1360
Jon Loeliger89875e92006-10-10 17:03:43 -05001361 if (cmd->funct != NULL)
1362 (*(cmd->funct)) (result, priv);
wdenk97d80fc2004-06-09 00:34:46 +00001363
1364 } else {
Jon Loeliger89875e92006-10-10 17:03:43 -05001365 if (cmd->funct != NULL)
1366 result = (*(cmd->funct)) (cmd->mii_reg, priv);
wdenk97d80fc2004-06-09 00:34:46 +00001367 else
1368 result = cmd->mii_data;
1369
1370 write_phy_reg(priv, cmd->mii_reg, result);
1371
1372 }
1373 cmd++;
1374 }
1375}
1376
wdenk97d80fc2004-06-09 00:34:46 +00001377/* Relocate the function pointers in the phy cmd lists */
1378static void relocate_cmds(void)
1379{
1380 struct phy_cmd **cmdlistptr;
1381 struct phy_cmd *cmd;
Jon Loeliger89875e92006-10-10 17:03:43 -05001382 int i, j, k;
wdenk97d80fc2004-06-09 00:34:46 +00001383
Jon Loeliger89875e92006-10-10 17:03:43 -05001384 for (i = 0; phy_info[i]; i++) {
wdenk97d80fc2004-06-09 00:34:46 +00001385 /* First thing's first: relocate the pointers to the
1386 * PHY command structures (the structs were done) */
Jon Loeliger89875e92006-10-10 17:03:43 -05001387 phy_info[i] = (struct phy_info *)((uint) phy_info[i]
1388 + gd->reloc_off);
wdenk97d80fc2004-06-09 00:34:46 +00001389 phy_info[i]->name += gd->reloc_off;
1390 phy_info[i]->config =
Jon Loeliger89875e92006-10-10 17:03:43 -05001391 (struct phy_cmd *)((uint) phy_info[i]->config
1392 + gd->reloc_off);
wdenk97d80fc2004-06-09 00:34:46 +00001393 phy_info[i]->startup =
Jon Loeliger89875e92006-10-10 17:03:43 -05001394 (struct phy_cmd *)((uint) phy_info[i]->startup
1395 + gd->reloc_off);
wdenk97d80fc2004-06-09 00:34:46 +00001396 phy_info[i]->shutdown =
Jon Loeliger89875e92006-10-10 17:03:43 -05001397 (struct phy_cmd *)((uint) phy_info[i]->shutdown
1398 + gd->reloc_off);
wdenk97d80fc2004-06-09 00:34:46 +00001399
1400 cmdlistptr = &phy_info[i]->config;
Jon Loeliger89875e92006-10-10 17:03:43 -05001401 j = 0;
1402 for (; cmdlistptr <= &phy_info[i]->shutdown; cmdlistptr++) {
1403 k = 0;
1404 for (cmd = *cmdlistptr;
1405 cmd->mii_reg != miim_end;
1406 cmd++) {
wdenk97d80fc2004-06-09 00:34:46 +00001407 /* Only relocate non-NULL pointers */
Jon Loeliger89875e92006-10-10 17:03:43 -05001408 if (cmd->funct)
wdenk97d80fc2004-06-09 00:34:46 +00001409 cmd->funct += gd->reloc_off;
1410
1411 k++;
1412 }
1413 j++;
1414 }
1415 }
1416
1417 relocated = 1;
1418}
1419
Marian Balakowicz63ff0042005-10-28 22:30:33 +02001420#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) \
1421 && !defined(BITBANGMII)
wdenk97d80fc2004-06-09 00:34:46 +00001422
Jon Loeliger89875e92006-10-10 17:03:43 -05001423struct tsec_private *get_priv_for_phy(unsigned char phyaddr)
wdenk97d80fc2004-06-09 00:34:46 +00001424{
1425 int i;
1426
Jon Loeliger89875e92006-10-10 17:03:43 -05001427 for (i = 0; i < MAXCONTROLLERS; i++) {
1428 if (privlist[i]->phyaddr == phyaddr)
wdenk97d80fc2004-06-09 00:34:46 +00001429 return privlist[i];
1430 }
1431
1432 return NULL;
1433}
1434
wdenk7abf0c52004-04-18 21:45:42 +00001435/*
1436 * Read a MII PHY register.
1437 *
1438 * Returns:
wdenk97d80fc2004-06-09 00:34:46 +00001439 * 0 on success
wdenk7abf0c52004-04-18 21:45:42 +00001440 */
Marian Balakowicz63ff0042005-10-28 22:30:33 +02001441static int tsec_miiphy_read(char *devname, unsigned char addr,
Jon Loeliger89875e92006-10-10 17:03:43 -05001442 unsigned char reg, unsigned short *value)
wdenk7abf0c52004-04-18 21:45:42 +00001443{
wdenk97d80fc2004-06-09 00:34:46 +00001444 unsigned short ret;
1445 struct tsec_private *priv = get_priv_for_phy(addr);
wdenk7abf0c52004-04-18 21:45:42 +00001446
Jon Loeliger89875e92006-10-10 17:03:43 -05001447 if (NULL == priv) {
wdenk97d80fc2004-06-09 00:34:46 +00001448 printf("Can't read PHY at address %d\n", addr);
1449 return -1;
1450 }
1451
1452 ret = (unsigned short)read_phy_reg(priv, reg);
1453 *value = ret;
wdenk7abf0c52004-04-18 21:45:42 +00001454
1455 return 0;
1456}
1457
1458/*
1459 * Write a MII PHY register.
1460 *
1461 * Returns:
wdenk97d80fc2004-06-09 00:34:46 +00001462 * 0 on success
wdenk7abf0c52004-04-18 21:45:42 +00001463 */
Marian Balakowicz63ff0042005-10-28 22:30:33 +02001464static int tsec_miiphy_write(char *devname, unsigned char addr,
Jon Loeliger89875e92006-10-10 17:03:43 -05001465 unsigned char reg, unsigned short value)
wdenk7abf0c52004-04-18 21:45:42 +00001466{
wdenk97d80fc2004-06-09 00:34:46 +00001467 struct tsec_private *priv = get_priv_for_phy(addr);
wdenk7abf0c52004-04-18 21:45:42 +00001468
Jon Loeliger89875e92006-10-10 17:03:43 -05001469 if (NULL == priv) {
wdenk97d80fc2004-06-09 00:34:46 +00001470 printf("Can't write PHY at address %d\n", addr);
1471 return -1;
1472 }
1473
1474 write_phy_reg(priv, reg, value);
wdenk7abf0c52004-04-18 21:45:42 +00001475
1476 return 0;
1477}
wdenk97d80fc2004-06-09 00:34:46 +00001478
Marian Balakowicz63ff0042005-10-28 22:30:33 +02001479#endif /* defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
1480 && !defined(BITBANGMII) */
wdenk97d80fc2004-06-09 00:34:46 +00001481
wdenk42d1f032003-10-15 23:53:47 +00001482#endif /* CONFIG_TSEC_ENET */