| Rajeshwari Shinde | c5e3710 | 2012-06-06 19:54:29 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Samsung Electronics |
| 3 | * Rajeshwari Shinde <rajeshwari.s@samsung.com> |
| 4 | * |
| Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| Rajeshwari Shinde | c5e3710 | 2012-06-06 19:54:29 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef __ASM_ARM_ARCH_PERIPH_H |
| 9 | #define __ASM_ARM_ARCH_PERIPH_H |
| 10 | |
| 11 | /* |
| Rajeshwari Shinde | d055911 | 2012-12-26 20:03:11 +0000 | [diff] [blame] | 12 | * Peripherals required for pinmux configuration. List will |
| Rajeshwari Shinde | c5e3710 | 2012-06-06 19:54:29 +0000 | [diff] [blame] | 13 | * grow with support for more devices getting added. |
| Rajeshwari Shinde | d055911 | 2012-12-26 20:03:11 +0000 | [diff] [blame] | 14 | * Numbering based on interrupt table. |
| Rajeshwari Shinde | c5e3710 | 2012-06-06 19:54:29 +0000 | [diff] [blame] | 15 | * |
| 16 | */ |
| 17 | enum periph_id { |
| Rajeshwari Shinde | d055911 | 2012-12-26 20:03:11 +0000 | [diff] [blame] | 18 | PERIPH_ID_UART0 = 51, |
| 19 | PERIPH_ID_UART1, |
| 20 | PERIPH_ID_UART2, |
| 21 | PERIPH_ID_UART3, |
| 22 | PERIPH_ID_I2C0 = 56, |
| Rajeshwari Shinde | c65c05f | 2012-07-23 21:23:51 +0000 | [diff] [blame] | 23 | PERIPH_ID_I2C1, |
| 24 | PERIPH_ID_I2C2, |
| 25 | PERIPH_ID_I2C3, |
| 26 | PERIPH_ID_I2C4, |
| 27 | PERIPH_ID_I2C5, |
| 28 | PERIPH_ID_I2C6, |
| 29 | PERIPH_ID_I2C7, |
| Rajeshwari Shinde | d055911 | 2012-12-26 20:03:11 +0000 | [diff] [blame] | 30 | PERIPH_ID_SPI0 = 68, |
| 31 | PERIPH_ID_SPI1, |
| 32 | PERIPH_ID_SPI2, |
| 33 | PERIPH_ID_SDMMC0 = 75, |
| Rajeshwari Shinde | c5e3710 | 2012-06-06 19:54:29 +0000 | [diff] [blame] | 34 | PERIPH_ID_SDMMC1, |
| 35 | PERIPH_ID_SDMMC2, |
| 36 | PERIPH_ID_SDMMC3, |
| Dani Krishna Mohan | 3dd22a3 | 2013-09-11 16:38:48 +0530 | [diff] [blame^] | 37 | PERIPH_ID_I2S0 = 98, |
| Rajeshwari Shinde | d055911 | 2012-12-26 20:03:11 +0000 | [diff] [blame] | 38 | PERIPH_ID_I2S1 = 99, |
| 39 | |
| 40 | /* Since following peripherals do |
| 41 | * not have shared peripheral interrupts (SPIs) |
| 42 | * they are numbered arbitiraly after the maximum |
| 43 | * SPIs Exynos has (128) |
| 44 | */ |
| 45 | PERIPH_ID_SROMC = 128, |
| Rajeshwari Shinde | fbb5743 | 2012-10-28 19:32:54 +0000 | [diff] [blame] | 46 | PERIPH_ID_SPI3, |
| 47 | PERIPH_ID_SPI4, |
| Rajeshwari Shinde | d055911 | 2012-12-26 20:03:11 +0000 | [diff] [blame] | 48 | PERIPH_ID_SDMMC4, |
| Padmavathi Venna | 394d64e | 2013-03-31 18:42:24 +0000 | [diff] [blame] | 49 | PERIPH_ID_PWM0, |
| 50 | PERIPH_ID_PWM1, |
| 51 | PERIPH_ID_PWM2, |
| 52 | PERIPH_ID_PWM3, |
| 53 | PERIPH_ID_PWM4, |
| Rajeshwari Shinde | c5e3710 | 2012-06-06 19:54:29 +0000 | [diff] [blame] | 54 | |
| 55 | PERIPH_ID_COUNT, |
| 56 | PERIPH_ID_NONE = -1, |
| 57 | }; |
| 58 | |
| 59 | #endif /* __ASM_ARM_ARCH_PERIPH_H */ |