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York Sune2b65ea2015-03-20 19:28:24 -07001/*
2 * Copyright 2015 Freescale Semiconductor
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6#include <common.h>
7#include <malloc.h>
8#include <errno.h>
9#include <netdev.h>
10#include <fsl_ifc.h>
11#include <fsl_ddr.h>
12#include <asm/io.h>
Yangbo Lu5a4d7442015-05-28 14:53:55 +053013#include <hwconfig.h>
York Sune2b65ea2015-03-20 19:28:24 -070014#include <fdt_support.h>
15#include <libfdt.h>
York Sune2b65ea2015-03-20 19:28:24 -070016#include <fsl-mc/fsl_mc.h>
17#include <environment.h>
Alexander Graf215b1fb2016-11-17 01:02:59 +010018#include <efi_loader.h>
York Sune2b65ea2015-03-20 19:28:24 -070019#include <i2c.h>
Mingkai Hu9f3183d2015-10-26 19:47:50 +080020#include <asm/arch/soc.h>
Saksham Jainfcfdb6d2016-03-23 16:24:35 +053021#include <fsl_sec.h>
York Sune2b65ea2015-03-20 19:28:24 -070022
23#include "../common/qixis.h"
Prabhakar Kushwaha44937212015-11-09 16:42:07 +053024#include "ls2080ardb_qixis.h"
Rai Harnindered2530d2016-03-23 17:04:38 +053025#include "../common/vid.h"
York Sune2b65ea2015-03-20 19:28:24 -070026
Yangbo Lu5a4d7442015-05-28 14:53:55 +053027#define PIN_MUX_SEL_SDHC 0x00
Haikun.Wang@freescale.com5989df72015-06-26 19:58:24 +080028#define PIN_MUX_SEL_DSPI 0x0a
Yangbo Lu5a4d7442015-05-28 14:53:55 +053029
30#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
York Sune2b65ea2015-03-20 19:28:24 -070031DECLARE_GLOBAL_DATA_PTR;
32
Yangbo Lu5a4d7442015-05-28 14:53:55 +053033enum {
34 MUX_TYPE_SDHC,
Haikun.Wang@freescale.com5989df72015-06-26 19:58:24 +080035 MUX_TYPE_DSPI,
Yangbo Lu5a4d7442015-05-28 14:53:55 +053036};
37
York Sune2b65ea2015-03-20 19:28:24 -070038unsigned long long get_qixis_addr(void)
39{
40 unsigned long long addr;
41
42 if (gd->flags & GD_FLG_RELOC)
43 addr = QIXIS_BASE_PHYS;
44 else
45 addr = QIXIS_BASE_PHYS_EARLY;
46
47 /*
48 * IFC address under 256MB is mapped to 0x30000000, any address above
49 * is mapped to 0x5_10000000 up to 4GB.
50 */
51 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
52
53 return addr;
54}
55
56int checkboard(void)
57{
58 u8 sw;
Prabhakar Kushwahaff1b8e32015-05-28 14:54:07 +053059 char buf[15];
60
61 cpu_name(buf);
62 printf("Board: %s-RDB, ", buf);
York Sune2b65ea2015-03-20 19:28:24 -070063
64 sw = QIXIS_READ(arch);
York Sune2b65ea2015-03-20 19:28:24 -070065 printf("Board Arch: V%d, ", sw >> 4);
Prabhakar Kushwaha27df54b2015-05-28 14:54:04 +053066 printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
York Sune2b65ea2015-03-20 19:28:24 -070067
68 sw = QIXIS_READ(brdcfg[0]);
69 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
70
71 if (sw < 0x8)
72 printf("vBank: %d\n", sw);
73 else if (sw == 0x9)
74 puts("NAND\n");
75 else
76 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
77
78 printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
79
80 puts("SERDES1 Reference : ");
81 printf("Clock1 = 156.25MHz ");
82 printf("Clock2 = 156.25MHz");
83
84 puts("\nSERDES2 Reference : ");
85 printf("Clock1 = 100MHz ");
86 printf("Clock2 = 100MHz\n");
87
88 return 0;
89}
90
91unsigned long get_board_sys_clk(void)
92{
93 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
94
95 switch (sysclk_conf & 0x0F) {
96 case QIXIS_SYSCLK_83:
97 return 83333333;
98 case QIXIS_SYSCLK_100:
99 return 100000000;
100 case QIXIS_SYSCLK_125:
101 return 125000000;
102 case QIXIS_SYSCLK_133:
103 return 133333333;
104 case QIXIS_SYSCLK_150:
105 return 150000000;
106 case QIXIS_SYSCLK_160:
107 return 160000000;
108 case QIXIS_SYSCLK_166:
109 return 166666666;
110 }
111 return 66666666;
112}
113
114int select_i2c_ch_pca9547(u8 ch)
115{
116 int ret;
117
118 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
119 if (ret) {
120 puts("PCA: failed to select proper channel\n");
121 return ret;
122 }
123
124 return 0;
125}
126
Rai Harnindered2530d2016-03-23 17:04:38 +0530127int i2c_multiplexer_select_vid_channel(u8 channel)
128{
129 return select_i2c_ch_pca9547(channel);
130}
131
Haikun.Wang@freescale.com5989df72015-06-26 19:58:24 +0800132int config_board_mux(int ctrl_type)
133{
134 u8 reg5;
135
136 reg5 = QIXIS_READ(brdcfg[5]);
137
138 switch (ctrl_type) {
139 case MUX_TYPE_SDHC:
140 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
141 break;
142 case MUX_TYPE_DSPI:
143 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
144 break;
145 default:
146 printf("Wrong mux interface type\n");
147 return -1;
148 }
149
150 QIXIS_WRITE(brdcfg[5], reg5);
151
152 return 0;
153}
154
York Sune2b65ea2015-03-20 19:28:24 -0700155int board_init(void)
156{
Haikun.Wang@freescale.com5989df72015-06-26 19:58:24 +0800157 char *env_hwconfig;
158 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
York Sun931e8752016-05-26 13:59:03 -0700159#ifdef CONFIG_FSL_MC_ENET
Shaohui Xieabc7d0f2016-01-28 15:38:15 +0800160 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
York Sun931e8752016-05-26 13:59:03 -0700161#endif
Haikun.Wang@freescale.com5989df72015-06-26 19:58:24 +0800162 u32 val;
163
York Sune2b65ea2015-03-20 19:28:24 -0700164 init_final_memctl_regs();
165
Haikun.Wang@freescale.com5989df72015-06-26 19:58:24 +0800166 val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
167
168 env_hwconfig = getenv("hwconfig");
169
170 if (hwconfig_f("dspi", env_hwconfig) &&
171 DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
172 config_board_mux(MUX_TYPE_DSPI);
173 else
174 config_board_mux(MUX_TYPE_SDHC);
175
York Sune2b65ea2015-03-20 19:28:24 -0700176#ifdef CONFIG_ENV_IS_NOWHERE
177 gd->env_addr = (ulong)&default_environment[0];
178#endif
179 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
180
181 QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
182
York Sun931e8752016-05-26 13:59:03 -0700183#ifdef CONFIG_FSL_MC_ENET
Shaohui Xieabc7d0f2016-01-28 15:38:15 +0800184 /* invert AQR405 IRQ pins polarity */
185 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
York Sun931e8752016-05-26 13:59:03 -0700186#endif
Shaohui Xieabc7d0f2016-01-28 15:38:15 +0800187
York Sune2b65ea2015-03-20 19:28:24 -0700188 return 0;
189}
190
191int board_early_init_f(void)
192{
193 fsl_lsch3_early_init_f();
194 return 0;
195}
196
Yangbo Lu5a4d7442015-05-28 14:53:55 +0530197int misc_init_r(void)
198{
199 if (hwconfig("sdhc"))
200 config_board_mux(MUX_TYPE_SDHC);
201
Rai Harnindered2530d2016-03-23 17:04:38 +0530202 if (adjust_vdd(0))
203 printf("Warning: Adjusting core voltage failed.\n");
204
Alexander Graf215b1fb2016-11-17 01:02:59 +0100205#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD)
206 if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
207 efi_add_memory_map(gd->bd->bi_dram[2].start,
208 gd->bd->bi_dram[2].size >> EFI_PAGE_SHIFT,
209 EFI_RESERVED_MEMORY_TYPE, false);
210 }
211#endif
212
Yangbo Lu5a4d7442015-05-28 14:53:55 +0530213 return 0;
214}
215
York Sune2b65ea2015-03-20 19:28:24 -0700216void detail_board_ddr_info(void)
217{
218 puts("\nDDR ");
219 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
220 print_ddr_info(0);
Prabhakar Kushwaha44937212015-11-09 16:42:07 +0530221#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
York Sun3c1d2182016-04-04 11:41:26 -0700222 if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
York Sune2b65ea2015-03-20 19:28:24 -0700223 puts("\nDP-DDR ");
224 print_size(gd->bd->bi_dram[2].size, "");
225 print_ddr_info(CONFIG_DP_DDR_CTRL);
226 }
Prabhakar Kushwaha44937212015-11-09 16:42:07 +0530227#endif
York Sune2b65ea2015-03-20 19:28:24 -0700228}
229
230int dram_init(void)
231{
232 gd->ram_size = initdram(0);
233
234 return 0;
235}
236
237#if defined(CONFIG_ARCH_MISC_INIT)
238int arch_misc_init(void)
239{
Saksham Jainfcfdb6d2016-03-23 16:24:35 +0530240#ifdef CONFIG_FSL_CAAM
241 sec_init();
242#endif
York Sune2b65ea2015-03-20 19:28:24 -0700243 return 0;
244}
245#endif
246
York Sune2b65ea2015-03-20 19:28:24 -0700247#ifdef CONFIG_FSL_MC_ENET
248void fdt_fixup_board_enet(void *fdt)
249{
250 int offset;
251
Stuart Yodere91f1de2016-03-02 16:37:13 -0600252 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
York Sune2b65ea2015-03-20 19:28:24 -0700253
254 if (offset < 0)
Stuart Yodere91f1de2016-03-02 16:37:13 -0600255 offset = fdt_path_offset(fdt, "/fsl-mc");
York Sune2b65ea2015-03-20 19:28:24 -0700256
257 if (offset < 0) {
258 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
259 __func__, offset);
260 return;
261 }
262
263 if (get_mc_boot_status() == 0)
264 fdt_status_okay(fdt, offset);
265 else
266 fdt_status_fail(fdt, offset);
267}
Alexander Grafb7b84102016-11-17 01:02:57 +0100268
269void board_quiesce_devices(void)
270{
271 fsl_mc_ldpaa_exit(gd->bd);
272}
York Sune2b65ea2015-03-20 19:28:24 -0700273#endif
274
275#ifdef CONFIG_OF_BOARD_SETUP
276int ft_board_setup(void *blob, bd_t *bd)
277{
Bhupesh Sharmaa2dc8182015-05-28 14:54:10 +0530278 u64 base[CONFIG_NR_DRAM_BANKS];
279 u64 size[CONFIG_NR_DRAM_BANKS];
York Sune2b65ea2015-03-20 19:28:24 -0700280
281 ft_cpu_setup(blob, bd);
282
Bhupesh Sharmaa2dc8182015-05-28 14:54:10 +0530283 /* fixup DT for the two GPP DDR banks */
284 base[0] = gd->bd->bi_dram[0].start;
285 size[0] = gd->bd->bi_dram[0].size;
286 base[1] = gd->bd->bi_dram[1].start;
287 size[1] = gd->bd->bi_dram[1].size;
288
289 fdt_fixup_memory_banks(blob, base, size, 2);
York Sune2b65ea2015-03-20 19:28:24 -0700290
Sriram Dasha5c289b2016-09-16 17:12:15 +0530291 fsl_fdt_fixup_dr_usb(blob, bd);
Sriram Dashef53b8c2016-06-13 09:58:36 +0530292
York Sune2b65ea2015-03-20 19:28:24 -0700293#ifdef CONFIG_FSL_MC_ENET
294 fdt_fixup_board_enet(blob);
York Sune2b65ea2015-03-20 19:28:24 -0700295#endif
296
297 return 0;
298}
299#endif
300
301void qixis_dump_switch(void)
302{
303 int i, nr_of_cfgsw;
304
305 QIXIS_WRITE(cms[0], 0x00);
306 nr_of_cfgsw = QIXIS_READ(cms[1]);
307
308 puts("DIP switch settings dump:\n");
309 for (i = 1; i <= nr_of_cfgsw; i++) {
310 QIXIS_WRITE(cms[0], i);
311 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
312 }
313}
York Sunfc7b3852015-05-28 14:54:09 +0530314
315/*
316 * Board rev C and earlier has duplicated I2C addresses for 2nd controller.
317 * Both slots has 0x54, resulting 2nd slot unusable.
318 */
319void update_spd_address(unsigned int ctrl_num,
320 unsigned int slot,
321 unsigned int *addr)
322{
323 u8 sw;
324
325 sw = QIXIS_READ(arch);
326 if ((sw & 0xf) < 0x3) {
327 if (ctrl_num == 1 && slot == 0)
328 *addr = SPD_EEPROM_ADDRESS4;
329 else if (ctrl_num == 1 && slot == 1)
330 *addr = SPD_EEPROM_ADDRESS3;
331 }
332}