blob: 0c2185c529f7c880fa96178a233d277336bca8a1 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Stefan Roesea4884832014-10-22 12:13:19 +02002/*
3 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
Stefan Roesea4884832014-10-22 12:13:19 +02004 */
5
6#ifndef _CONFIG_DB_MV7846MP_GP_H
7#define _CONFIG_DB_MV7846MP_GP_H
8
9/*
10 * High Level Configuration Options (easy to change)
11 */
Stefan Roesea4884832014-10-22 12:13:19 +020012
Stefan Roese2923c2d2015-08-06 14:27:36 +020013/*
14 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
15 * for DDR ECC byte filling in the SPL before loading the main
16 * U-Boot into it.
17 */
Stefan Roesea4884832014-10-22 12:13:19 +020018#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
19
Stefan Roesea4884832014-10-22 12:13:19 +020020/* I2C */
21#define CONFIG_SYS_I2C
22#define CONFIG_SYS_I2C_MVTWSI
Paul Kocialkowskidd822422015-04-10 23:09:51 +020023#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
Stefan Roesea4884832014-10-22 12:13:19 +020024#define CONFIG_SYS_I2C_SLAVE 0x0
25#define CONFIG_SYS_I2C_SPEED 100000
26
27/* SPI NOR flash default params, used by sf commands */
Stefan Roesea4884832014-10-22 12:13:19 +020028
29/* Environment in SPI NOR flash */
Stefan Roesea4884832014-10-22 12:13:19 +020030
Stefan Roesea4884832014-10-22 12:13:19 +020031#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
Stefan Roesea4884832014-10-22 12:13:19 +020032
Stefan Roesea4884832014-10-22 12:13:19 +020033/*
34 * mv-common.h should be defined after CMD configs since it used them
35 * to enable certain macros
36 */
37#include "mv-common.h"
38
Stefan Roesee7778ec2015-01-19 11:33:47 +010039/*
40 * Memory layout while starting into the bin_hdr via the
41 * BootROM:
42 *
43 * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
44 * 0x4000.4030 bin_hdr start address
45 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
46 * 0x4007.fffc BootROM stack top
47 *
48 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
49 * L2 cache thus cannot be used.
50 */
51
52/* SPL */
53/* Defines for SPL */
Stefan Roesee7778ec2015-01-19 11:33:47 +010054#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
55
56#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
57#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
58
Stefan Roese64512232015-11-25 07:37:00 +010059#ifdef CONFIG_SPL_BUILD
60#define CONFIG_SYS_MALLOC_SIMPLE
61#endif
Stefan Roesee7778ec2015-01-19 11:33:47 +010062
63#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
64#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
65
Stefan Roesee7778ec2015-01-19 11:33:47 +010066/* SPL related SPI defines */
Stefan Roesee7778ec2015-01-19 11:33:47 +010067
68/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
Stefan Roesee7778ec2015-01-19 11:33:47 +010069#define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */
Stefan Roese698ffab2015-12-10 15:02:38 +010070#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */
Stefan Roesee7778ec2015-01-19 11:33:47 +010071
Stefan Roesea4884832014-10-22 12:13:19 +020072#endif /* _CONFIG_DB_MV7846MP_GP_H */