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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Stefan Roese3fda4ef2016-05-19 15:56:44 +02002/*
3 * Copyright (C) 2015 Marvell International Ltd.
4 *
5 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
Stefan Roese3fda4ef2016-05-19 15:56:44 +02006 */
7
8#include <common.h>
9#include <dm.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060010#include <log.h>
Stefan Roese3fda4ef2016-05-19 15:56:44 +020011#include <malloc.h>
12#include <spi.h>
Marek Behúndbbd5bd2018-04-24 17:21:26 +020013#include <clk.h>
Stefan Roese3fda4ef2016-05-19 15:56:44 +020014#include <wait_bit.h>
15#include <asm/io.h>
Simon Glass336d4612020-02-03 07:36:16 -070016#include <dm/device_compat.h>
Simon Glasscd93d622020-05-10 11:40:13 -060017#include <linux/bitops.h>
Stefan Roese3fda4ef2016-05-19 15:56:44 +020018
19DECLARE_GLOBAL_DATA_PTR;
20
21#define MVEBU_SPI_A3700_XFER_RDY BIT(1)
22#define MVEBU_SPI_A3700_FIFO_FLUSH BIT(9)
23#define MVEBU_SPI_A3700_BYTE_LEN BIT(5)
24#define MVEBU_SPI_A3700_CLK_PHA BIT(6)
25#define MVEBU_SPI_A3700_CLK_POL BIT(7)
26#define MVEBU_SPI_A3700_FIFO_EN BIT(17)
27#define MVEBU_SPI_A3700_SPI_EN_0 BIT(16)
Marek Behúndbbd5bd2018-04-24 17:21:26 +020028#define MVEBU_SPI_A3700_CLK_PRESCALE_MASK 0x1f
29
Stefan Roese3fda4ef2016-05-19 15:56:44 +020030
31/* SPI registers */
32struct spi_reg {
33 u32 ctrl; /* 0x10600 */
34 u32 cfg; /* 0x10604 */
35 u32 dout; /* 0x10608 */
36 u32 din; /* 0x1060c */
37};
38
39struct mvebu_spi_platdata {
40 struct spi_reg *spireg;
Marek Behúndbbd5bd2018-04-24 17:21:26 +020041 struct clk clk;
Stefan Roese3fda4ef2016-05-19 15:56:44 +020042};
43
44static void spi_cs_activate(struct spi_reg *reg, int cs)
45{
46 setbits_le32(&reg->ctrl, MVEBU_SPI_A3700_SPI_EN_0 << cs);
47}
48
49static void spi_cs_deactivate(struct spi_reg *reg, int cs)
50{
51 clrbits_le32(&reg->ctrl, MVEBU_SPI_A3700_SPI_EN_0 << cs);
52}
53
54/**
55 * spi_legacy_shift_byte() - triggers the real SPI transfer
56 * @bytelen: Indicate how many bytes to transfer.
57 * @dout: Buffer address of what to send.
58 * @din: Buffer address of where to receive.
59 *
60 * This function triggers the real SPI transfer in legacy mode. It
61 * will shift out char buffer from @dout, and shift in char buffer to
62 * @din, if necessary.
63 *
64 * This function assumes that only one byte is shifted at one time.
65 * However, it is not its responisbility to set the transfer type to
66 * one-byte. Also, it does not guarantee that it will work if transfer
67 * type becomes two-byte. See spi_set_legacy() for details.
68 *
69 * In legacy mode, simply write to the SPI_DOUT register will trigger
70 * the transfer.
71 *
72 * If @dout == NULL, which means no actual data needs to be sent out,
73 * then the function will shift out 0x00 in order to shift in data.
74 * The XFER_RDY flag is checked every time before accessing SPI_DOUT
75 * and SPI_DIN register.
76 *
77 * The number of transfers to be triggerred is decided by @bytelen.
78 *
79 * Return: 0 - cool
80 * -ETIMEDOUT - XFER_RDY flag timeout
81 */
82static int spi_legacy_shift_byte(struct spi_reg *reg, unsigned int bytelen,
83 const void *dout, void *din)
84{
85 const u8 *dout_8;
86 u8 *din_8;
87 int ret;
88
89 /* Use 0x00 as dummy dout */
90 const u8 dummy_dout = 0x0;
91 u32 pending_dout = 0x0;
92
93 /* dout_8: pointer of current dout */
94 dout_8 = dout;
95 /* din_8: pointer of current din */
96 din_8 = din;
97
98 while (bytelen) {
Álvaro Fernández Rojas48263502018-01-23 17:14:55 +010099 ret = wait_for_bit_le32(&reg->ctrl,
100 MVEBU_SPI_A3700_XFER_RDY,
101 true,100, false);
Stefan Roese3fda4ef2016-05-19 15:56:44 +0200102 if (ret)
103 return ret;
104
105 if (dout)
106 pending_dout = (u32)*dout_8;
107 else
108 pending_dout = (u32)dummy_dout;
109
110 /* Trigger the xfer */
111 writel(pending_dout, &reg->dout);
112
113 if (din) {
Álvaro Fernández Rojas48263502018-01-23 17:14:55 +0100114 ret = wait_for_bit_le32(&reg->ctrl,
115 MVEBU_SPI_A3700_XFER_RDY,
116 true, 100, false);
Stefan Roese3fda4ef2016-05-19 15:56:44 +0200117 if (ret)
118 return ret;
119
120 /* Read what is transferred in */
121 *din_8 = (u8)readl(&reg->din);
122 }
123
124 /* Don't increment the current pointer if NULL */
125 if (dout)
126 dout_8++;
127 if (din)
128 din_8++;
129
130 bytelen--;
131 }
132
133 return 0;
134}
135
136static int mvebu_spi_xfer(struct udevice *dev, unsigned int bitlen,
137 const void *dout, void *din, unsigned long flags)
138{
139 struct udevice *bus = dev->parent;
140 struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
141 struct spi_reg *reg = plat->spireg;
142 unsigned int bytelen;
143 int ret;
144
145 bytelen = bitlen / 8;
146
147 if (dout && din)
148 debug("This is a duplex transfer.\n");
149
150 /* Activate CS */
151 if (flags & SPI_XFER_BEGIN) {
152 debug("SPI: activate cs.\n");
153 spi_cs_activate(reg, spi_chip_select(dev));
154 }
155
156 /* Send and/or receive */
157 if (dout || din) {
158 ret = spi_legacy_shift_byte(reg, bytelen, dout, din);
159 if (ret)
160 return ret;
161 }
162
163 /* Deactivate CS */
164 if (flags & SPI_XFER_END) {
Álvaro Fernández Rojas48263502018-01-23 17:14:55 +0100165 ret = wait_for_bit_le32(&reg->ctrl,
166 MVEBU_SPI_A3700_XFER_RDY,
167 true, 100, false);
Stefan Roese3fda4ef2016-05-19 15:56:44 +0200168 if (ret)
169 return ret;
170
171 debug("SPI: deactivate cs.\n");
172 spi_cs_deactivate(reg, spi_chip_select(dev));
173 }
174
175 return 0;
176}
177
178static int mvebu_spi_set_speed(struct udevice *bus, uint hz)
179{
180 struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
181 struct spi_reg *reg = plat->spireg;
Marek Behúndbbd5bd2018-04-24 17:21:26 +0200182 u32 data, prescale;
Stefan Roese3fda4ef2016-05-19 15:56:44 +0200183
184 data = readl(&reg->cfg);
185
Marek Behúndbbd5bd2018-04-24 17:21:26 +0200186 prescale = DIV_ROUND_UP(clk_get_rate(&plat->clk), hz);
Marek Behún07a5cb92019-07-23 16:49:32 +0200187 if (prescale > 0xf)
Marek Behúndbbd5bd2018-04-24 17:21:26 +0200188 prescale = 0x10 + (prescale + 1) / 2;
Marek Behún07a5cb92019-07-23 16:49:32 +0200189 prescale = min(prescale, 0x1fu);
Stefan Roese3fda4ef2016-05-19 15:56:44 +0200190
Marek Behúndbbd5bd2018-04-24 17:21:26 +0200191 data &= ~MVEBU_SPI_A3700_CLK_PRESCALE_MASK;
192 data |= prescale & MVEBU_SPI_A3700_CLK_PRESCALE_MASK;
Stefan Roese3fda4ef2016-05-19 15:56:44 +0200193
194 writel(data, &reg->cfg);
195
196 return 0;
197}
198
199static int mvebu_spi_set_mode(struct udevice *bus, uint mode)
200{
201 struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
202 struct spi_reg *reg = plat->spireg;
203
204 /*
205 * Set SPI polarity
206 * 0: Serial interface clock is low when inactive
207 * 1: Serial interface clock is high when inactive
208 */
209 if (mode & SPI_CPOL)
210 setbits_le32(&reg->cfg, MVEBU_SPI_A3700_CLK_POL);
211 else
212 clrbits_le32(&reg->cfg, MVEBU_SPI_A3700_CLK_POL);
213 if (mode & SPI_CPHA)
214 setbits_le32(&reg->cfg, MVEBU_SPI_A3700_CLK_PHA);
215 else
216 clrbits_le32(&reg->cfg, MVEBU_SPI_A3700_CLK_PHA);
217
218 return 0;
219}
220
221static int mvebu_spi_probe(struct udevice *bus)
222{
223 struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
224 struct spi_reg *reg = plat->spireg;
225 u32 data;
226 int ret;
227
228 /*
229 * Settings SPI controller to be working in legacy mode, which
230 * means use only DO pin (I/O 1) for Data Out, and DI pin (I/O 0)
231 * for Data In.
232 */
233
234 /* Flush read/write FIFO */
235 data = readl(&reg->cfg);
236 writel(data | MVEBU_SPI_A3700_FIFO_FLUSH, &reg->cfg);
Álvaro Fernández Rojas48263502018-01-23 17:14:55 +0100237 ret = wait_for_bit_le32(&reg->cfg, MVEBU_SPI_A3700_FIFO_FLUSH,
238 false, 1000, false);
Stefan Roese3fda4ef2016-05-19 15:56:44 +0200239 if (ret)
240 return ret;
241
242 /* Disable FIFO mode */
243 data &= ~MVEBU_SPI_A3700_FIFO_EN;
244
245 /* Always shift 1 byte at a time */
246 data &= ~MVEBU_SPI_A3700_BYTE_LEN;
247
248 writel(data, &reg->cfg);
249
250 return 0;
251}
252
253static int mvebu_spi_ofdata_to_platdata(struct udevice *bus)
254{
255 struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
Marek Behúndbbd5bd2018-04-24 17:21:26 +0200256 int ret;
Stefan Roese3fda4ef2016-05-19 15:56:44 +0200257
Simon Glassa821c4a2017-05-17 17:18:05 -0600258 plat->spireg = (struct spi_reg *)devfdt_get_addr(bus);
Stefan Roese3fda4ef2016-05-19 15:56:44 +0200259
Marek Behúndbbd5bd2018-04-24 17:21:26 +0200260 ret = clk_get_by_index(bus, 0, &plat->clk);
261 if (ret) {
262 dev_err(bus, "cannot get clock\n");
263 return ret;
264 }
265
266 return 0;
267}
268
269static int mvebu_spi_remove(struct udevice *bus)
270{
271 struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
272
273 clk_free(&plat->clk);
Stefan Roese3fda4ef2016-05-19 15:56:44 +0200274
275 return 0;
276}
277
278static const struct dm_spi_ops mvebu_spi_ops = {
279 .xfer = mvebu_spi_xfer,
280 .set_speed = mvebu_spi_set_speed,
281 .set_mode = mvebu_spi_set_mode,
282 /*
283 * cs_info is not needed, since we require all chip selects to be
284 * in the device tree explicitly
285 */
286};
287
288static const struct udevice_id mvebu_spi_ids[] = {
289 { .compatible = "marvell,armada-3700-spi" },
290 { }
291};
292
293U_BOOT_DRIVER(mvebu_spi) = {
294 .name = "mvebu_spi",
295 .id = UCLASS_SPI,
296 .of_match = mvebu_spi_ids,
297 .ops = &mvebu_spi_ops,
298 .ofdata_to_platdata = mvebu_spi_ofdata_to_platdata,
299 .platdata_auto_alloc_size = sizeof(struct mvebu_spi_platdata),
300 .probe = mvebu_spi_probe,
Marek Behúndbbd5bd2018-04-24 17:21:26 +0200301 .remove = mvebu_spi_remove,
Stefan Roese3fda4ef2016-05-19 15:56:44 +0200302};