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Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +01001/*
2 * Copyright (C) 2016, Imagination Technologies Ltd.
3 *
4 * Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 *
8 * Imagination Technologies Ltd. MIPSfpga
9 */
10
11#ifndef __XILFPGA_CONFIG_H
12#define __XILFPGA_CONFIG_H
13
14/* BootROM + MIG is pretty smart. DDR and Cache initialized */
15#define CONFIG_SKIP_LOWLEVEL_INIT
16
17/*--------------------------------------------
18 * CPU configuration
19 */
20/* CPU Timer rate */
21#define CONFIG_SYS_MIPS_TIMER_FREQ 50000000
22
23/* Cache Configuration */
24#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
25
26/*----------------------------------------------------------------------
27 * Memory Layout
28 */
29
30/* SDRAM Configuration (for final code, data, stack, heap) */
31#define CONFIG_SYS_SDRAM_BASE 0x80000000
32#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 Mbytes */
33#define CONFIG_SYS_INIT_SP_ADDR \
34 (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 0x1000)
35
36#define CONFIG_SYS_MALLOC_LEN (256 << 10)
37#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
38#define CONFIG_SYS_LOAD_ADDR 0x80500000 /* default load address */
39
40/*----------------------------------------------------------------------
41 * Commands
42 */
43#define CONFIG_SYS_LONGHELP /* undef to save memory */
44
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +010045/*------------------------------------------------------------
46 * Console Configuration
47 */
48#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
49#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
Zubair Lutfullah Kakakhelebf2b9e2016-07-29 15:11:20 +010050
51/* -------------------------------------------------
52 * Environment
53 */
54#define CONFIG_ENV_IS_NOWHERE 1
55#define CONFIG_ENV_SIZE 0x4000
56
57/* ---------------------------------------------------------------------
58 * Board boot configuration
59 */
60#define CONFIG_TIMESTAMP /* Print image info with timestamp */
61
62#endif /* __XILFPGA_CONFIG_H */