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Stefano Babic8be4f402016-06-06 11:19:42 +02001/*
2 * Copyright (C) Stefano Babic <sbabic@denx.de>
3 *
4 * Configuration settings for the E+L i.MX6Q DO82 board.
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#ifndef __EL6Q_COMMON_CONFIG_H
10#define __EL6Q_COMMON_CONFIG_H
11
12#define CONFIG_BOARD_NAME EL6Q
13
14#include <config_distro_defaults.h>
15#include "mx6_common.h"
16
17#define CONFIG_IMX_THERMAL
18
19/* Size of malloc() pool */
20#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
21
Stefano Babic8be4f402016-06-06 11:19:42 +020022#define CONFIG_MXC_UART
23
24#ifdef CONFIG_SPL
Stefano Babic8be4f402016-06-06 11:19:42 +020025#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
26#define CONFIG_SPL_SPI_LOAD
27#include "imx6_spl.h"
28#endif
29
30/* MMC Configs */
31#define CONFIG_SYS_FSL_ESDHC_ADDR 0
32#define CONFIG_SYS_FSL_USDHC_NUM 2
33
34/* I2C config */
35#define CONFIG_SYS_I2C
36#define CONFIG_SYS_I2C_MXC
37#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
38#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
39#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
40#define CONFIG_SYS_I2C_SPEED 100000
41
42/* PMIC */
43#define CONFIG_POWER
44#define CONFIG_POWER_I2C
45#define CONFIG_POWER_PFUZE100
46#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
47
48/* Commands */
49#define CONFIG_MXC_SPI
50#define CONFIG_SF_DEFAULT_BUS 3
51#define CONFIG_SF_DEFAULT_CS 0
52#define CONFIG_SF_DEFAULT_SPEED 20000000
53#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
54
55/* allow to overwrite serial and ethaddr */
56#define CONFIG_ENV_OVERWRITE
57#define CONFIG_MXC_UART_BASE UART2_BASE
Stefano Babic8be4f402016-06-06 11:19:42 +020058
59/* Command definition */
60
61#define CONFIG_CMD_BMODE
Stefano Babic8be4f402016-06-06 11:19:42 +020062#undef CONFIG_CMD_IMLS
63
64#define CONFIG_BOARD_NAME EL6Q
65
66#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
67#define CONFIG_EXTRA_ENV_SETTINGS \
68 "board="__stringify(CONFIG_BOARD_NAME)"\0" \
69 "cma_size="__stringify(EL6Q_CMA_SIZE)"\0" \
70 "chp_size="__stringify(EL6Q_COHERENT_POOL_SIZE)"\0" \
Simon Glass12ca05a2016-10-17 20:12:39 -060071 "console=" CONSOLE_DEV "\0" \
Stefano Babic8be4f402016-06-06 11:19:42 +020072 "fdtfile=undefined\0" \
73 "fdt_high=0xffffffff\0" \
74 "fdt_addr_r=0x18000000\0" \
75 "fdt_addr=0x18000000\0" \
76 "findfdt=setenv fdtfile " CONFIG_DEFAULT_FDT_FILE "\0" \
77 "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
78 "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
79 "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
80 BOOTENV
81
82#define BOOT_TARGET_DEVICES(func) \
83 func(MMC, mmc, 0) \
84 func(MMC, mmc, 1) \
85 func(PXE, PXE, na) \
86 func(DHCP, dhcp, na)
87
88#define CONFIG_BOOTCOMMAND \
89 "run findfdt; " \
90 "run distro_bootcmd"
91
92#include <config_distro_bootcmd.h>
93
94#define CONFIG_ARP_TIMEOUT 200UL
95
96#define CONFIG_CMD_MEMTEST
97
98#define CONFIG_SYS_MEMTEST_START 0x10000000
99#define CONFIG_SYS_MEMTEST_END 0x10800000
100#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
101
102#define CONFIG_STACKSIZE (128 * 1024)
103
104/* Physical Memory Map */
105#define CONFIG_NR_DRAM_BANKS 1
106#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
107
108#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
109#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
110#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
111
112#define CONFIG_SYS_INIT_SP_OFFSET \
113 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
114#define CONFIG_SYS_INIT_SP_ADDR \
115 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
116
Masahiro Yamadae856bdc2017-02-11 22:43:54 +0900117/* environment organization */
Stefano Babic8be4f402016-06-06 11:19:42 +0200118
119#define CONFIG_ENV_SIZE (8 * 1024)
120
121#define CONFIG_ENV_IS_IN_MMC
122
123#if defined(CONFIG_ENV_IS_IN_MMC)
124#define CONFIG_SYS_MMC_ENV_DEV 1
125#define CONFIG_SYS_MMC_ENV_PART 2
126#define CONFIG_ENV_OFFSET 0x0
127#endif
128
129#endif /* __EL6Q_COMMON_CONFIG_H */