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wdenkfe8c2802002-11-03 00:38:21 +00001/*------------------------------------------------------------------------
2 . smc91111.c
3 . This is a driver for SMSC's 91C111 single-chip Ethernet device.
4 .
5 . (C) Copyright 2002
6 . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 . Rolf Offermanns <rof@sysgo.de>
8 .
9 . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
10 . Developed by Simple Network Magic Corporation (SNMC)
11 . Copyright (C) 1996 by Erik Stahlman (ES)
12 .
13 . This program is free software; you can redistribute it and/or modify
14 . it under the terms of the GNU General Public License as published by
15 . the Free Software Foundation; either version 2 of the License, or
16 . (at your option) any later version.
17 .
18 . This program is distributed in the hope that it will be useful,
19 . but WITHOUT ANY WARRANTY; without even the implied warranty of
20 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 . GNU General Public License for more details.
22 .
23 . You should have received a copy of the GNU General Public License
24 . along with this program; if not, write to the Free Software
25 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 .
27 . Information contained in this file was obtained from the LAN91C111
28 . manual from SMC. To get a copy, if you really want one, you can find
29 . information under www.smsc.com.
30 .
31 .
32 . "Features" of the SMC chip:
33 . Integrated PHY/MAC for 10/100BaseT Operation
34 . Supports internal and external MII
35 . Integrated 8K packet memory
36 . EEPROM interface for configuration
37 .
38 . Arguments:
39 . io = for the base address
40 . irq = for the IRQ
41 .
42 . author:
43 . Erik Stahlman ( erik@vt.edu )
44 . Daris A Nevil ( dnevil@snmc.com )
45 .
46 .
47 . Hardware multicast code from Peter Cammaert ( pc@denkart.be )
48 .
49 . Sources:
50 . o SMSC LAN91C111 databook (www.smsc.com)
51 . o smc9194.c by Erik Stahlman
52 . o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov )
53 .
54 . History:
wdenk8bde7f72003-06-27 21:31:46 +000055 . 06/19/03 Richard Woodruff Made u-boot environment aware and added mac addr checks.
wdenkfe8c2802002-11-03 00:38:21 +000056 . 10/17/01 Marco Hasewinkel Modify for DNP/1110
57 . 07/25/01 Woojung Huh Modify for ADS Bitsy
58 . 04/25/01 Daris A Nevil Initial public release through SMSC
59 . 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111
60 ----------------------------------------------------------------------------*/
61
62#include <common.h>
63#include <command.h>
64#include "smc91111.h"
65#include <net.h>
66
67#ifdef CONFIG_DRIVER_SMC91111
68
69/* Use power-down feature of the chip */
70#define POWER_DOWN 0
71
72#define NO_AUTOPROBE
73
wdenk8bf3b002003-12-06 23:20:41 +000074#define SMC_DEBUG 0
75
76#if SMC_DEBUG > 1
wdenkfe8c2802002-11-03 00:38:21 +000077static const char version[] =
78 "smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n";
wdenk8bf3b002003-12-06 23:20:41 +000079#endif
wdenkfe8c2802002-11-03 00:38:21 +000080
81/*------------------------------------------------------------------------
82 .
83 . Configuration options, for the experienced user to change.
84 .
85 -------------------------------------------------------------------------*/
86
87/*
88 . Wait time for memory to be free. This probably shouldn't be
89 . tuned that much, as waiting for this means nothing else happens
90 . in the system
91*/
92#define MEMORY_WAIT_TIME 16
93
94
95#if (SMC_DEBUG > 2 )
96#define PRINTK3(args...) printf(args)
97#else
98#define PRINTK3(args...)
99#endif
100
101#if SMC_DEBUG > 1
102#define PRINTK2(args...) printf(args)
103#else
104#define PRINTK2(args...)
105#endif
106
107#ifdef SMC_DEBUG
108#define PRINTK(args...) printf(args)
109#else
110#define PRINTK(args...)
111#endif
112
113
114/*------------------------------------------------------------------------
115 .
116 . The internal workings of the driver. If you are changing anything
117 . here with the SMC stuff, you should have the datasheet and know
118 . what you are doing.
119 .
120 -------------------------------------------------------------------------*/
121#define CARDNAME "LAN91C111"
122
123/* Memory sizing constant */
124#define LAN91C111_MEMORY_MULTIPLIER (1024*2)
125
126#ifndef CONFIG_SMC91111_BASE
127#define CONFIG_SMC91111_BASE 0x20000300
128#endif
129
130#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE
131
132#define SMC_DEV_NAME "SMC91111"
133#define SMC_PHY_ADDR 0x0000
134#define SMC_ALLOC_MAX_TRY 5
135#define SMC_TX_TIMEOUT 30
136
137#define SMC_PHY_CLOCK_DELAY 1000
138
139#define ETH_ZLEN 60
140
141#ifdef CONFIG_SMC_USE_32_BIT
142#define USE_32_BIT 1
143#else
144#undef USE_32_BIT
145#endif
146/*-----------------------------------------------------------------
147 .
148 . The driver can be entered at any of the following entry points.
149 .
150 .------------------------------------------------------------------ */
151
152extern int eth_init(bd_t *bd);
153extern void eth_halt(void);
154extern int eth_rx(void);
155extern int eth_send(volatile void *packet, int length);
156
157
wdenkfe8c2802002-11-03 00:38:21 +0000158/*
159 . This is called by register_netdev(). It is responsible for
160 . checking the portlist for the SMC9000 series chipset. If it finds
161 . one, then it will initialize the device, find the hardware information,
162 . and sets up the appropriate device parameters.
163 . NOTE: Interrupts are *OFF* when this procedure is called.
164 .
165 . NB:This shouldn't be static since it is referred to externally.
166*/
167int smc_init(void);
168
169/*
170 . This is called by unregister_netdev(). It is responsible for
171 . cleaning up before the driver is finally unregistered and discarded.
172*/
173void smc_destructor(void);
174
175/*
176 . The kernel calls this function when someone wants to use the device,
177 . typically 'ifconfig ethX up'.
178*/
wdenk0b97ab12003-06-19 23:58:30 +0000179static int smc_open(bd_t *bd);
wdenkfe8c2802002-11-03 00:38:21 +0000180
181
182/*
183 . This is called by the kernel in response to 'ifconfig ethX down'. It
184 . is responsible for cleaning up everything that the open routine
185 . does, and maybe putting the card into a powerdown state.
186*/
187static int smc_close(void);
188
189/*
190 . Configures the PHY through the MII Management interface
191*/
192#ifndef CONFIG_SMC91111_EXT_PHY
193static void smc_phy_configure(void);
194#endif /* !CONFIG_SMC91111_EXT_PHY */
195
196/*
197 . This is a separate procedure to handle the receipt of a packet, to
198 . leave the interrupt code looking slightly cleaner
199*/
200static int smc_rcv(void);
201
wdenk0b97ab12003-06-19 23:58:30 +0000202/* See if a MAC address is defined in the current environment. If so use it. If not
wdenk8bde7f72003-06-27 21:31:46 +0000203 . print a warning and set the environment and other globals with the default.
wdenk0b97ab12003-06-19 23:58:30 +0000204 . If an EEPROM is present it really should be consulted.
205*/
206int smc_get_ethaddr(bd_t *bd);
207int get_rom_mac(char *v_rom_mac);
wdenkfe8c2802002-11-03 00:38:21 +0000208
209/*
210 ------------------------------------------------------------
211 .
212 . Internal routines
213 .
214 ------------------------------------------------------------
215*/
216
wdenk8bf3b002003-12-06 23:20:41 +0000217static char unsigned smc_mac_addr[6] = {0x02, 0x80, 0xad, 0x20, 0x31, 0xb8};
wdenkfe8c2802002-11-03 00:38:21 +0000218
219/*
220 * This function must be called before smc_open() if you want to override
221 * the default mac address.
222 */
223
224void smc_set_mac_addr(const char *addr) {
225 int i;
226
227 for (i=0; i < sizeof(smc_mac_addr); i++){
228 smc_mac_addr[i] = addr[i];
229 }
230}
231
232/*
233 * smc_get_macaddr is no longer used. If you want to override the default
wdenk0b97ab12003-06-19 23:58:30 +0000234 * mac address, call smc_get_mac_addr as a part of the board initialization.
wdenkfe8c2802002-11-03 00:38:21 +0000235 */
236
237#if 0
238void smc_get_macaddr( byte *addr ) {
239 /* MAC ADDRESS AT FLASHBLOCK 1 / OFFSET 0x10 */
wdenk8bde7f72003-06-27 21:31:46 +0000240 unsigned char *dnp1110_mac = (unsigned char *) (0xE8000000 + 0x20010);
wdenkfe8c2802002-11-03 00:38:21 +0000241 int i;
242
243
wdenk8bde7f72003-06-27 21:31:46 +0000244 for (i=0; i<6; i++) {
245 addr[0] = *(dnp1110_mac+0);
246 addr[1] = *(dnp1110_mac+1);
247 addr[2] = *(dnp1110_mac+2);
248 addr[3] = *(dnp1110_mac+3);
249 addr[4] = *(dnp1110_mac+4);
250 addr[5] = *(dnp1110_mac+5);
251 }
wdenkfe8c2802002-11-03 00:38:21 +0000252}
253#endif /* 0 */
254
255/***********************************************
256 * Show available memory *
257 ***********************************************/
258void dump_memory_info(void)
259{
wdenk8bde7f72003-06-27 21:31:46 +0000260 word mem_info;
261 word old_bank;
wdenkfe8c2802002-11-03 00:38:21 +0000262
wdenk8bde7f72003-06-27 21:31:46 +0000263 old_bank = SMC_inw(BANK_SELECT)&0xF;
wdenkfe8c2802002-11-03 00:38:21 +0000264
wdenk8bde7f72003-06-27 21:31:46 +0000265 SMC_SELECT_BANK(0);
266 mem_info = SMC_inw( MIR_REG );
267 PRINTK2("Memory: %4d available\n", (mem_info >> 8)*2048);
wdenkfe8c2802002-11-03 00:38:21 +0000268
wdenk8bde7f72003-06-27 21:31:46 +0000269 SMC_SELECT_BANK(old_bank);
wdenkfe8c2802002-11-03 00:38:21 +0000270}
271/*
272 . A rather simple routine to print out a packet for debugging purposes.
273*/
274#if SMC_DEBUG > 2
275static void print_packet( byte *, int );
276#endif
277
278#define tx_done(dev) 1
279
280
wdenkfe8c2802002-11-03 00:38:21 +0000281/* this does a soft reset on the device */
282static void smc_reset( void );
283
284/* Enable Interrupts, Receive, and Transmit */
285static void smc_enable( void );
286
287/* this puts the device in an inactive state */
288static void smc_shutdown( void );
289
290/* Routines to Read and Write the PHY Registers across the
291 MII Management Interface
292*/
293
294#ifndef CONFIG_SMC91111_EXT_PHY
295static word smc_read_phy_register(byte phyreg);
296static void smc_write_phy_register(byte phyreg, word phydata);
297#endif /* !CONFIG_SMC91111_EXT_PHY */
298
299
wdenkb56ddc62003-09-15 21:14:37 +0000300static int poll4int (byte mask, int timeout)
301{
302 int tmo = get_timer (0) + timeout * CFG_HZ;
303 int is_timeout = 0;
304 word old_bank = SMC_inw (BSR_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000305
wdenkb56ddc62003-09-15 21:14:37 +0000306 PRINTK2 ("Polling...\n");
307 SMC_SELECT_BANK (2);
308 while ((SMC_inw (SMC91111_INT_REG) & mask) == 0) {
309 if (get_timer (0) >= tmo) {
310 is_timeout = 1;
311 break;
312 }
wdenkfe8c2802002-11-03 00:38:21 +0000313 }
wdenkfe8c2802002-11-03 00:38:21 +0000314
wdenkb56ddc62003-09-15 21:14:37 +0000315 /* restore old bank selection */
316 SMC_SELECT_BANK (old_bank);
wdenkfe8c2802002-11-03 00:38:21 +0000317
wdenkb56ddc62003-09-15 21:14:37 +0000318 if (is_timeout)
319 return 1;
320 else
321 return 0;
wdenkfe8c2802002-11-03 00:38:21 +0000322}
323
wdenk487778b2003-06-06 11:20:01 +0000324/* Only one release command at a time, please */
wdenkb56ddc62003-09-15 21:14:37 +0000325static inline void smc_wait_mmu_release_complete (void)
wdenk487778b2003-06-06 11:20:01 +0000326{
327 int count = 0;
wdenkb56ddc62003-09-15 21:14:37 +0000328
wdenk487778b2003-06-06 11:20:01 +0000329 /* assume bank 2 selected */
wdenkb56ddc62003-09-15 21:14:37 +0000330 while (SMC_inw (MMU_CMD_REG) & MC_BUSY) {
331 udelay (1); /* Wait until not busy */
332 if (++count > 200)
333 break;
wdenk487778b2003-06-06 11:20:01 +0000334 }
335}
336
wdenkfe8c2802002-11-03 00:38:21 +0000337/*
338 . Function: smc_reset( void )
339 . Purpose:
340 . This sets the SMC91111 chip to its normal state, hopefully from whatever
341 . mess that any other DOS driver has put it in.
342 .
343 . Maybe I should reset more registers to defaults in here? SOFTRST should
344 . do that for me.
345 .
346 . Method:
347 . 1. send a SOFT RESET
348 . 2. wait for it to finish
349 . 3. enable autorelease mode
350 . 4. reset the memory management unit
351 . 5. clear all interrupts
352 .
353*/
wdenkb56ddc62003-09-15 21:14:37 +0000354static void smc_reset (void)
wdenkfe8c2802002-11-03 00:38:21 +0000355{
wdenkb56ddc62003-09-15 21:14:37 +0000356 PRINTK2 ("%s:smc_reset\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000357
358 /* This resets the registers mostly to defaults, but doesn't
359 affect EEPROM. That seems unnecessary */
wdenkb56ddc62003-09-15 21:14:37 +0000360 SMC_SELECT_BANK (0);
361 SMC_outw (RCR_SOFTRST, RCR_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000362
363 /* Setup the Configuration Register */
364 /* This is necessary because the CONFIG_REG is not affected */
365 /* by a soft reset */
366
wdenkb56ddc62003-09-15 21:14:37 +0000367 SMC_SELECT_BANK (1);
wdenkfe8c2802002-11-03 00:38:21 +0000368#if defined(CONFIG_SMC91111_EXT_PHY)
wdenkb56ddc62003-09-15 21:14:37 +0000369 SMC_outw (CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000370#else
wdenkb56ddc62003-09-15 21:14:37 +0000371 SMC_outw (CONFIG_DEFAULT, CONFIG_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000372#endif
373
374
375 /* Release from possible power-down state */
376 /* Configuration register is not affected by Soft Reset */
wdenkb56ddc62003-09-15 21:14:37 +0000377 SMC_outw (SMC_inw (CONFIG_REG) | CONFIG_EPH_POWER_EN, CONFIG_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000378
wdenkb56ddc62003-09-15 21:14:37 +0000379 SMC_SELECT_BANK (0);
wdenkfe8c2802002-11-03 00:38:21 +0000380
381 /* this should pause enough for the chip to be happy */
wdenkb56ddc62003-09-15 21:14:37 +0000382 udelay (10);
wdenkfe8c2802002-11-03 00:38:21 +0000383
384 /* Disable transmit and receive functionality */
wdenkb56ddc62003-09-15 21:14:37 +0000385 SMC_outw (RCR_CLEAR, RCR_REG);
386 SMC_outw (TCR_CLEAR, TCR_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000387
388 /* set the control register */
wdenkb56ddc62003-09-15 21:14:37 +0000389 SMC_SELECT_BANK (1);
390 SMC_outw (CTL_DEFAULT, CTL_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000391
392 /* Reset the MMU */
wdenkb56ddc62003-09-15 21:14:37 +0000393 SMC_SELECT_BANK (2);
394 smc_wait_mmu_release_complete ();
395 SMC_outw (MC_RESET, MMU_CMD_REG);
396 while (SMC_inw (MMU_CMD_REG) & MC_BUSY)
397 udelay (1); /* Wait until not busy */
wdenkfe8c2802002-11-03 00:38:21 +0000398
399 /* Note: It doesn't seem that waiting for the MMU busy is needed here,
400 but this is a place where future chipsets _COULD_ break. Be wary
wdenk8bde7f72003-06-27 21:31:46 +0000401 of issuing another MMU command right after this */
wdenkfe8c2802002-11-03 00:38:21 +0000402
403 /* Disable all interrupts */
wdenkb56ddc62003-09-15 21:14:37 +0000404 SMC_outb (0, IM_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000405}
406
407/*
408 . Function: smc_enable
409 . Purpose: let the chip talk to the outside work
410 . Method:
411 . 1. Enable the transmitter
412 . 2. Enable the receiver
413 . 3. Enable interrupts
414*/
415static void smc_enable()
416{
417 PRINTK2("%s:smc_enable\n", SMC_DEV_NAME);
418 SMC_SELECT_BANK( 0 );
419 /* see the header file for options in TCR/RCR DEFAULT*/
420 SMC_outw( TCR_DEFAULT, TCR_REG );
421 SMC_outw( RCR_DEFAULT, RCR_REG );
422
423 /* clear MII_DIS */
424/* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */
425}
426
427/*
428 . Function: smc_shutdown
429 . Purpose: closes down the SMC91xxx chip.
430 . Method:
431 . 1. zero the interrupt mask
432 . 2. clear the enable receive flag
433 . 3. clear the enable xmit flags
434 .
435 . TODO:
436 . (1) maybe utilize power down mode.
437 . Why not yet? Because while the chip will go into power down mode,
438 . the manual says that it will wake up in response to any I/O requests
439 . in the register space. Empirical results do not show this working.
440*/
441static void smc_shutdown()
442{
443 PRINTK2(CARDNAME ":smc_shutdown\n");
444
445 /* no more interrupts for me */
446 SMC_SELECT_BANK( 2 );
447 SMC_outb( 0, IM_REG );
448
449 /* and tell the card to stay away from that nasty outside world */
450 SMC_SELECT_BANK( 0 );
451 SMC_outb( RCR_CLEAR, RCR_REG );
452 SMC_outb( TCR_CLEAR, TCR_REG );
453}
454
455
456/*
457 . Function: smc_hardware_send_packet(struct net_device * )
458 . Purpose:
459 . This sends the actual packet to the SMC9xxx chip.
460 .
461 . Algorithm:
462 . First, see if a saved_skb is available.
463 . ( this should NOT be called if there is no 'saved_skb'
464 . Now, find the packet number that the chip allocated
465 . Point the data pointers at it in memory
466 . Set the length word in the chip's memory
467 . Dump the packet to chip memory
468 . Check if a last byte is needed ( odd length packet )
469 . if so, set the control flag right
470 . Tell the card to send it
471 . Enable the transmit interrupt, so I know if it failed
472 . Free the kernel data if I actually sent it.
473*/
wdenkb56ddc62003-09-15 21:14:37 +0000474static int smc_send_packet (volatile void *packet, int packet_length)
wdenkfe8c2802002-11-03 00:38:21 +0000475{
wdenkb56ddc62003-09-15 21:14:37 +0000476 byte packet_no;
477 unsigned long ioaddr;
478 byte *buf;
479 int length;
480 int numPages;
481 int try = 0;
482 int time_out;
483 byte status;
wdenkfe8c2802002-11-03 00:38:21 +0000484
485
wdenkb56ddc62003-09-15 21:14:37 +0000486 PRINTK3 ("%s:smc_hardware_send_packet\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000487
488 length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN;
489
490 /* allocate memory
wdenkb56ddc62003-09-15 21:14:37 +0000491 ** The MMU wants the number of pages to be the number of 256 bytes
492 ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
493 **
494 ** The 91C111 ignores the size bits, but the code is left intact
495 ** for backwards and future compatibility.
496 **
497 ** Pkt size for allocating is data length +6 (for additional status
498 ** words, length and ctl!)
499 **
500 ** If odd size then last byte is included in this header.
501 */
502 numPages = ((length & 0xfffe) + 6);
503 numPages >>= 8; /* Divide by 256 */
wdenkfe8c2802002-11-03 00:38:21 +0000504
wdenkb56ddc62003-09-15 21:14:37 +0000505 if (numPages > 7) {
506 printf ("%s: Far too big packet error. \n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000507 return 0;
508 }
509
510 /* now, try to allocate the memory */
wdenkb56ddc62003-09-15 21:14:37 +0000511 SMC_SELECT_BANK (2);
512 SMC_outw (MC_ALLOC | numPages, MMU_CMD_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000513
wdenkdc7c9a12003-03-26 06:55:25 +0000514 /* FIXME: the ALLOC_INT bit never gets set *
515 * so the following will always give a *
516 * memory allocation error. *
517 * same code works in armboot though *
518 * -ro
519 */
520
wdenkfe8c2802002-11-03 00:38:21 +0000521again:
522 try++;
523 time_out = MEMORY_WAIT_TIME;
524 do {
wdenkb56ddc62003-09-15 21:14:37 +0000525 status = SMC_inb (SMC91111_INT_REG);
526 if (status & IM_ALLOC_INT) {
wdenkfe8c2802002-11-03 00:38:21 +0000527 /* acknowledge the interrupt */
wdenkb56ddc62003-09-15 21:14:37 +0000528 SMC_outb (IM_ALLOC_INT, SMC91111_INT_REG);
wdenk8bde7f72003-06-27 21:31:46 +0000529 break;
wdenkfe8c2802002-11-03 00:38:21 +0000530 }
wdenkb56ddc62003-09-15 21:14:37 +0000531 } while (--time_out);
wdenkfe8c2802002-11-03 00:38:21 +0000532
wdenkb56ddc62003-09-15 21:14:37 +0000533 if (!time_out) {
534 PRINTK2 ("%s: memory allocation, try %d failed ...\n",
535 SMC_DEV_NAME, try);
536 if (try < SMC_ALLOC_MAX_TRY)
537 goto again;
538 else
539 return 0;
wdenkfe8c2802002-11-03 00:38:21 +0000540 }
541
wdenkb56ddc62003-09-15 21:14:37 +0000542 PRINTK2 ("%s: memory allocation, try %d succeeded ...\n",
543 SMC_DEV_NAME, try);
wdenkfe8c2802002-11-03 00:38:21 +0000544
545 /* I can send the packet now.. */
546
547 ioaddr = SMC_BASE_ADDRESS;
548
wdenkb56ddc62003-09-15 21:14:37 +0000549 buf = (byte *) packet;
wdenkfe8c2802002-11-03 00:38:21 +0000550
551 /* If I get here, I _know_ there is a packet slot waiting for me */
wdenkb56ddc62003-09-15 21:14:37 +0000552 packet_no = SMC_inb (AR_REG);
553 if (packet_no & AR_FAILED) {
wdenkfe8c2802002-11-03 00:38:21 +0000554 /* or isn't there? BAD CHIP! */
wdenkb56ddc62003-09-15 21:14:37 +0000555 printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000556 return 0;
557 }
558
559 /* we have a packet address, so tell the card to use it */
wdenkb56ddc62003-09-15 21:14:37 +0000560 SMC_outb (packet_no, PN_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000561
562 /* point to the beginning of the packet */
wdenkb56ddc62003-09-15 21:14:37 +0000563 SMC_outw (PTR_AUTOINC, PTR_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000564
wdenkb56ddc62003-09-15 21:14:37 +0000565 PRINTK3 ("%s: Trying to xmit packet of length %x\n",
566 SMC_DEV_NAME, length);
wdenkfe8c2802002-11-03 00:38:21 +0000567
568#if SMC_DEBUG > 2
wdenkb56ddc62003-09-15 21:14:37 +0000569 printf ("Transmitting Packet\n");
570 print_packet (buf, length);
wdenkfe8c2802002-11-03 00:38:21 +0000571#endif
572
573 /* send the packet length ( +6 for status, length and ctl byte )
wdenk8bde7f72003-06-27 21:31:46 +0000574 and the status word ( set to zeros ) */
wdenkfe8c2802002-11-03 00:38:21 +0000575#ifdef USE_32_BIT
wdenkb56ddc62003-09-15 21:14:37 +0000576 SMC_outl ((length + 6) << 16, SMC91111_DATA_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000577#else
wdenkb56ddc62003-09-15 21:14:37 +0000578 SMC_outw (0, SMC91111_DATA_REG);
579 /* send the packet length ( +6 for status words, length, and ctl */
580 SMC_outw ((length + 6), SMC91111_DATA_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000581#endif
582
583 /* send the actual data
wdenkb56ddc62003-09-15 21:14:37 +0000584 . I _think_ it's faster to send the longs first, and then
585 . mop up by sending the last word. It depends heavily
586 . on alignment, at least on the 486. Maybe it would be
587 . a good idea to check which is optimal? But that could take
588 . almost as much time as is saved?
589 */
wdenkfe8c2802002-11-03 00:38:21 +0000590#ifdef USE_32_BIT
wdenkb56ddc62003-09-15 21:14:37 +0000591 SMC_outsl (SMC91111_DATA_REG, buf, length >> 2);
592 if (length & 0x2)
593 SMC_outw (*((word *) (buf + (length & 0xFFFFFFFC))),
594 SMC91111_DATA_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000595#else
wdenkb56ddc62003-09-15 21:14:37 +0000596 SMC_outsw (SMC91111_DATA_REG, buf, (length) >> 1);
wdenkfe8c2802002-11-03 00:38:21 +0000597#endif /* USE_32_BIT */
598
599 /* Send the last byte, if there is one. */
wdenkb56ddc62003-09-15 21:14:37 +0000600 if ((length & 1) == 0) {
601 SMC_outw (0, SMC91111_DATA_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000602 } else {
wdenkb56ddc62003-09-15 21:14:37 +0000603 SMC_outw (buf[length - 1] | 0x2000, SMC91111_DATA_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000604 }
605
606 /* and let the chipset deal with it */
wdenkb56ddc62003-09-15 21:14:37 +0000607 SMC_outw (MC_ENQUEUE, MMU_CMD_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000608
609 /* poll for TX INT */
wdenkb56ddc62003-09-15 21:14:37 +0000610 if (poll4int (IM_TX_INT, SMC_TX_TIMEOUT)) {
wdenkfe8c2802002-11-03 00:38:21 +0000611 /* sending failed */
wdenkb56ddc62003-09-15 21:14:37 +0000612 PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000613
614 /* release packet */
wdenkb56ddc62003-09-15 21:14:37 +0000615 SMC_outw (MC_FREEPKT, MMU_CMD_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000616
wdenk8bde7f72003-06-27 21:31:46 +0000617 /* wait for MMU getting ready (low) */
wdenkb56ddc62003-09-15 21:14:37 +0000618 while (SMC_inw (MMU_CMD_REG) & MC_BUSY) {
619 udelay (10);
wdenk8bde7f72003-06-27 21:31:46 +0000620 }
wdenkfe8c2802002-11-03 00:38:21 +0000621
wdenkb56ddc62003-09-15 21:14:37 +0000622 PRINTK2 ("MMU ready\n");
wdenkfe8c2802002-11-03 00:38:21 +0000623
624
625 return 0;
626 } else {
627 /* ack. int */
wdenk8bf3b002003-12-06 23:20:41 +0000628 SMC_outb (IM_TX_INT, SMC91111_INT_REG);
wdenkb56ddc62003-09-15 21:14:37 +0000629 PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME,
630 length);
wdenkfe8c2802002-11-03 00:38:21 +0000631
632 /* release packet */
wdenkb56ddc62003-09-15 21:14:37 +0000633 SMC_outw (MC_FREEPKT, MMU_CMD_REG);
wdenkfe8c2802002-11-03 00:38:21 +0000634
wdenk8bde7f72003-06-27 21:31:46 +0000635 /* wait for MMU getting ready (low) */
wdenkb56ddc62003-09-15 21:14:37 +0000636 while (SMC_inw (MMU_CMD_REG) & MC_BUSY) {
637 udelay (10);
wdenk8bde7f72003-06-27 21:31:46 +0000638 }
wdenkfe8c2802002-11-03 00:38:21 +0000639
wdenkb56ddc62003-09-15 21:14:37 +0000640 PRINTK2 ("MMU ready\n");
wdenkfe8c2802002-11-03 00:38:21 +0000641
642
643 }
644
645 return length;
646}
647
648/*-------------------------------------------------------------------------
649 |
650 | smc_destructor( struct net_device * dev )
651 | Input parameters:
652 | dev, pointer to the device structure
653 |
654 | Output:
655 | None.
656 |
657 ---------------------------------------------------------------------------
658*/
659void smc_destructor()
660{
661 PRINTK2(CARDNAME ":smc_destructor\n");
662}
663
664
665/*
666 * Open and Initialize the board
667 *
668 * Set up everything, reset the card, etc ..
669 *
670 */
wdenkb56ddc62003-09-15 21:14:37 +0000671static int smc_open (bd_t * bd)
wdenkfe8c2802002-11-03 00:38:21 +0000672{
wdenkb56ddc62003-09-15 21:14:37 +0000673 int i, err;
wdenkfe8c2802002-11-03 00:38:21 +0000674
wdenkb56ddc62003-09-15 21:14:37 +0000675 PRINTK2 ("%s:smc_open\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +0000676
677 /* reset the hardware */
wdenkb56ddc62003-09-15 21:14:37 +0000678 smc_reset ();
679 smc_enable ();
wdenkfe8c2802002-11-03 00:38:21 +0000680
681 /* Configure the PHY */
682#ifndef CONFIG_SMC91111_EXT_PHY
wdenkb56ddc62003-09-15 21:14:37 +0000683 smc_phy_configure ();
wdenkfe8c2802002-11-03 00:38:21 +0000684#endif
685
wdenkfe8c2802002-11-03 00:38:21 +0000686 /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */
687/* SMC_SELECT_BANK(0); */
688/* SMC_outw(0, RPC_REG); */
wdenkb56ddc62003-09-15 21:14:37 +0000689 SMC_SELECT_BANK (1);
wdenk8bde7f72003-06-27 21:31:46 +0000690
wdenkb56ddc62003-09-15 21:14:37 +0000691 err = smc_get_ethaddr (bd); /* set smc_mac_addr, and sync it with u-boot globals */
692 if (err < 0) {
693 memset (bd->bi_enetaddr, 0, 6); /* hack to make error stick! upper code will abort if not set */
694 return (-1); /* upper code ignores this, but NOT bi_enetaddr */
695 }
wdenkfe8c2802002-11-03 00:38:21 +0000696#ifdef USE_32_BIT
wdenkb56ddc62003-09-15 21:14:37 +0000697 for (i = 0; i < 6; i += 2) {
wdenkfe8c2802002-11-03 00:38:21 +0000698 word address;
699
wdenkb56ddc62003-09-15 21:14:37 +0000700 address = smc_mac_addr[i + 1] << 8;
701 address |= smc_mac_addr[i];
702 SMC_outw (address, ADDR0_REG + i);
wdenkfe8c2802002-11-03 00:38:21 +0000703 }
704#else
wdenkb56ddc62003-09-15 21:14:37 +0000705 for (i = 0; i < 6; i++)
706 SMC_outb (smc_mac_addr[i], ADDR0_REG + i);
wdenkfe8c2802002-11-03 00:38:21 +0000707#endif
708
709 return 0;
710}
711
wdenkfe8c2802002-11-03 00:38:21 +0000712/*-------------------------------------------------------------
713 .
714 . smc_rcv - receive a packet from the card
715 .
716 . There is ( at least ) a packet waiting to be read from
717 . chip-memory.
718 .
719 . o Read the status
720 . o If an error, record it
721 . o otherwise, read in the packet
722 --------------------------------------------------------------
723*/
724static int smc_rcv()
725{
726 int packet_number;
727 word status;
728 word packet_length;
729 int is_error = 0;
730#ifdef USE_32_BIT
731 dword stat_len;
732#endif
733
wdenkfe8c2802002-11-03 00:38:21 +0000734 SMC_SELECT_BANK(2);
735 packet_number = SMC_inw( RXFIFO_REG );
736
737 if ( packet_number & RXFIFO_REMPTY ) {
738
739 return 0;
740 }
741
742 PRINTK3("%s:smc_rcv\n", SMC_DEV_NAME);
743 /* start reading from the start of the packet */
744 SMC_outw( PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG );
745
746 /* First two words are status and packet_length */
747#ifdef USE_32_BIT
748 stat_len = SMC_inl(SMC91111_DATA_REG);
749 status = stat_len & 0xffff;
750 packet_length = stat_len >> 16;
751#else
752 status = SMC_inw( SMC91111_DATA_REG );
753 packet_length = SMC_inw( SMC91111_DATA_REG );
754#endif
755
756 packet_length &= 0x07ff; /* mask off top bits */
757
758 PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status, packet_length );
759
760 if ( !(status & RS_ERRORS ) ){
761 /* Adjust for having already read the first two words */
762 packet_length -= 4; /*4; */
763
764
wdenkfe8c2802002-11-03 00:38:21 +0000765 /* set odd length for bug in LAN91C111, */
766 /* which never sets RS_ODDFRAME */
767 /* TODO ? */
768
769
770#ifdef USE_32_BIT
771 PRINTK3(" Reading %d dwords (and %d bytes) \n",
772 packet_length >> 2, packet_length & 3 );
773 /* QUESTION: Like in the TX routine, do I want
774 to send the DWORDs or the bytes first, or some
775 mixture. A mixture might improve already slow PIO
776 performance */
777 SMC_insl( SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 2 );
778 /* read the left over bytes */
779 if (packet_length & 3) {
780 int i;
781
wdenk699b13a2002-11-03 18:03:52 +0000782 byte *tail = (byte *)(NetRxPackets[0] + (packet_length & ~3));
wdenkfe8c2802002-11-03 00:38:21 +0000783 dword leftover = SMC_inl(SMC91111_DATA_REG);
784 for (i=0; i<(packet_length & 3); i++)
785 *tail++ = (byte) (leftover >> (8*i)) & 0xff;
786 }
787#else
788 PRINTK3(" Reading %d words and %d byte(s) \n",
789 (packet_length >> 1 ), packet_length & 1 );
790 SMC_insw(SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 1);
791
792#endif /* USE_32_BIT */
793
794#if SMC_DEBUG > 2
795 printf("Receiving Packet\n");
796 print_packet( NetRxPackets[0], packet_length );
797#endif
798 } else {
799 /* error ... */
800 /* TODO ? */
801 is_error = 1;
802 }
803
804 while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY )
805 udelay(1); /* Wait until not busy */
806
807 /* error or good, tell the card to get rid of this packet */
808 SMC_outw( MC_RELEASE, MMU_CMD_REG );
809
810 while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY )
811 udelay(1); /* Wait until not busy */
812
813 if (!is_error) {
814 /* Pass the packet up to the protocol layers. */
815 NetReceive(NetRxPackets[0], packet_length);
816 return packet_length;
817 } else {
818 return 0;
819 }
820
821}
822
823
wdenkfe8c2802002-11-03 00:38:21 +0000824/*----------------------------------------------------
825 . smc_close
826 .
827 . this makes the board clean up everything that it can
828 . and not talk to the outside world. Caused by
829 . an 'ifconfig ethX down'
830 .
831 -----------------------------------------------------*/
832static int smc_close()
833{
834 PRINTK2("%s:smc_close\n", SMC_DEV_NAME);
835
836 /* clear everything */
837 smc_shutdown();
838
839 return 0;
840}
841
842
843#if 0
844/*------------------------------------------------------------
845 . Modify a bit in the LAN91C111 register set
846 .-------------------------------------------------------------*/
847static word smc_modify_regbit(int bank, int ioaddr, int reg,
848 unsigned int bit, int val)
849{
850 word regval;
851
852 SMC_SELECT_BANK( bank );
853
854 regval = SMC_inw( reg );
855 if (val)
856 regval |= bit;
857 else
858 regval &= ~bit;
859
860 SMC_outw( regval, 0 );
861 return(regval);
862}
863
864
865/*------------------------------------------------------------
866 . Retrieve a bit in the LAN91C111 register set
867 .-------------------------------------------------------------*/
868static int smc_get_regbit(int bank, int ioaddr, int reg, unsigned int bit)
869{
870 SMC_SELECT_BANK( bank );
871 if ( SMC_inw( reg ) & bit)
872 return(1);
873 else
874 return(0);
875}
876
877
878/*------------------------------------------------------------
879 . Modify a LAN91C111 register (word access only)
880 .-------------------------------------------------------------*/
881static void smc_modify_reg(int bank, int ioaddr, int reg, word val)
882{
883 SMC_SELECT_BANK( bank );
884 SMC_outw( val, reg );
885}
886
887
888/*------------------------------------------------------------
889 . Retrieve a LAN91C111 register (word access only)
890 .-------------------------------------------------------------*/
891static int smc_get_reg(int bank, int ioaddr, int reg)
892{
893 SMC_SELECT_BANK( bank );
894 return(SMC_inw( reg ));
895}
896
897#endif /* 0 */
898
899/*---PHY CONTROL AND CONFIGURATION----------------------------------------- */
900
901#if (SMC_DEBUG > 2 )
902
903/*------------------------------------------------------------
904 . Debugging function for viewing MII Management serial bitstream
905 .-------------------------------------------------------------*/
wdenkb56ddc62003-09-15 21:14:37 +0000906static void smc_dump_mii_stream (byte * bits, int size)
wdenkfe8c2802002-11-03 00:38:21 +0000907{
908 int i;
909
wdenkb56ddc62003-09-15 21:14:37 +0000910 printf ("BIT#:");
911 for (i = 0; i < size; ++i) {
912 printf ("%d", i % 10);
913 }
wdenkfe8c2802002-11-03 00:38:21 +0000914
wdenkb56ddc62003-09-15 21:14:37 +0000915 printf ("\nMDOE:");
916 for (i = 0; i < size; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +0000917 if (bits[i] & MII_MDOE)
wdenkb56ddc62003-09-15 21:14:37 +0000918 printf ("1");
wdenkfe8c2802002-11-03 00:38:21 +0000919 else
wdenkb56ddc62003-09-15 21:14:37 +0000920 printf ("0");
921 }
wdenkfe8c2802002-11-03 00:38:21 +0000922
wdenkb56ddc62003-09-15 21:14:37 +0000923 printf ("\nMDO :");
924 for (i = 0; i < size; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +0000925 if (bits[i] & MII_MDO)
wdenkb56ddc62003-09-15 21:14:37 +0000926 printf ("1");
wdenkfe8c2802002-11-03 00:38:21 +0000927 else
wdenkb56ddc62003-09-15 21:14:37 +0000928 printf ("0");
929 }
wdenkfe8c2802002-11-03 00:38:21 +0000930
wdenkb56ddc62003-09-15 21:14:37 +0000931 printf ("\nMDI :");
932 for (i = 0; i < size; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +0000933 if (bits[i] & MII_MDI)
wdenkb56ddc62003-09-15 21:14:37 +0000934 printf ("1");
wdenkfe8c2802002-11-03 00:38:21 +0000935 else
wdenkb56ddc62003-09-15 21:14:37 +0000936 printf ("0");
937 }
wdenkfe8c2802002-11-03 00:38:21 +0000938
wdenkb56ddc62003-09-15 21:14:37 +0000939 printf ("\n");
wdenkfe8c2802002-11-03 00:38:21 +0000940}
941#endif
942
943/*------------------------------------------------------------
944 . Reads a register from the MII Management serial interface
945 .-------------------------------------------------------------*/
946#ifndef CONFIG_SMC91111_EXT_PHY
wdenkb56ddc62003-09-15 21:14:37 +0000947static word smc_read_phy_register (byte phyreg)
wdenkfe8c2802002-11-03 00:38:21 +0000948{
949 int oldBank;
950 int i;
951 byte mask;
952 word mii_reg;
953 byte bits[64];
954 int clk_idx = 0;
955 int input_idx;
956 word phydata;
957 byte phyaddr = SMC_PHY_ADDR;
958
959 /* 32 consecutive ones on MDO to establish sync */
960 for (i = 0; i < 32; ++i)
961 bits[clk_idx++] = MII_MDOE | MII_MDO;
962
963 /* Start code <01> */
964 bits[clk_idx++] = MII_MDOE;
965 bits[clk_idx++] = MII_MDOE | MII_MDO;
966
967 /* Read command <10> */
968 bits[clk_idx++] = MII_MDOE | MII_MDO;
969 bits[clk_idx++] = MII_MDOE;
970
971 /* Output the PHY address, msb first */
wdenkb56ddc62003-09-15 21:14:37 +0000972 mask = (byte) 0x10;
973 for (i = 0; i < 5; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +0000974 if (phyaddr & mask)
975 bits[clk_idx++] = MII_MDOE | MII_MDO;
976 else
977 bits[clk_idx++] = MII_MDOE;
978
979 /* Shift to next lowest bit */
980 mask >>= 1;
wdenkb56ddc62003-09-15 21:14:37 +0000981 }
wdenkfe8c2802002-11-03 00:38:21 +0000982
983 /* Output the phy register number, msb first */
wdenkb56ddc62003-09-15 21:14:37 +0000984 mask = (byte) 0x10;
985 for (i = 0; i < 5; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +0000986 if (phyreg & mask)
987 bits[clk_idx++] = MII_MDOE | MII_MDO;
988 else
989 bits[clk_idx++] = MII_MDOE;
990
991 /* Shift to next lowest bit */
992 mask >>= 1;
wdenkb56ddc62003-09-15 21:14:37 +0000993 }
wdenkfe8c2802002-11-03 00:38:21 +0000994
995 /* Tristate and turnaround (2 bit times) */
996 bits[clk_idx++] = 0;
997 /*bits[clk_idx++] = 0; */
998
999 /* Input starts at this bit time */
1000 input_idx = clk_idx;
1001
1002 /* Will input 16 bits */
1003 for (i = 0; i < 16; ++i)
1004 bits[clk_idx++] = 0;
1005
1006 /* Final clock bit */
1007 bits[clk_idx++] = 0;
1008
1009 /* Save the current bank */
wdenkb56ddc62003-09-15 21:14:37 +00001010 oldBank = SMC_inw (BANK_SELECT);
wdenkfe8c2802002-11-03 00:38:21 +00001011
1012 /* Select bank 3 */
wdenkb56ddc62003-09-15 21:14:37 +00001013 SMC_SELECT_BANK (3);
wdenkfe8c2802002-11-03 00:38:21 +00001014
1015 /* Get the current MII register value */
wdenkb56ddc62003-09-15 21:14:37 +00001016 mii_reg = SMC_inw (MII_REG);
wdenkfe8c2802002-11-03 00:38:21 +00001017
1018 /* Turn off all MII Interface bits */
wdenkb56ddc62003-09-15 21:14:37 +00001019 mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
wdenkfe8c2802002-11-03 00:38:21 +00001020
1021 /* Clock all 64 cycles */
wdenkb56ddc62003-09-15 21:14:37 +00001022 for (i = 0; i < sizeof bits; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +00001023 /* Clock Low - output data */
wdenkb56ddc62003-09-15 21:14:37 +00001024 SMC_outw (mii_reg | bits[i], MII_REG);
1025 udelay (SMC_PHY_CLOCK_DELAY);
wdenkfe8c2802002-11-03 00:38:21 +00001026
1027
1028 /* Clock Hi - input data */
wdenkb56ddc62003-09-15 21:14:37 +00001029 SMC_outw (mii_reg | bits[i] | MII_MCLK, MII_REG);
1030 udelay (SMC_PHY_CLOCK_DELAY);
1031 bits[i] |= SMC_inw (MII_REG) & MII_MDI;
1032 }
wdenkfe8c2802002-11-03 00:38:21 +00001033
1034 /* Return to idle state */
1035 /* Set clock to low, data to low, and output tristated */
wdenkb56ddc62003-09-15 21:14:37 +00001036 SMC_outw (mii_reg, MII_REG);
1037 udelay (SMC_PHY_CLOCK_DELAY);
wdenkfe8c2802002-11-03 00:38:21 +00001038
1039 /* Restore original bank select */
wdenkb56ddc62003-09-15 21:14:37 +00001040 SMC_SELECT_BANK (oldBank);
wdenkfe8c2802002-11-03 00:38:21 +00001041
1042 /* Recover input data */
1043 phydata = 0;
wdenkb56ddc62003-09-15 21:14:37 +00001044 for (i = 0; i < 16; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +00001045 phydata <<= 1;
1046
1047 if (bits[input_idx++] & MII_MDI)
1048 phydata |= 0x0001;
wdenkb56ddc62003-09-15 21:14:37 +00001049 }
wdenkfe8c2802002-11-03 00:38:21 +00001050
1051#if (SMC_DEBUG > 2 )
wdenkb56ddc62003-09-15 21:14:37 +00001052 printf ("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
wdenkfe8c2802002-11-03 00:38:21 +00001053 phyaddr, phyreg, phydata);
wdenkb56ddc62003-09-15 21:14:37 +00001054 smc_dump_mii_stream (bits, sizeof bits);
wdenkfe8c2802002-11-03 00:38:21 +00001055#endif
1056
wdenkb56ddc62003-09-15 21:14:37 +00001057 return (phydata);
wdenkfe8c2802002-11-03 00:38:21 +00001058}
1059
1060
1061/*------------------------------------------------------------
1062 . Writes a register to the MII Management serial interface
1063 .-------------------------------------------------------------*/
wdenkb56ddc62003-09-15 21:14:37 +00001064static void smc_write_phy_register (byte phyreg, word phydata)
wdenkfe8c2802002-11-03 00:38:21 +00001065{
1066 int oldBank;
1067 int i;
1068 word mask;
1069 word mii_reg;
1070 byte bits[65];
1071 int clk_idx = 0;
1072 byte phyaddr = SMC_PHY_ADDR;
1073
1074 /* 32 consecutive ones on MDO to establish sync */
1075 for (i = 0; i < 32; ++i)
1076 bits[clk_idx++] = MII_MDOE | MII_MDO;
1077
1078 /* Start code <01> */
1079 bits[clk_idx++] = MII_MDOE;
1080 bits[clk_idx++] = MII_MDOE | MII_MDO;
1081
1082 /* Write command <01> */
1083 bits[clk_idx++] = MII_MDOE;
1084 bits[clk_idx++] = MII_MDOE | MII_MDO;
1085
1086 /* Output the PHY address, msb first */
wdenkb56ddc62003-09-15 21:14:37 +00001087 mask = (byte) 0x10;
1088 for (i = 0; i < 5; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +00001089 if (phyaddr & mask)
1090 bits[clk_idx++] = MII_MDOE | MII_MDO;
1091 else
1092 bits[clk_idx++] = MII_MDOE;
1093
1094 /* Shift to next lowest bit */
1095 mask >>= 1;
wdenkb56ddc62003-09-15 21:14:37 +00001096 }
wdenkfe8c2802002-11-03 00:38:21 +00001097
1098 /* Output the phy register number, msb first */
wdenkb56ddc62003-09-15 21:14:37 +00001099 mask = (byte) 0x10;
1100 for (i = 0; i < 5; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +00001101 if (phyreg & mask)
1102 bits[clk_idx++] = MII_MDOE | MII_MDO;
1103 else
1104 bits[clk_idx++] = MII_MDOE;
1105
1106 /* Shift to next lowest bit */
1107 mask >>= 1;
wdenkb56ddc62003-09-15 21:14:37 +00001108 }
wdenkfe8c2802002-11-03 00:38:21 +00001109
1110 /* Tristate and turnaround (2 bit times) */
1111 bits[clk_idx++] = 0;
1112 bits[clk_idx++] = 0;
1113
1114 /* Write out 16 bits of data, msb first */
1115 mask = 0x8000;
wdenkb56ddc62003-09-15 21:14:37 +00001116 for (i = 0; i < 16; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +00001117 if (phydata & mask)
1118 bits[clk_idx++] = MII_MDOE | MII_MDO;
1119 else
1120 bits[clk_idx++] = MII_MDOE;
1121
1122 /* Shift to next lowest bit */
1123 mask >>= 1;
wdenkb56ddc62003-09-15 21:14:37 +00001124 }
wdenkfe8c2802002-11-03 00:38:21 +00001125
1126 /* Final clock bit (tristate) */
1127 bits[clk_idx++] = 0;
1128
1129 /* Save the current bank */
wdenkb56ddc62003-09-15 21:14:37 +00001130 oldBank = SMC_inw (BANK_SELECT);
wdenkfe8c2802002-11-03 00:38:21 +00001131
1132 /* Select bank 3 */
wdenkb56ddc62003-09-15 21:14:37 +00001133 SMC_SELECT_BANK (3);
wdenkfe8c2802002-11-03 00:38:21 +00001134
1135 /* Get the current MII register value */
wdenkb56ddc62003-09-15 21:14:37 +00001136 mii_reg = SMC_inw (MII_REG);
wdenkfe8c2802002-11-03 00:38:21 +00001137
1138 /* Turn off all MII Interface bits */
wdenkb56ddc62003-09-15 21:14:37 +00001139 mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
wdenkfe8c2802002-11-03 00:38:21 +00001140
1141 /* Clock all cycles */
wdenkb56ddc62003-09-15 21:14:37 +00001142 for (i = 0; i < sizeof bits; ++i) {
wdenkfe8c2802002-11-03 00:38:21 +00001143 /* Clock Low - output data */
wdenkb56ddc62003-09-15 21:14:37 +00001144 SMC_outw (mii_reg | bits[i], MII_REG);
1145 udelay (SMC_PHY_CLOCK_DELAY);
wdenkfe8c2802002-11-03 00:38:21 +00001146
1147
1148 /* Clock Hi - input data */
wdenkb56ddc62003-09-15 21:14:37 +00001149 SMC_outw (mii_reg | bits[i] | MII_MCLK, MII_REG);
1150 udelay (SMC_PHY_CLOCK_DELAY);
1151 bits[i] |= SMC_inw (MII_REG) & MII_MDI;
1152 }
wdenkfe8c2802002-11-03 00:38:21 +00001153
1154 /* Return to idle state */
1155 /* Set clock to low, data to low, and output tristated */
wdenkb56ddc62003-09-15 21:14:37 +00001156 SMC_outw (mii_reg, MII_REG);
1157 udelay (SMC_PHY_CLOCK_DELAY);
wdenkfe8c2802002-11-03 00:38:21 +00001158
1159 /* Restore original bank select */
wdenkb56ddc62003-09-15 21:14:37 +00001160 SMC_SELECT_BANK (oldBank);
wdenkfe8c2802002-11-03 00:38:21 +00001161
1162#if (SMC_DEBUG > 2 )
wdenkb56ddc62003-09-15 21:14:37 +00001163 printf ("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
wdenkfe8c2802002-11-03 00:38:21 +00001164 phyaddr, phyreg, phydata);
wdenkb56ddc62003-09-15 21:14:37 +00001165 smc_dump_mii_stream (bits, sizeof bits);
wdenkfe8c2802002-11-03 00:38:21 +00001166#endif
1167}
1168#endif /* !CONFIG_SMC91111_EXT_PHY */
1169
1170
wdenkfe8c2802002-11-03 00:38:21 +00001171/*------------------------------------------------------------
1172 . Waits the specified number of milliseconds - kernel friendly
1173 .-------------------------------------------------------------*/
1174#ifndef CONFIG_SMC91111_EXT_PHY
1175static void smc_wait_ms(unsigned int ms)
1176{
1177 udelay(ms*1000);
1178}
1179#endif /* !CONFIG_SMC91111_EXT_PHY */
1180
1181
wdenkfe8c2802002-11-03 00:38:21 +00001182/*------------------------------------------------------------
1183 . Configures the specified PHY using Autonegotiation. Calls
1184 . smc_phy_fixed() if the user has requested a certain config.
1185 .-------------------------------------------------------------*/
1186#ifndef CONFIG_SMC91111_EXT_PHY
wdenkb56ddc62003-09-15 21:14:37 +00001187static void smc_phy_configure ()
wdenkfe8c2802002-11-03 00:38:21 +00001188{
1189 int timeout;
1190 byte phyaddr;
wdenkb56ddc62003-09-15 21:14:37 +00001191 word my_phy_caps; /* My PHY capabilities */
1192 word my_ad_caps; /* My Advertised capabilities */
1193 word status = 0; /*;my status = 0 */
wdenkfe8c2802002-11-03 00:38:21 +00001194 int failed = 0;
1195
wdenkb56ddc62003-09-15 21:14:37 +00001196 PRINTK3 ("%s:smc_program_phy()\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +00001197
1198
wdenkfe8c2802002-11-03 00:38:21 +00001199 /* Get the detected phy address */
1200 phyaddr = SMC_PHY_ADDR;
1201
1202 /* Reset the PHY, setting all other bits to zero */
wdenkb56ddc62003-09-15 21:14:37 +00001203 smc_write_phy_register (PHY_CNTL_REG, PHY_CNTL_RST);
wdenkfe8c2802002-11-03 00:38:21 +00001204
1205 /* Wait for the reset to complete, or time out */
wdenkb56ddc62003-09-15 21:14:37 +00001206 timeout = 6; /* Wait up to 3 seconds */
1207 while (timeout--) {
1208 if (!(smc_read_phy_register (PHY_CNTL_REG)
1209 & PHY_CNTL_RST)) {
wdenkfe8c2802002-11-03 00:38:21 +00001210 /* reset complete */
1211 break;
wdenkfe8c2802002-11-03 00:38:21 +00001212 }
1213
wdenkb56ddc62003-09-15 21:14:37 +00001214 smc_wait_ms (500); /* wait 500 millisecs */
1215 }
1216
1217 if (timeout < 1) {
1218 printf ("%s:PHY reset timed out\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +00001219 goto smc_phy_configure_exit;
wdenkb56ddc62003-09-15 21:14:37 +00001220 }
wdenkfe8c2802002-11-03 00:38:21 +00001221
1222 /* Read PHY Register 18, Status Output */
1223 /* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */
1224
1225 /* Enable PHY Interrupts (for register 18) */
1226 /* Interrupts listed here are disabled */
wdenk8bf3b002003-12-06 23:20:41 +00001227 smc_write_phy_register (PHY_MASK_REG, 0xffff);
wdenkfe8c2802002-11-03 00:38:21 +00001228
1229 /* Configure the Receive/Phy Control register */
wdenkb56ddc62003-09-15 21:14:37 +00001230 SMC_SELECT_BANK (0);
1231 SMC_outw (RPC_DEFAULT, RPC_REG);
wdenkfe8c2802002-11-03 00:38:21 +00001232
1233 /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */
wdenkb56ddc62003-09-15 21:14:37 +00001234 my_phy_caps = smc_read_phy_register (PHY_STAT_REG);
1235 my_ad_caps = PHY_AD_CSMA; /* I am CSMA capable */
wdenkfe8c2802002-11-03 00:38:21 +00001236
1237 if (my_phy_caps & PHY_STAT_CAP_T4)
1238 my_ad_caps |= PHY_AD_T4;
1239
1240 if (my_phy_caps & PHY_STAT_CAP_TXF)
1241 my_ad_caps |= PHY_AD_TX_FDX;
1242
1243 if (my_phy_caps & PHY_STAT_CAP_TXH)
1244 my_ad_caps |= PHY_AD_TX_HDX;
1245
1246 if (my_phy_caps & PHY_STAT_CAP_TF)
1247 my_ad_caps |= PHY_AD_10_FDX;
1248
1249 if (my_phy_caps & PHY_STAT_CAP_TH)
1250 my_ad_caps |= PHY_AD_10_HDX;
1251
1252 /* Update our Auto-Neg Advertisement Register */
wdenkb56ddc62003-09-15 21:14:37 +00001253 smc_write_phy_register (PHY_AD_REG, my_ad_caps);
wdenkfe8c2802002-11-03 00:38:21 +00001254
wdenkb56ddc62003-09-15 21:14:37 +00001255 PRINTK2 ("%s:phy caps=%x\n", SMC_DEV_NAME, my_phy_caps);
1256 PRINTK2 ("%s:phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps);
wdenkfe8c2802002-11-03 00:38:21 +00001257
1258 /* Restart auto-negotiation process in order to advertise my caps */
wdenkb56ddc62003-09-15 21:14:37 +00001259 smc_write_phy_register (PHY_CNTL_REG,
1260 PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST);
wdenkfe8c2802002-11-03 00:38:21 +00001261
1262 /* Wait for the auto-negotiation to complete. This may take from */
1263 /* 2 to 3 seconds. */
1264 /* Wait for the reset to complete, or time out */
wdenkb56ddc62003-09-15 21:14:37 +00001265 timeout = 20; /* Wait up to 10 seconds */
1266 while (timeout--) {
1267 status = smc_read_phy_register (PHY_STAT_REG);
1268 if (status & PHY_STAT_ANEG_ACK) {
wdenkfe8c2802002-11-03 00:38:21 +00001269 /* auto-negotiate complete */
1270 break;
wdenkb56ddc62003-09-15 21:14:37 +00001271 }
wdenkfe8c2802002-11-03 00:38:21 +00001272
wdenkb56ddc62003-09-15 21:14:37 +00001273 smc_wait_ms (500); /* wait 500 millisecs */
wdenkfe8c2802002-11-03 00:38:21 +00001274
1275 /* Restart auto-negotiation if remote fault */
wdenkb56ddc62003-09-15 21:14:37 +00001276 if (status & PHY_STAT_REM_FLT) {
1277 printf ("%s:PHY remote fault detected\n",
1278 SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +00001279
1280 /* Restart auto-negotiation */
wdenkb56ddc62003-09-15 21:14:37 +00001281 printf ("%s:PHY restarting auto-negotiation\n",
wdenkfe8c2802002-11-03 00:38:21 +00001282 SMC_DEV_NAME);
wdenkb56ddc62003-09-15 21:14:37 +00001283 smc_write_phy_register (PHY_CNTL_REG,
1284 PHY_CNTL_ANEG_EN |
1285 PHY_CNTL_ANEG_RST |
1286 PHY_CNTL_SPEED |
1287 PHY_CNTL_DPLX);
wdenkfe8c2802002-11-03 00:38:21 +00001288 }
wdenkb56ddc62003-09-15 21:14:37 +00001289 }
wdenkfe8c2802002-11-03 00:38:21 +00001290
wdenkb56ddc62003-09-15 21:14:37 +00001291 if (timeout < 1) {
1292 printf ("%s:PHY auto-negotiate timed out\n", SMC_DEV_NAME);
1293 printf ("%s:PHY auto-negotiate timed out\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +00001294 failed = 1;
wdenkb56ddc62003-09-15 21:14:37 +00001295 }
wdenkfe8c2802002-11-03 00:38:21 +00001296
1297 /* Fail if we detected an auto-negotiate remote fault */
wdenkb56ddc62003-09-15 21:14:37 +00001298 if (status & PHY_STAT_REM_FLT) {
1299 printf ("%s:PHY remote fault detected\n", SMC_DEV_NAME);
1300 printf ("%s:PHY remote fault detected\n", SMC_DEV_NAME);
wdenkfe8c2802002-11-03 00:38:21 +00001301 failed = 1;
wdenkb56ddc62003-09-15 21:14:37 +00001302 }
wdenkfe8c2802002-11-03 00:38:21 +00001303
1304 /* Re-Configure the Receive/Phy Control register */
wdenkb56ddc62003-09-15 21:14:37 +00001305 SMC_outw (RPC_DEFAULT, RPC_REG);
wdenkfe8c2802002-11-03 00:38:21 +00001306
wdenkb56ddc62003-09-15 21:14:37 +00001307 smc_phy_configure_exit:
wdenkfe8c2802002-11-03 00:38:21 +00001308
1309}
1310#endif /* !CONFIG_SMC91111_EXT_PHY */
1311
1312
1313#if SMC_DEBUG > 2
1314static void print_packet( byte * buf, int length )
1315{
1316#if 0
wdenk8bde7f72003-06-27 21:31:46 +00001317 int i;
1318 int remainder;
1319 int lines;
wdenkfe8c2802002-11-03 00:38:21 +00001320
wdenk8bde7f72003-06-27 21:31:46 +00001321 printf("Packet of length %d \n", length );
wdenkfe8c2802002-11-03 00:38:21 +00001322
1323#if SMC_DEBUG > 3
wdenk8bde7f72003-06-27 21:31:46 +00001324 lines = length / 16;
1325 remainder = length % 16;
wdenkfe8c2802002-11-03 00:38:21 +00001326
wdenk8bde7f72003-06-27 21:31:46 +00001327 for ( i = 0; i < lines ; i ++ ) {
1328 int cur;
wdenkfe8c2802002-11-03 00:38:21 +00001329
wdenk8bde7f72003-06-27 21:31:46 +00001330 for ( cur = 0; cur < 8; cur ++ ) {
1331 byte a, b;
wdenkfe8c2802002-11-03 00:38:21 +00001332
wdenk8bde7f72003-06-27 21:31:46 +00001333 a = *(buf ++ );
1334 b = *(buf ++ );
1335 printf("%02x%02x ", a, b );
1336 }
1337 printf("\n");
1338 }
1339 for ( i = 0; i < remainder/2 ; i++ ) {
1340 byte a, b;
wdenkfe8c2802002-11-03 00:38:21 +00001341
wdenk8bde7f72003-06-27 21:31:46 +00001342 a = *(buf ++ );
1343 b = *(buf ++ );
1344 printf("%02x%02x ", a, b );
1345 }
1346 printf("\n");
wdenkfe8c2802002-11-03 00:38:21 +00001347#endif
1348#endif
1349}
1350#endif
1351
1352int eth_init(bd_t *bd) {
wdenk0b97ab12003-06-19 23:58:30 +00001353 return (smc_open(bd));
wdenkfe8c2802002-11-03 00:38:21 +00001354}
1355
1356void eth_halt() {
1357 smc_close();
1358}
1359
1360int eth_rx() {
1361 return smc_rcv();
1362}
1363
1364int eth_send(volatile void *packet, int length) {
1365 return smc_send_packet(packet, length);
1366}
1367
wdenkb56ddc62003-09-15 21:14:37 +00001368int smc_get_ethaddr (bd_t * bd)
wdenk0b97ab12003-06-19 23:58:30 +00001369{
wdenkb56ddc62003-09-15 21:14:37 +00001370 int env_size, rom_valid, env_present = 0, reg;
1371 char *s = NULL, *e, *v_mac, es[] = "11:22:33:44:55:66";
1372 uchar s_env_mac[64], v_env_mac[6], v_rom_mac[6];
wdenk0b97ab12003-06-19 23:58:30 +00001373
wdenkb56ddc62003-09-15 21:14:37 +00001374 env_size = getenv_r ("ethaddr", s_env_mac, sizeof (s_env_mac));
1375 if ((env_size > 0) && (env_size < sizeof (es))) { /* exit if env is bad */
1376 printf ("\n*** ERROR: ethaddr is not set properly!!\n");
1377 return (-1);
wdenk8bde7f72003-06-27 21:31:46 +00001378 }
wdenk8bde7f72003-06-27 21:31:46 +00001379
wdenkb56ddc62003-09-15 21:14:37 +00001380 if (env_size > 0) {
1381 env_present = 1;
1382 s = s_env_mac;
wdenk8bde7f72003-06-27 21:31:46 +00001383 }
wdenkb56ddc62003-09-15 21:14:37 +00001384
1385 for (reg = 0; reg < 6; ++reg) { /* turn string into mac value */
1386 v_env_mac[reg] = s ? simple_strtoul (s, &e, 16) : 0;
1387 if (s)
1388 s = (*e) ? e + 1 : e;
1389 }
1390
1391 rom_valid = get_rom_mac (v_rom_mac); /* get ROM mac value if any */
1392
1393 if (!env_present) { /* if NO env */
1394 if (rom_valid) { /* but ROM is valid */
1395 v_mac = v_rom_mac;
1396 sprintf (s_env_mac, "%02X:%02X:%02X:%02X:%02X:%02X",
1397 v_mac[0], v_mac[1], v_mac[2], v_mac[3],
1398 v_mac[4], v_mac[5]);
1399 setenv ("ethaddr", s_env_mac);
1400 } else { /* no env, bad ROM */
1401 printf ("\n*** ERROR: ethaddr is NOT set !!\n");
1402 return (-1);
1403 }
1404 } else { /* good env, don't care ROM */
1405 v_mac = v_env_mac; /* always use a good env over a ROM */
1406 }
1407
1408 if (env_present && rom_valid) { /* if both env and ROM are good */
1409 if (memcmp (v_env_mac, v_rom_mac, 6) != 0) {
wdenkb56ddc62003-09-15 21:14:37 +00001410 printf ("\nWarning: MAC addresses don't match:\n");
1411 printf ("\tHW MAC address: "
1412 "%02X:%02X:%02X:%02X:%02X:%02X\n",
1413 v_rom_mac[0], v_rom_mac[1],
1414 v_rom_mac[2], v_rom_mac[3],
1415 v_rom_mac[4], v_rom_mac[5] );
1416 printf ("\t\"ethaddr\" value: "
1417 "%02X:%02X:%02X:%02X:%02X:%02X\n",
1418 v_env_mac[0], v_env_mac[1],
1419 v_env_mac[2], v_env_mac[3],
1420 v_env_mac[4], v_env_mac[5]) ;
1421 debug ("### Set MAC addr from environment\n");
wdenkb56ddc62003-09-15 21:14:37 +00001422 }
1423 }
1424 memcpy (bd->bi_enetaddr, v_mac, 6); /* update global address to match env (allows env changing) */
1425 smc_set_mac_addr (v_mac); /* use old function to update smc default */
1426 return (0);
wdenk0b97ab12003-06-19 23:58:30 +00001427}
1428
wdenkb56ddc62003-09-15 21:14:37 +00001429int get_rom_mac (char *v_rom_mac)
wdenk0b97ab12003-06-19 23:58:30 +00001430{
wdenkb56ddc62003-09-15 21:14:37 +00001431 int is_rom_present = 0;
wdenk0b97ab12003-06-19 23:58:30 +00001432
wdenkb56ddc62003-09-15 21:14:37 +00001433#ifdef HARDCODE_MAC /* used for testing or to supress run time warnings */
1434 char hw_mac_addr[] = { 0x02, 0x80, 0xad, 0x20, 0x31, 0xb8 };
1435
1436 memcpy (v_rom_mac, hw_mac_addr, 6);
1437 return (1);
wdenk0b97ab12003-06-19 23:58:30 +00001438#else
wdenkb56ddc62003-09-15 21:14:37 +00001439 if (is_rom_present) {
1440 /* if eeprom contents are valid
1441 * extract mac address into hw_mac_addr, 8 or 16 bit accesses
1442 * memcpy (v_rom_mac, hc_mac_addr, 6);
1443 * return(1);
1444 */
1445 }
1446 memset (v_rom_mac, 0, 6);
1447 return (0);
wdenk0b97ab12003-06-19 23:58:30 +00001448#endif
1449}
wdenkfe8c2802002-11-03 00:38:21 +00001450#endif /* CONFIG_DRIVER_SMC91111 */