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Vitaly Andrianovef509b92014-04-04 13:16:53 -04001/*
2 * Keystone2: Common SoC definitions, structures etc.
3 *
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9#ifndef __ASM_ARCH_HARDWARE_H
10#define __ASM_ARCH_HARDWARE_H
11
12#include <config.h>
13
14#ifndef __ASSEMBLY__
15
16#include <linux/sizes.h>
17#include <asm/io.h>
18
19#define REG(addr) (*(volatile unsigned int *)(addr))
20#define REG_P(addr) ((volatile unsigned int *)(addr))
21
22typedef volatile unsigned int dv_reg;
23typedef volatile unsigned int *dv_reg_p;
24
Vitaly Andrianovef509b92014-04-04 13:16:53 -040025#endif
26
27#define BIT(x) (1 << (x))
28
29#define KS2_DDRPHY_PIR_OFFSET 0x04
30#define KS2_DDRPHY_PGCR0_OFFSET 0x08
31#define KS2_DDRPHY_PGCR1_OFFSET 0x0C
32#define KS2_DDRPHY_PGSR0_OFFSET 0x10
33#define KS2_DDRPHY_PGSR1_OFFSET 0x14
34#define KS2_DDRPHY_PLLCR_OFFSET 0x18
35#define KS2_DDRPHY_PTR0_OFFSET 0x1C
36#define KS2_DDRPHY_PTR1_OFFSET 0x20
37#define KS2_DDRPHY_PTR2_OFFSET 0x24
38#define KS2_DDRPHY_PTR3_OFFSET 0x28
39#define KS2_DDRPHY_PTR4_OFFSET 0x2C
40#define KS2_DDRPHY_DCR_OFFSET 0x44
41
42#define KS2_DDRPHY_DTPR0_OFFSET 0x48
43#define KS2_DDRPHY_DTPR1_OFFSET 0x4C
44#define KS2_DDRPHY_DTPR2_OFFSET 0x50
45
46#define KS2_DDRPHY_MR0_OFFSET 0x54
47#define KS2_DDRPHY_MR1_OFFSET 0x58
48#define KS2_DDRPHY_MR2_OFFSET 0x5C
49#define KS2_DDRPHY_DTCR_OFFSET 0x68
50#define KS2_DDRPHY_PGCR2_OFFSET 0x8C
51
52#define KS2_DDRPHY_ZQ0CR1_OFFSET 0x184
53#define KS2_DDRPHY_ZQ1CR1_OFFSET 0x194
54#define KS2_DDRPHY_ZQ2CR1_OFFSET 0x1A4
55#define KS2_DDRPHY_ZQ3CR1_OFFSET 0x1B4
56
57#define KS2_DDRPHY_DATX8_8_OFFSET 0x3C0
58
59#define IODDRM_MASK 0x00000180
60#define ZCKSEL_MASK 0x01800000
61#define CL_MASK 0x00000072
62#define WR_MASK 0x00000E00
63#define BL_MASK 0x00000003
64#define RRMODE_MASK 0x00040000
65#define UDIMM_MASK 0x20000000
66#define BYTEMASK_MASK 0x0003FC00
67#define MPRDQ_MASK 0x00000080
68#define PDQ_MASK 0x00000070
69#define NOSRA_MASK 0x08000000
70#define ECC_MASK 0x00000001
71
72#define KS2_DDR3_MIDR_OFFSET 0x00
73#define KS2_DDR3_STATUS_OFFSET 0x04
74#define KS2_DDR3_SDCFG_OFFSET 0x08
75#define KS2_DDR3_SDRFC_OFFSET 0x10
76#define KS2_DDR3_SDTIM1_OFFSET 0x18
77#define KS2_DDR3_SDTIM2_OFFSET 0x1C
78#define KS2_DDR3_SDTIM3_OFFSET 0x20
79#define KS2_DDR3_SDTIM4_OFFSET 0x28
80#define KS2_DDR3_PMCTL_OFFSET 0x38
81#define KS2_DDR3_ZQCFG_OFFSET 0xC8
82
Hao Zhang101eec52014-07-09 19:48:41 +030083#define KS2_DDR3_PLLCTRL_PHY_RESET 0x80000000
84
Murali Karicheriafee59c2014-05-29 18:57:12 +030085#define KS2_UART0_BASE 0x02530c00
86#define KS2_UART1_BASE 0x02531000
87
Khoronzhuk, Ivan04b7ce02014-07-09 19:48:39 +030088/* PSC */
89#define KS2_PSC_BASE 0x02350000
Hao Zhang7b26c1f2014-07-09 19:48:44 +030090#define KS2_LPSC_GEM_0 15
91#define KS2_LPSC_TETRIS 52
92#define KS2_TETRIS_PWR_DOMAIN 31
Khoronzhuk, Ivan04b7ce02014-07-09 19:48:39 +030093
Khoronzhuk, Ivan909ea9a2014-06-07 05:10:49 +030094/* AEMIF */
95#define KS2_AEMIF_CNTRL_BASE 0x21000a00
96#define DAVINCI_ASYNC_EMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
97
Hao Zhang7b26c1f2014-07-09 19:48:44 +030098/* Flag from ks2_debug options to check if DSPs need to stay ON */
99#define DBG_LEAVE_DSPS_ON 0x1
100
Vitaly Andrianovef509b92014-04-04 13:16:53 -0400101#ifdef CONFIG_SOC_K2HK
102#include <asm/arch/hardware-k2hk.h>
103#endif
104
105#ifndef __ASSEMBLY__
106static inline int cpu_is_k2hk(void)
107{
Khoronzhuk, Ivan3d315382014-07-09 23:44:44 +0300108 unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG);
Vitaly Andrianovef509b92014-04-04 13:16:53 -0400109 unsigned int part_no = (jtag_id >> 12) & 0xffff;
110
111 return (part_no == 0xb981) ? 1 : 0;
112}
113
114static inline int cpu_revision(void)
115{
Khoronzhuk, Ivan3d315382014-07-09 23:44:44 +0300116 unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG);
Vitaly Andrianovef509b92014-04-04 13:16:53 -0400117 unsigned int rev = (jtag_id >> 28) & 0xf;
118
119 return rev;
120}
121
122void share_all_segments(int priv_id);
123int cpu_to_bus(u32 *ptr, u32 length);
Vitaly Andrianovef509b92014-04-04 13:16:53 -0400124void sdelay(unsigned long);
125
126#endif
127
128#endif /* __ASM_ARCH_HARDWARE_H */