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Ron Madrid5bb907a2009-01-22 15:05:24 -08001/*
2 * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
3 * Copyright (C) Sheldon Instruments, Inc. 2008
4 *
5 * Author: Ron Madrid <info@sheldoninst.com>
6 *
7 * (C) Copyright 2006
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020010 * SPDX-License-Identifier: GPL-2.0+
Ron Madrid5bb907a2009-01-22 15:05:24 -080011 */
12
13#include <common.h>
14#include <mpc83xx.h>
15#include <spd_sdram.h>
16#include <asm/bitops.h>
17#include <asm/io.h>
18#include <asm/processor.h>
19#include <asm/mmu.h>
20
21DECLARE_GLOBAL_DATA_PTR;
22
23static long fixed_sdram(void);
24
25#if defined(CONFIG_NAND_SPL)
26void si_wait_i2c(void)
27{
28 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
29
30 while (!(__raw_readb(&im->i2c[0].sr) & 0x02))
31 ;
32
33 __raw_writeb(0x00, &im->i2c[0].sr);
34
35 sync();
36
37 return;
38}
39
40void si_read_i2c(u32 lbyte, int count, u8 *buffer)
41{
42 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
43 u32 i;
44 u8 chip = 0x50 << 1; /* boot sequencer I2C */
45 u32 ubyte = (lbyte & 0xff00) >> 8;
46
47 lbyte &= 0xff;
48
49 /*
50 * Set up controller
51 */
52 __raw_writeb(0x3f, &im->i2c[0].fdr);
53 __raw_writeb(0x00, &im->i2c[0].adr);
54 __raw_writeb(0x00, &im->i2c[0].sr);
55 __raw_writeb(0x00, &im->i2c[0].dr);
56
57 while (__raw_readb(&im->i2c[0].sr) & 0x20)
58 ;
59
60 /*
61 * Writing address to device
62 */
63 __raw_writeb(0xb0, &im->i2c[0].cr);
64 sync();
65 __raw_writeb(chip, &im->i2c[0].dr);
66 si_wait_i2c();
67
68 __raw_writeb(0xb0, &im->i2c[0].cr);
69 sync();
70 __raw_writeb(ubyte, &im->i2c[0].dr);
71 si_wait_i2c();
72
73 __raw_writeb(lbyte, &im->i2c[0].dr);
74 si_wait_i2c();
75
76 __raw_writeb(0xb4, &im->i2c[0].cr);
77 sync();
78 __raw_writeb(chip + 1, &im->i2c[0].dr);
79 si_wait_i2c();
80
81 __raw_writeb(0xa0, &im->i2c[0].cr);
82 sync();
83
84 /*
85 * Dummy read
86 */
87 __raw_readb(&im->i2c[0].dr);
88
89 si_wait_i2c();
90
91 /*
92 * Read actual data
93 */
94 for (i = 0; i < count; i++)
95 {
96 if (i == (count - 2)) /* Reached next to last byte, No ACK */
97 __raw_writeb(0xa8, &im->i2c[0].cr);
98 if (i == (count - 1)) /* Reached last byte, STOP */
99 __raw_writeb(0x88, &im->i2c[0].cr);
100
101 /* Read byte of data */
102 buffer[i] = __raw_readb(&im->i2c[0].dr);
103
104 if (i == (count - 1))
105 break;
106 si_wait_i2c();
107 }
108
109 return;
110}
111#endif /* CONFIG_NAND_SPL */
112
113phys_size_t initdram(int board_type)
114{
115 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
Becky Brucef51cdaf2010-06-17 11:37:20 -0500116 volatile fsl_lbc_t *lbc = &im->im_lbc;
Ron Madrid5bb907a2009-01-22 15:05:24 -0800117 u32 msize;
118
119 if ((__raw_readl(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32) im)
120 return -1;
121
122 /* DDR SDRAM - Main SODIMM */
123 __raw_writel(CONFIG_SYS_DDR_BASE & LAWBAR_BAR, &im->sysconf.ddrlaw[0].bar);
124
125 msize = fixed_sdram();
126
127 /* Local Bus setup lbcr and mrtpr */
128 __raw_writel(CONFIG_SYS_LBC_LBCR, &lbc->lbcr);
129 __raw_writel(CONFIG_SYS_LBC_MRTPR, &lbc->mrtpr);
130 sync();
131
132 /* return total bus SDRAM size(bytes) -- DDR */
133 return (msize * 1024 * 1024);
134}
135
136/*************************************************************************
137 * fixed sdram init -- reads values from boot sequencer I2C
138 ************************************************************************/
139static long fixed_sdram(void)
140{
141 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
142 u32 msizelog2, msize = 1;
143#if defined(CONFIG_NAND_SPL)
144 u32 i;
145 const u8 bytecount = 135;
146 u8 buffer[bytecount];
147 u32 addr, data;
148
149 si_read_i2c(0, bytecount, buffer);
150
151 for (i = 18; i < bytecount; i += 7){
152 addr = (u32)buffer[i];
153 addr <<= 8;
154 addr |= (u32)buffer[i + 1];
155 addr <<= 2;
156 data = (u32)buffer[i + 2];
157 data <<= 8;
158 data |= (u32)buffer[i + 3];
159 data <<= 8;
160 data |= (u32)buffer[i + 4];
161 data <<= 8;
162 data |= (u32)buffer[i + 5];
163
164 __raw_writel(data, (u32 *)(CONFIG_SYS_IMMR + addr));
165 }
166
167 sync();
168
169 /* enable DDR controller */
170 __raw_writel((__raw_readl(&im->ddr.sdram_cfg) | SDRAM_CFG_MEM_EN), &im->ddr.sdram_cfg);
171#endif /* (CONFIG_NAND_SPL) */
172
173 msizelog2 = ((__raw_readl(&im->sysconf.ddrlaw[0].ar) & LAWAR_SIZE) + 1);
174 msize <<= (msizelog2 - 20);
175
176 return msize;
177}