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wdenk2262cfe2002-11-18 00:14:45 +00001/*
2 * (C) Copyright 2002
3 * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/* This file is largely based on code obtned from AMD. AMD's original
wdenk8bde7f72003-06-27 21:31:46 +000025 * copyright is included below
wdenk2262cfe2002-11-18 00:14:45 +000026 */
27
28/*
29 * =============================================================================
wdenk8bde7f72003-06-27 21:31:46 +000030 *
31 * Copyright 1999 Advanced Micro Devices, Inc.
32 *
33 * This software is the property of Advanced Micro Devices, Inc (AMD) which
34 * specifically grants the user the right to modify, use and distribute this
35 * software provided this COPYRIGHT NOTICE is not removed or altered. All
36 * other rights are reserved by AMD.
37 *
38 * THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY
39 * OF ANY KIND INCLUDING WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT OF
wdenk2262cfe2002-11-18 00:14:45 +000040 * THIRD-PARTY INTELLECTUAL PROPERTY, OR FITNESS FOR ANY PARTICULAR PURPOSE.
41 * IN NO EVENT SHALL AMD OR ITS SUPPLIERS BE LIABLE FOR ANY DAMAGES WHATSOEVER
42 * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
43 * INTERRUPTION, LOSS OF INFORMAITON) ARISING OUT OF THE USE OF OR INABILITY
44 * TO USE THE MATERIALS, EVEN IF AMD HAS BEEN ADVISED OF THE POSSIBILITY OF
45 * SUCH DAMAGES. BECAUSE SOME JURSIDICTIONS PROHIBIT THE EXCLUSION OR
46 * LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
47 * LIMITATION MAY NOT APPLY TO YOU.
wdenk8bde7f72003-06-27 21:31:46 +000048 *
wdenk2262cfe2002-11-18 00:14:45 +000049 * AMD does not assume any responsibility for any errors that may appear in
50 * the Materials nor any responsibility to support or update the Materials.
51 * AMD retains the right to make changes to its test specifications at any
52 * time, without notice.
wdenk8bde7f72003-06-27 21:31:46 +000053 *
54 * So that all may benefit from your experience, please report any problems
55 * or suggestions about this software back to AMD. Please include your name,
56 * company, telephone number, AMD product requiring support and question or
57 * problem encountered.
58 *
59 * Advanced Micro Devices, Inc. Worldwide support and contact
60 * Embedded Processor Division information available at:
wdenk2262cfe2002-11-18 00:14:45 +000061 * Systems Engineering epd.support@amd.com
62 * 5204 E. Ben White Blvd. -or-
63 * Austin, TX 78741 http://www.amd.com/html/support/techsup.html
64 * ============================================================================
65 */
66
67
68/*******************************************************************************
wdenk8bde7f72003-06-27 21:31:46 +000069 * AUTHOR : Buddy Fey - Original.
wdenk2262cfe2002-11-18 00:14:45 +000070 *******************************************************************************
71 */
72
73
74/*******************************************************************************
75 * FUNCTIONAL DESCRIPTION:
76 * This routine is called to autodetect the geometry of the DRAM.
77 *
78 * This routine is called to determine the number of column bits for the DRAM
79 * devices in this external bank. This routine assumes that the external bank
80 * has been configured for an 11-bit column and for 4 internal banks. This gives
81 * us the maximum address reach in memory. By writing a test value to the max
82 * address and locating where it aliases to, we can determine the number of valid
83 * column bits.
84 *
85 * This routine is called to determine the number of internal banks each DRAM
86 * device has. The external bank (under test) is configured for maximum reach
87 * with 11-bit columns and 4 internal banks. This routine will write to a max
88 * address (BA1 and BA0 = 1) and then read from an address with BA1=0 to see if
89 * that column is a "don't care". If BA1 does not affect write/read of data,
90 * then this device has only 2 internal banks.
91 *
92 * This routine is called to determine the ending address for this external
93 * bank of SDRAM. We write to a max address with a data value and then disable
94 * row address bits looking for "don't care" locations. Each "don't care" bit
95 * represents a dividing of the maximum density (128M) by 2. By dividing the
96 * maximum of 32 4M chunks in an external bank down by all the "don't care" bits
97 * determined during sizing, we set the proper density.
98 *
99 * WARNINGS.
100 * bp must be preserved because it is used for return linkage.
101 *
102 * EXIT
103 * nothing returned - but the memory subsystem is enabled
104 *******************************************************************************
105 */
106
wdenk7a8e9bed2003-05-31 18:35:21 +0000107#include <config.h>
108#ifdef CONFIG_SC520
109
wdenk2262cfe2002-11-18 00:14:45 +0000110.section .text
111.equ DRCCTL, 0x0fffef010 /* DRAM control register */
112.equ DRCTMCTL, 0x0fffef012 /* DRAM timing control register */
113.equ DRCCFG, 0x0fffef014 /* DRAM bank configuration register */
114.equ DRCBENDADR, 0x0fffef018 /* DRAM bank ending address register */
115.equ ECCCTL, 0x0fffef020 /* DRAM ECC control register */
Wolfgang Denk94568b62006-08-14 23:23:06 +0200116.equ ECCINT, 0x0fffefd18 /* DRAM ECC nmi-INT mapping */
wdenk2262cfe2002-11-18 00:14:45 +0000117.equ DBCTL, 0x0fffef040 /* DRAM buffer control register */
118
119.equ CACHELINESZ, 0x00000010 /* size of our cache line (read buffer) */
120.equ COL11_ADR, 0x0e001e00 /* 11 col addrs */
121.equ COL10_ADR, 0x0e000e00 /* 10 col addrs */
122.equ COL09_ADR, 0x0e000600 /* 9 col addrs */
123.equ COL08_ADR, 0x0e000200 /* 8 col addrs */
124.equ ROW14_ADR, 0x0f000000 /* 14 row addrs */
125.equ ROW13_ADR, 0x07000000 /* 13 row addrs */
126.equ ROW12_ADR, 0x03000000 /* 12 row addrs */
127.equ ROW11_ADR, 0x01000000 /* 11 row addrs/also bank switch */
128.equ ROW10_ADR, 0x00000000 /* 10 row addrs/also bank switch */
129.equ COL11_DATA, 0x0b0b0b0b /* 11 col addrs */
130.equ COL10_DATA, 0x0a0a0a0a /* 10 col data */
131.equ COL09_DATA, 0x09090909 /* 9 col data */
132.equ COL08_DATA, 0x08080808 /* 8 col data */
133.equ ROW14_DATA, 0x3f3f3f3f /* 14 row data (MASK) */
134.equ ROW13_DATA, 0x1f1f1f1f /* 13 row data (MASK) */
135.equ ROW12_DATA, 0x0f0f0f0f /* 12 row data (MASK) */
136.equ ROW11_DATA, 0x07070707 /* 11 row data/also bank switch (MASK) */
137.equ ROW10_DATA, 0xaaaaaaaa /* 10 row data/also bank switch (MASK) */
138
139
140 /*
141 * initialize dram controller registers
142 */
143.globl mem_init
wdenk8bde7f72003-06-27 21:31:46 +0000144mem_init:
145 xorw %ax,%ax
146 movl $DBCTL, %edi
wdenk7a8e9bed2003-05-31 18:35:21 +0000147 movb %al, (%edi) /* disable write buffer */
wdenk2262cfe2002-11-18 00:14:45 +0000148
wdenk8bde7f72003-06-27 21:31:46 +0000149 movl $ECCCTL, %edi
wdenk7a8e9bed2003-05-31 18:35:21 +0000150 movb %al, (%edi) /* disable ECC */
wdenk2262cfe2002-11-18 00:14:45 +0000151
wdenk8bde7f72003-06-27 21:31:46 +0000152 movl $DRCTMCTL, %edi
153 movb $0x1E,%al /* Set SDRAM timing for slowest */
wdenk7a8e9bed2003-05-31 18:35:21 +0000154 movb %al, (%edi)
wdenk2262cfe2002-11-18 00:14:45 +0000155
156 /*
157 * setup loop to do 4 external banks starting with bank 3
158 */
wdenk8bde7f72003-06-27 21:31:46 +0000159 movl $0xff000000,%eax /* enable last bank and setup */
160 movl $DRCBENDADR, %edi /* ending address register */
wdenk7a8e9bed2003-05-31 18:35:21 +0000161 movl %eax, (%edi)
wdenk2262cfe2002-11-18 00:14:45 +0000162
wdenk8bde7f72003-06-27 21:31:46 +0000163 movl $DRCCFG, %edi /* setup */
164 movw $0xbbbb,%ax /* dram config register for */
wdenk7a8e9bed2003-05-31 18:35:21 +0000165 movw %ax, (%edi)
wdenk2262cfe2002-11-18 00:14:45 +0000166
167 /*
168 * issue a NOP to all DRAMs
169 */
wdenk8bde7f72003-06-27 21:31:46 +0000170 movl $DRCCTL, %edi /* setup DRAM control register with */
171 movb $0x1,%al /* Disable refresh,disable write buffer */
wdenk7a8e9bed2003-05-31 18:35:21 +0000172 movb %al, (%edi)
wdenk8bde7f72003-06-27 21:31:46 +0000173 movl $CACHELINESZ, %esi /* just a dummy address to write for */
wdenk7a8e9bed2003-05-31 18:35:21 +0000174 movw %ax, (%esi)
wdenk2262cfe2002-11-18 00:14:45 +0000175 /*
176 * delay for 100 usec? 200?
177 * ******this is a cludge for now *************
178 */
wdenk8bde7f72003-06-27 21:31:46 +0000179 movw $100,%cx
180sizdelay:
181 loop sizdelay /* we need 100 usec here */
wdenk2262cfe2002-11-18 00:14:45 +0000182 /***********************************************/
183
184 /*
185 * issue all banks precharge
186 */
wdenk8bde7f72003-06-27 21:31:46 +0000187 movb $0x2,%al /* All banks precharge */
wdenk7a8e9bed2003-05-31 18:35:21 +0000188 movb %al, (%edi)
189 movw %ax, (%esi)
wdenk2262cfe2002-11-18 00:14:45 +0000190
191 /*
wdenk8bde7f72003-06-27 21:31:46 +0000192 * issue 2 auto refreshes to all banks
wdenk2262cfe2002-11-18 00:14:45 +0000193 */
wdenk8bde7f72003-06-27 21:31:46 +0000194 movb $0x4,%al /* Auto refresh cmd */
wdenk7a8e9bed2003-05-31 18:35:21 +0000195 movb %al, (%edi)
wdenk8bde7f72003-06-27 21:31:46 +0000196 movw $2,%cx
197refresh1:
wdenk7a8e9bed2003-05-31 18:35:21 +0000198 movw %ax, (%esi)
wdenk8bde7f72003-06-27 21:31:46 +0000199 loop refresh1
wdenk2262cfe2002-11-18 00:14:45 +0000200
201 /*
202 * issue LOAD MODE REGISTER command
203 */
wdenk8bde7f72003-06-27 21:31:46 +0000204 movb $0x3,%al /* Load mode register cmd */
wdenk7a8e9bed2003-05-31 18:35:21 +0000205 movb %al, (%edi)
206 movw %ax, (%esi)
wdenk2262cfe2002-11-18 00:14:45 +0000207
208 /*
wdenk8bde7f72003-06-27 21:31:46 +0000209 * issue 8 more auto refreshes to all banks
wdenk2262cfe2002-11-18 00:14:45 +0000210 */
wdenk8bde7f72003-06-27 21:31:46 +0000211 movb $0x4,%al /* Auto refresh cmd */
212 movb %al, (%edi)
213 movw $8,%cx
214refresh2:
215 movw %ax, (%esi)
216 loop refresh2
217
218 /*
219 * set control register to NORMAL mode
220 */
221 movb $0x0,%al /* Normal mode value */
wdenk7a8e9bed2003-05-31 18:35:21 +0000222 movb %al, (%edi)
wdenk2262cfe2002-11-18 00:14:45 +0000223
224 /*
225 * size dram starting with external bank 3 moving to external bank 0
226 */
wdenk8bde7f72003-06-27 21:31:46 +0000227 movl $0x3,%ecx /* start with external bank 3 */
wdenk2262cfe2002-11-18 00:14:45 +0000228
wdenk8bde7f72003-06-27 21:31:46 +0000229nextbank:
wdenk2262cfe2002-11-18 00:14:45 +0000230
231 /*
232 * write col 11 wrap adr
233 */
wdenk8bde7f72003-06-27 21:31:46 +0000234 movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */
235 movl $COL11_DATA, %eax /* pattern for max supported columns(11) */
wdenk7a8e9bed2003-05-31 18:35:21 +0000236 movl %eax, (%esi) /* write max col pattern at max col adr */
237 movl (%esi), %ebx /* optional read */
wdenk8bde7f72003-06-27 21:31:46 +0000238 cmpl %ebx,%eax /* to verify write */
239 jnz bad_ram /* this ram is bad */
wdenk2262cfe2002-11-18 00:14:45 +0000240 /*
241 * write col 10 wrap adr
242 */
243
wdenk8bde7f72003-06-27 21:31:46 +0000244 movl $COL10_ADR, %esi /* set address to 10 col wrap address */
245 movl $COL10_DATA, %eax /* pattern for 10 col wrap */
wdenk7a8e9bed2003-05-31 18:35:21 +0000246 movl %eax, (%esi) /* write 10 col pattern @ 10 col wrap adr */
247 movl (%esi), %ebx /* optional read */
wdenk8bde7f72003-06-27 21:31:46 +0000248 cmpl %ebx,%eax /* to verify write */
249 jnz bad_ram /* this ram is bad */
wdenk2262cfe2002-11-18 00:14:45 +0000250 /*
251 * write col 9 wrap adr
252 */
wdenk8bde7f72003-06-27 21:31:46 +0000253 movl $COL09_ADR, %esi /* set address to 9 col wrap address */
254 movl $COL09_DATA, %eax /* pattern for 9 col wrap */
wdenk7a8e9bed2003-05-31 18:35:21 +0000255 movl %eax, (%esi) /* write 9 col pattern @ 9 col wrap adr */
256 movl (%esi), %ebx /* optional read */
wdenk8bde7f72003-06-27 21:31:46 +0000257 cmpl %ebx,%eax /* to verify write */
258 jnz bad_ram /* this ram is bad */
wdenk2262cfe2002-11-18 00:14:45 +0000259 /*
260 * write col 8 wrap adr
261 */
wdenk8bde7f72003-06-27 21:31:46 +0000262 movl $COL08_ADR, %esi /* set address to min(8) col wrap address */
263 movl $COL08_DATA, %eax /* pattern for min (8) col wrap */
wdenk7a8e9bed2003-05-31 18:35:21 +0000264 movl %eax, (%esi) /* write min col pattern @ min col adr */
265 movl (%esi), %ebx /* optional read */
wdenk8bde7f72003-06-27 21:31:46 +0000266 cmpl %ebx,%eax /* to verify write */
267 jnz bad_ram /* this ram is bad */
wdenk2262cfe2002-11-18 00:14:45 +0000268 /*
269 * write row 14 wrap adr
270 */
wdenk8bde7f72003-06-27 21:31:46 +0000271 movl $ROW14_ADR, %esi /* set address to max row (14) wrap addr */
272 movl $ROW14_DATA, %eax /* pattern for max supported rows(14) */
wdenk7a8e9bed2003-05-31 18:35:21 +0000273 movl %eax, (%esi) /* write max row pattern at max row adr */
274 movl (%esi), %ebx /* optional read */
wdenk8bde7f72003-06-27 21:31:46 +0000275 cmpl %ebx,%eax /* to verify write */
276 jnz bad_ram /* this ram is bad */
wdenk2262cfe2002-11-18 00:14:45 +0000277 /*
278 * write row 13 wrap adr
279 */
wdenk8bde7f72003-06-27 21:31:46 +0000280 movl $ROW13_ADR, %esi /* set address to 13 row wrap address */
281 movl $ROW13_DATA, %eax /* pattern for 13 row wrap */
wdenk7a8e9bed2003-05-31 18:35:21 +0000282 movl %eax, (%esi) /* write 13 row pattern @ 13 row wrap adr */
283 movl (%esi), %ebx /* optional read */
wdenk8bde7f72003-06-27 21:31:46 +0000284 cmpl %ebx,%eax /* to verify write */
285 jnz bad_ram /* this ram is bad */
wdenk2262cfe2002-11-18 00:14:45 +0000286 /*
287 * write row 12 wrap adr
288 */
wdenk8bde7f72003-06-27 21:31:46 +0000289 movl $ROW12_ADR, %esi /* set address to 12 row wrap address */
290 movl $ROW12_DATA, %eax /* pattern for 12 row wrap */
wdenk7a8e9bed2003-05-31 18:35:21 +0000291 movl %eax, (%esi) /* write 12 row pattern @ 12 row wrap adr */
292 movl (%esi), %ebx /* optional read */
wdenk8bde7f72003-06-27 21:31:46 +0000293 cmpl %ebx,%eax /* to verify write */
294 jnz bad_ram /* this ram is bad */
wdenk2262cfe2002-11-18 00:14:45 +0000295 /*
296 * write row 11 wrap adr
297 */
wdenk8bde7f72003-06-27 21:31:46 +0000298 movl $ROW11_ADR, %edi /* set address to 11 row wrap address */
299 movl $ROW11_DATA, %eax /* pattern for 11 row wrap */
wdenk7a8e9bed2003-05-31 18:35:21 +0000300 movl %eax, (%edi) /* write 11 row pattern @ 11 row wrap adr */
301 movl (%edi), %ebx /* optional read */
wdenk8bde7f72003-06-27 21:31:46 +0000302 cmpl %ebx,%eax /* to verify write */
303 jnz bad_ram /* this ram is bad */
wdenk2262cfe2002-11-18 00:14:45 +0000304 /*
305 * write row 10 wrap adr --- this write is really to determine number of banks
306 */
wdenk8bde7f72003-06-27 21:31:46 +0000307 movl $ROW10_ADR, %edi /* set address to 10 row wrap address */
308 movl $ROW10_DATA, %eax /* pattern for 10 row wrap (AA) */
wdenk7a8e9bed2003-05-31 18:35:21 +0000309 movl %eax, (%edi) /* write 10 row pattern @ 10 row wrap adr */
310 movl (%edi), %ebx /* optional read */
wdenk8bde7f72003-06-27 21:31:46 +0000311 cmpl %ebx,%eax /* to verify write */
312 jnz bad_ram /* this ram is bad */
wdenk2262cfe2002-11-18 00:14:45 +0000313 /*
wdenk8bde7f72003-06-27 21:31:46 +0000314 * read data @ row 12 wrap adr to determine * banks,
wdenk2262cfe2002-11-18 00:14:45 +0000315 * and read data @ row 14 wrap adr to determine * rows.
316 * if data @ row 12 wrap adr is not AA, 11 or 12 we have bad RAM.
wdenk8bde7f72003-06-27 21:31:46 +0000317 * if data @ row 12 wrap == AA, we only have 2 banks, NOT 4
wdenk2262cfe2002-11-18 00:14:45 +0000318 * if data @ row 12 wrap == 11 or 12, we have 4 banks,
319 */
wdenk8bde7f72003-06-27 21:31:46 +0000320 xorw %di,%di /* value for 2 banks in DI */
321 movl (%esi), %ebx /* read from 12 row wrap to check banks
322 * (esi is setup from the write to row 12 wrap) */
323 cmpl %ebx,%eax /* check for AA pattern (eax holds the aa pattern) */
324 jz only2 /* if pattern == AA, we only have 2 banks */
wdenk2262cfe2002-11-18 00:14:45 +0000325
326 /* 4 banks */
wdenk8bde7f72003-06-27 21:31:46 +0000327
328 movw $8,%di /* value for 4 banks in DI (BNK_CNT bit) */
329 cmpl $ROW11_DATA, %ebx /* only other legitimate values are 11 */
330 jz only2
331 cmpl $ROW12_DATA, %ebx /* and 12 */
332 jnz bad_ram /* its bad if not 11 or 12! */
333
wdenk2262cfe2002-11-18 00:14:45 +0000334 /* fall through */
wdenk8bde7f72003-06-27 21:31:46 +0000335only2:
wdenk2262cfe2002-11-18 00:14:45 +0000336 /*
337 * validate row mask
338 */
wdenk8bde7f72003-06-27 21:31:46 +0000339 movl $ROW14_ADR, %esi /* set address back to max row wrap addr */
wdenk7a8e9bed2003-05-31 18:35:21 +0000340 movl (%esi), %eax /* read actual number of rows @ row14 adr */
wdenk2262cfe2002-11-18 00:14:45 +0000341
wdenk8bde7f72003-06-27 21:31:46 +0000342 cmpl $ROW11_DATA, %eax /* row must be greater than 11 pattern */
343 jb bad_ram
wdenk2262cfe2002-11-18 00:14:45 +0000344
wdenk8bde7f72003-06-27 21:31:46 +0000345 cmpl $ROW14_DATA, %eax /* and row must be less than 14 pattern */
346 ja bad_ram
wdenk2262cfe2002-11-18 00:14:45 +0000347
wdenk8bde7f72003-06-27 21:31:46 +0000348 cmpb %ah,%al /* verify all 4 bytes of dword same */
349 jnz bad_ram
350 movl %eax,%ebx
351 shrl $16,%ebx
352 cmpw %bx,%ax
353 jnz bad_ram
wdenk2262cfe2002-11-18 00:14:45 +0000354 /*
355 * read col 11 wrap adr for real column data value
356 */
wdenk8bde7f72003-06-27 21:31:46 +0000357 movl $COL11_ADR, %esi /* set address to max col (11) wrap addr */
wdenk7a8e9bed2003-05-31 18:35:21 +0000358 movl (%esi), %eax /* read real col number at max col adr */
wdenk2262cfe2002-11-18 00:14:45 +0000359 /*
360 * validate column data
361 */
wdenk8bde7f72003-06-27 21:31:46 +0000362 cmpl $COL08_DATA, %eax /* col must be greater than 8 pattern */
363 jb bad_ram
wdenk2262cfe2002-11-18 00:14:45 +0000364
wdenk8bde7f72003-06-27 21:31:46 +0000365 cmpl $COL11_DATA, %eax /* and row must be less than 11 pattern */
366 ja bad_ram
wdenk2262cfe2002-11-18 00:14:45 +0000367
wdenk8bde7f72003-06-27 21:31:46 +0000368 subl $COL08_DATA, %eax /* normalize column data to zero */
369 jc bad_ram
370 cmpb %ah,%al /* verify all 4 bytes of dword equal */
371 jnz bad_ram
372 movl %eax,%edx
373 shrl $16,%edx
374 cmpw %dx,%ax
375 jnz bad_ram
wdenk2262cfe2002-11-18 00:14:45 +0000376 /*
377 * merge bank and col data together
378 */
wdenk8bde7f72003-06-27 21:31:46 +0000379 addw %di,%dx /* merge of bank and col info in dl */
wdenk2262cfe2002-11-18 00:14:45 +0000380 /*
381 * fix ending addr mask based upon col info
382 */
wdenk8bde7f72003-06-27 21:31:46 +0000383 movb $3,%al
384 subb %dh,%al /* dh contains the overflow from the bank/col merge */
385 movb %bl,%dh /* bl contains the row mask (aa, 07, 0f, 1f or 3f) */
386 xchgw %cx,%ax /* cx = ax = 3 or 2 depending on 2 or 4 bank device */
387 shrb %cl,%dh /* */
388 incb %dh /* ending addr is 1 greater than real end */
389 xchgw %cx,%ax /* cx is bank number again */
wdenk2262cfe2002-11-18 00:14:45 +0000390 /*
391 * issue all banks precharge
392 */
wdenk8bde7f72003-06-27 21:31:46 +0000393bad_reint:
394 movl $DRCCTL, %esi /* setup DRAM control register with */
395 movb $0x2,%al /* All banks precharge */
wdenk7a8e9bed2003-05-31 18:35:21 +0000396 movb %al, (%esi)
wdenk8bde7f72003-06-27 21:31:46 +0000397 movl $CACHELINESZ, %esi /* address to init read buffer */
wdenk7a8e9bed2003-05-31 18:35:21 +0000398 movw %ax, (%esi)
wdenk2262cfe2002-11-18 00:14:45 +0000399
400 /*
401 * update ENDING ADDRESS REGISTER
402 */
wdenk8bde7f72003-06-27 21:31:46 +0000403 movl $DRCBENDADR, %edi /* DRAM ending address register */
404 movl %ecx,%ebx
wdenk2262cfe2002-11-18 00:14:45 +0000405 addl %ebx, %edi
wdenk7a8e9bed2003-05-31 18:35:21 +0000406 movb %dh, (%edi)
wdenk2262cfe2002-11-18 00:14:45 +0000407 /*
408 * update CONFIG REGISTER
409 */
wdenk8bde7f72003-06-27 21:31:46 +0000410 xorb %dh,%dh
411 movw $0x00f,%bx
412 movw %cx,%ax
413 shlw $2,%ax
414 xchgw %cx,%ax
415 shlw %cl,%dx
416 shlw %cl,%bx
417 notw %bx
418 xchgw %cx,%ax
419 movl $DRCCFG, %edi
wdenk7a8e9bed2003-05-31 18:35:21 +0000420 mov (%edi), %ax
wdenk8bde7f72003-06-27 21:31:46 +0000421 andw %bx,%ax
422 orw %dx,%ax
wdenk7a8e9bed2003-05-31 18:35:21 +0000423 movw %ax, (%edi)
wdenk8bde7f72003-06-27 21:31:46 +0000424 jcxz cleanup
wdenk2262cfe2002-11-18 00:14:45 +0000425
wdenk8bde7f72003-06-27 21:31:46 +0000426 decw %cx
427 movl %ecx,%ebx
428 movl $DRCBENDADR, %edi /* DRAM ending address register */
429 movb $0xff,%al
wdenk2262cfe2002-11-18 00:14:45 +0000430 addl %ebx, %edi
wdenk7a8e9bed2003-05-31 18:35:21 +0000431 movb %al, (%edi)
wdenk2262cfe2002-11-18 00:14:45 +0000432 /*
wdenk8bde7f72003-06-27 21:31:46 +0000433 * set control register to NORMAL mode
wdenk2262cfe2002-11-18 00:14:45 +0000434 */
wdenk8bde7f72003-06-27 21:31:46 +0000435 movl $DRCCTL, %esi /* setup DRAM control register with */
436 movb $0x0,%al /* Normal mode value */
wdenk7a8e9bed2003-05-31 18:35:21 +0000437 movb %al, (%esi)
wdenk8bde7f72003-06-27 21:31:46 +0000438 movl $CACHELINESZ, %esi /* address to init read buffer */
wdenk7a8e9bed2003-05-31 18:35:21 +0000439 movw %ax, (%esi)
wdenk8bde7f72003-06-27 21:31:46 +0000440 jmp nextbank
wdenk2262cfe2002-11-18 00:14:45 +0000441
wdenk8bde7f72003-06-27 21:31:46 +0000442cleanup:
443 movl $DRCBENDADR, %edi /* DRAM ending address register */
444 movw $4,%cx
445 xorw %ax,%ax
446cleanuplp:
wdenk7a8e9bed2003-05-31 18:35:21 +0000447 movb (%edi), %al
wdenk8bde7f72003-06-27 21:31:46 +0000448 orb %al,%al
449 jz emptybank
wdenk2262cfe2002-11-18 00:14:45 +0000450
wdenk8bde7f72003-06-27 21:31:46 +0000451 addb %ah,%al
452 jns nottoomuch
wdenk2262cfe2002-11-18 00:14:45 +0000453
wdenk8bde7f72003-06-27 21:31:46 +0000454 movb $0x7f,%al
455nottoomuch:
456 movb %al,%ah
457 orb $0x80,%al
wdenk7a8e9bed2003-05-31 18:35:21 +0000458 movb %al, (%edi)
wdenk8bde7f72003-06-27 21:31:46 +0000459emptybank:
460 incl %edi
461 loop cleanuplp
wdenk2262cfe2002-11-18 00:14:45 +0000462
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200463#if defined CONFIG_SYS_SDRAM_DRCTMCTL
Wolfgang Denk94568b62006-08-14 23:23:06 +0200464 /* just have your hardware desinger _GIVE_ you what you need here! */
Wolfgang Denk16850912006-08-27 18:10:01 +0200465 movl $DRCTMCTL, %edi
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200466 movb $CONFIG_SYS_SDRAM_DRCTMCTL,%al
Wolfgang Denk94568b62006-08-14 23:23:06 +0200467 movb (%edi), %al
468#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200469#if defined(CONFIG_SYS_SDRAM_CAS_LATENCY_2T) || defined(CONFIG_SYS_SDRAM_CAS_LATENCY_3T)
wdenk2262cfe2002-11-18 00:14:45 +0000470 /* set the CAS latency now since it is hard to do
471 * when we run from the RAM */
472 movl $DRCTMCTL, %edi /* DRAM timing register */
wdenk8bde7f72003-06-27 21:31:46 +0000473 movb (%edi), %al
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200474#ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
wdenk2262cfe2002-11-18 00:14:45 +0000475 andb $0xef, %al
476#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200477#ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
wdenk2262cfe2002-11-18 00:14:45 +0000478 orb $0x10, %al
wdenk8bde7f72003-06-27 21:31:46 +0000479#endif
Wolfgang Denk16850912006-08-27 18:10:01 +0200480 movb %al, (%edi)
Wolfgang Denk94568b62006-08-14 23:23:06 +0200481#endif
wdenk2262cfe2002-11-18 00:14:45 +0000482#endif
wdenk8bde7f72003-06-27 21:31:46 +0000483 movl $DRCCTL, %edi /* DRAM Control register */
484 movb $0x3,%al /* Load mode register cmd */
wdenk7a8e9bed2003-05-31 18:35:21 +0000485 movb %al, (%edi)
486 movw %ax, (%esi)
wdenk2262cfe2002-11-18 00:14:45 +0000487
488
wdenk8bde7f72003-06-27 21:31:46 +0000489 movl $DRCCTL, %edi /* DRAM Control register */
490 movb $0x18,%al /* Enable refresh and NORMAL mode */
wdenk7a8e9bed2003-05-31 18:35:21 +0000491 movb %al, (%edi)
wdenk2262cfe2002-11-18 00:14:45 +0000492
wdenk8bde7f72003-06-27 21:31:46 +0000493 jmp dram_done
wdenk2262cfe2002-11-18 00:14:45 +0000494
wdenk8bde7f72003-06-27 21:31:46 +0000495bad_ram:
496 xorl %edx,%edx
497 xorl %edi,%edi
498 jmp bad_reint
wdenk2262cfe2002-11-18 00:14:45 +0000499
wdenk8bde7f72003-06-27 21:31:46 +0000500dram_done:
501
wdenk2262cfe2002-11-18 00:14:45 +0000502 /* readback DRCBENDADR and return the number
wdenk8bde7f72003-06-27 21:31:46 +0000503 * of available ram bytes in %eax */
wdenk2262cfe2002-11-18 00:14:45 +0000504
wdenk8bde7f72003-06-27 21:31:46 +0000505 movl $DRCBENDADR, %edi /* DRAM ending address register */
506
wdenk2262cfe2002-11-18 00:14:45 +0000507 movl (%edi), %eax
508 movl %eax, %ecx
509 andl $0x80000000, %ecx
510 jz bank2
511 andl $0x7f000000, %eax
wdenk8bde7f72003-06-27 21:31:46 +0000512 shrl $2, %eax
wdenk2262cfe2002-11-18 00:14:45 +0000513 movl %eax, %ebx
514
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200515bank2: movl (%edi), %eax
wdenk2262cfe2002-11-18 00:14:45 +0000516 movl %eax, %ecx
517 andl $0x00800000, %ecx
518 jz bank1
519 andl $0x007f0000, %eax
wdenk8bde7f72003-06-27 21:31:46 +0000520 shll $6, %eax
wdenk2262cfe2002-11-18 00:14:45 +0000521 movl %eax, %ebx
522
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200523bank1: movl (%edi), %eax
wdenk2262cfe2002-11-18 00:14:45 +0000524 movl %eax, %ecx
525 andl $0x00008000, %ecx
526 jz bank0
527 andl $0x00007f00, %eax
wdenk8bde7f72003-06-27 21:31:46 +0000528 shll $14, %eax
wdenk2262cfe2002-11-18 00:14:45 +0000529 movl %eax, %ebx
530
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200531bank0: movl (%edi), %eax
wdenk2262cfe2002-11-18 00:14:45 +0000532 movl %eax, %ecx
533 andl $0x00000080, %ecx
534 jz done
535 andl $0x0000007f, %eax
wdenk8bde7f72003-06-27 21:31:46 +0000536 shll $22, %eax
wdenk2262cfe2002-11-18 00:14:45 +0000537 movl %eax, %ebx
538
wdenk2262cfe2002-11-18 00:14:45 +0000539
Wolfgang Denk16850912006-08-27 18:10:01 +0200540done:
Wolfgang Denk94568b62006-08-14 23:23:06 +0200541 movl %ebx, %eax
542
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200543#if CONFIG_SYS_SDRAM_ECC_ENABLE
Wolfgang Denk94568b62006-08-14 23:23:06 +0200544 /* A nominal memory test: just a byte at each address line */
545 movl %eax, %ecx
546 shrl $0x1, %ecx
547 movl $0x1, %edi
548memtest0:
549 movb $0xa5, (%edi)
Wolfgang Denk16850912006-08-27 18:10:01 +0200550 cmpb $0xa5, (%edi)
Wolfgang Denk94568b62006-08-14 23:23:06 +0200551 jne out
552 shrl $1, %ecx
553 andl %ecx,%ecx
554 jz set_ecc
555 shll $1, %edi
556 jmp memtest0
557
558set_ecc:
559 /* clear all ram with a memset */
560 movl %eax, %ecx
561 xorl %esi, %esi
562 xorl %edi, %edi
563 xorl %eax, %eax
564 shrl $2, %ecx
565 cld
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200566 rep stosl
Wolfgang Denk94568b62006-08-14 23:23:06 +0200567 /* enable read, write buffers */
568 movb $0x11, %al
569 movl $DBCTL, %edi
570 movb %al, (%edi)
571 /* enable NMI mapping for ECC */
572 movl $ECCINT, %edi
573 mov $0x10, %al
Wolfgang Denk16850912006-08-27 18:10:01 +0200574 movb %al, (%edi)
Wolfgang Denk94568b62006-08-14 23:23:06 +0200575 /* Turn on ECC */
576 movl $ECCCTL, %edi
577 mov $0x05, %al
Wolfgang Denk16850912006-08-27 18:10:01 +0200578 movb %al, (%edi)
Wolfgang Denk94568b62006-08-14 23:23:06 +0200579#endif
580out:
581 movl %ebx, %eax
wdenk2262cfe2002-11-18 00:14:45 +0000582 jmp *%ebp
wdenk7a8e9bed2003-05-31 18:35:21 +0000583
wdenk7a8e9bed2003-05-31 18:35:21 +0000584#endif /* CONFIG_SC520 */