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Luca Ceresolifb6e1f12011-04-20 11:02:08 -04001/*
2 * (C) Copyright 2011 Comelit Group SpA
3 * Luca Ceresoli <luca.ceresoli@comelit.it>
4 *
5 * Based on omap3_beagle.h:
6 * (C) Copyright 2006-2008
7 * Texas Instruments.
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 *
11 * Configuration settings for the Comelit DIG297 board.
12 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020013 * SPDX-License-Identifier: GPL-2.0+
Luca Ceresolifb6e1f12011-04-20 11:02:08 -040014 */
15
16#ifndef __CONFIG_H
17#define __CONFIG_H
18
Luca Ceresoli30dca9d2011-11-04 13:42:09 -040019#include <asm/mach-types.h>
20#ifdef MACH_TYPE_OMAP3_CPS
21#error "MACH_TYPE_OMAP3_CPS has been defined properly, please remove this."
22#else
23#define MACH_TYPE_OMAP3_CPS 2751
24#endif
25#define CONFIG_MACH_TYPE MACH_TYPE_OMAP3_CPS
26
Luca Ceresolifb6e1f12011-04-20 11:02:08 -040027/*
28 * High Level Configuration Options
29 */
Luca Ceresolifb6e1f12011-04-20 11:02:08 -040030#define CONFIG_OMAP /* in a TI OMAP core */
31#define CONFIG_OMAP34XX /* which is a 34XX */
Marek Vasut308252a2012-07-21 05:02:23 +000032#define CONFIG_OMAP_GPIO
Lokesh Vutla806d2792013-07-30 11:36:30 +053033#define CONFIG_OMAP_COMMON
Luca Ceresolifb6e1f12011-04-20 11:02:08 -040034
35#define CONFIG_SYS_TEXT_BASE 0x80008000
36
37#define CONFIG_SDRC /* The chip has SDRC controller */
38
39#include <asm/arch/cpu.h> /* get chip and board defs */
40#include <asm/arch/omap3.h>
41
42/*
43 * Display CPU and Board information
44 */
45#define CONFIG_DISPLAY_CPUINFO
46#define CONFIG_DISPLAY_BOARDINFO
47
48/* Clock Defines */
49#define V_OSCK 26000000 /* Clock output from T2 */
50#define V_SCLK (V_OSCK >> 1)
51
Luca Ceresolifb6e1f12011-04-20 11:02:08 -040052#define CONFIG_MISC_INIT_R
53
54#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
55#define CONFIG_SETUP_MEMORY_TAGS
56#define CONFIG_INITRD_TAG
57#define CONFIG_REVISION_TAG
58
59/*
60 * Size of malloc() pool
61 */
62#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
63 /* Sector */
64#define CONFIG_SYS_MALLOC_LEN (1024 << 10) /* UBI needs >= 512 kB */
65
66/*
67 * Hardware drivers
68 */
69
70/*
71 * NS16550 Configuration
72 */
73#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
74
75#define CONFIG_SYS_NS16550
76#define CONFIG_SYS_NS16550_SERIAL
77#define CONFIG_SYS_NS16550_REG_SIZE (-4)
78#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
79
80/*
81 * select serial console configuration: UART3 (ttyO2)
82 */
83#define CONFIG_CONS_INDEX 3
84#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
85#define CONFIG_SERIAL3 3
86
87/* allow to overwrite serial and ethaddr */
88#define CONFIG_ENV_OVERWRITE
89#define CONFIG_BAUDRATE 115200
90#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
91 115200}
Tom Rinieaff60d2011-09-03 21:50:05 -040092#define CONFIG_GENERIC_MMC 1
93#define CONFIG_MMC 1
94#define CONFIG_OMAP_HSMMC 1
Luca Ceresolifb6e1f12011-04-20 11:02:08 -040095#define CONFIG_DOS_PARTITION
96
Luca Ceresolifb6e1f12011-04-20 11:02:08 -040097/* library portions to compile in */
98#define CONFIG_RBTREE
99#define CONFIG_MTD_PARTITIONS
100#define CONFIG_LZO
101
102/* commands to include */
103#include <config_cmd_default.h>
104
105#define CONFIG_CMD_FAT /* FAT support */
106#define CONFIG_CMD_UBI /* UBI Support */
107#define CONFIG_CMD_UBIFS /* UBIFS Support */
108#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
109#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
110#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
111#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:896k(uboot),"\
112 "128k(uboot-env),3m(kernel),252m(ubi)"
113
114#define CONFIG_CMD_I2C /* I2C serial bus support */
115#define CONFIG_CMD_MMC /* MMC support */
116#define CONFIG_CMD_NAND /* NAND support */
117
118#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
119#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
120#undef CONFIG_CMD_IMI /* iminfo */
121#undef CONFIG_CMD_IMLS /* List all found images */
122#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
123#undef CONFIG_CMD_NFS /* NFS support */
124
125#define CONFIG_SYS_NO_FLASH
126#define CONFIG_HARD_I2C
127#define CONFIG_SYS_I2C_SPEED 100000
128#define CONFIG_SYS_I2C_SLAVE 1
Luca Ceresolifb6e1f12011-04-20 11:02:08 -0400129#define CONFIG_DRIVER_OMAP34XX_I2C 1
130
131/*
132 * TWL4030
133 */
134#define CONFIG_TWL4030_POWER
135#define CONFIG_TWL4030_LED
136
137/*
138 * Board NAND Info.
139 */
140#define CONFIG_NAND_OMAP_GPMC
141#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
142 /* to access nand */
143#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
144 /* to access nand at */
145 /* CS0 */
146#define GPMC_NAND_ECC_LP_x16_LAYOUT
147
148#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
149
150#if defined(CONFIG_CMD_NET)
151/*
152 * SMSC9220 Ethernet
153 */
154
Luca Ceresolifb6e1f12011-04-20 11:02:08 -0400155#define CONFIG_SMC911X
156#define CONFIG_SMC911X_32_BIT
157#define CONFIG_SMC911X_BASE 0x2C000000
158
159#endif /* (CONFIG_CMD_NET) */
160
161/* Environment information */
162#define CONFIG_BOOTDELAY 1
163
164#define CONFIG_EXTRA_ENV_SETTINGS \
165 "loadaddr=0x82000000\0" \
166 "console=ttyO2,115200n8\0" \
167 "mtdids=" MTDIDS_DEFAULT "\0" \
168 "mtdparts=" MTDPARTS_DEFAULT "\0" \
169 "partition=nand0,3\0"\
170 "mmcroot=/dev/mmcblk0p2 rw\0" \
171 "mmcrootfstype=ext3 rootwait\0" \
172 "nandroot=ubi0:rootfs ro\0" \
173 "nandrootfstype=ubifs\0" \
174 "nfspath=/srv/nfs\0" \
175 "tftpfilename=uImage\0" \
176 "gatewayip=0.0.0.0\0" \
177 "mmcargs=setenv bootargs console=${console} " \
178 "${mtdparts} " \
179 "root=${mmcroot} " \
180 "rootfstype=${mmcrootfstype} " \
181 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
182 "${netmask}:${hostname}::off\0" \
183 "nandargs=setenv bootargs console=${console} " \
184 "${mtdparts} " \
185 "ubi.mtd=3 " \
186 "root=${nandroot} " \
187 "rootfstype=${nandrootfstype} " \
188 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
189 "${netmask}:${hostname}::off\0" \
190 "netargs=setenv bootargs console=${console} " \
191 "${mtdparts} " \
192 "root=/dev/nfs rw " \
193 "nfsroot=${serverip}:${nfspath} " \
194 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
195 "${netmask}:${hostname}::off\0" \
196 "mmcboot=echo Booting from mmc ...; " \
197 "run mmcargs; " \
198 "bootm ${loadaddr}\0" \
199 "nandboot=echo Booting from nand ...; " \
200 "run nandargs; " \
201 "nand read ${loadaddr} 100000 300000; " \
202 "bootm ${loadaddr}\0" \
203 "netboot=echo Booting from network ...; " \
204 "run netargs; " \
205 "tftp ${loadaddr} ${serverip}:${tftpfilename}; " \
206 "bootm ${loadaddr}\0" \
207 "resetenv=nand erase e0000 20000\0"\
208
209#define CONFIG_BOOTCOMMAND \
210 "run nandboot"
211
212#define CONFIG_AUTO_COMPLETE
213/*
214 * Miscellaneous configurable options
215 */
216#define CONFIG_SYS_LONGHELP /* undef to save memory */
217#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
Luca Ceresolifb6e1f12011-04-20 11:02:08 -0400218#define CONFIG_SYS_PROMPT "DIG297# "
219#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
220/* Print Buffer Size */
221#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
222 sizeof(CONFIG_SYS_PROMPT) + 16)
223#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
224/* Boot Argument Buffer Size */
225#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
226
227#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
228 /* works on */
229#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
230 0x01F00000) /* 31MB */
231
232#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
233 /* load address */
234
235/*
236 * OMAP3 has 12 GP timers, they can be driven by the system clock
237 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
238 * This rate is divided by a local divisor.
239 */
240#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
241#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
242#define CONFIG_SYS_HZ 1000
243
244/*-----------------------------------------------------------------------
Luca Ceresolifb6e1f12011-04-20 11:02:08 -0400245 * Physical Memory Map
246 */
247#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
248#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
Luca Ceresolifb6e1f12011-04-20 11:02:08 -0400249#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
250
Luca Ceresolifb6e1f12011-04-20 11:02:08 -0400251/*-----------------------------------------------------------------------
252 * FLASH and environment organization
253 */
254
255/* **** PISMO SUPPORT *** */
256
257/* Configure the PISMO */
258#define PISMO1_NAND_SIZE GPMC_SIZE_128M
259
260#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
261
262#define CONFIG_SYS_FLASH_BASE boot_flash_base
263
264/* Monitor at start of flash */
265#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
266
267#define CONFIG_ENV_IS_IN_NAND
268#define SMNAND_ENV_OFFSET 0x0E0000 /* environment starts here */
269
270#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
271#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
272#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
273
274#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
275#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
276#define CONFIG_SYS_INIT_RAM_SIZE 0x800
277#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
278 CONFIG_SYS_INIT_RAM_SIZE - \
279 GENERATED_GBL_DATA_SIZE)
280
281#endif /* __CONFIG_H */