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wdenkc0218802003-03-27 12:09:35 +00001/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkc0218802003-03-27 12:09:35 +00006 */
7
8#include <common.h>
9#include <command.h>
Ben Warren8218bd22008-08-31 10:16:59 -070010#include <netdev.h>
wdenkc0218802003-03-27 12:09:35 +000011#include <asm/addrspace.h>
12#include <asm/inca-ip.h>
Jean-Christophe PLAGNIOL-VILLARD5c150102007-11-13 09:11:05 +010013#include <asm/io.h>
Shinya Kuribayashib0c66af2008-03-25 21:30:07 +090014#include <asm/reboot.h>
wdenkc0218802003-03-27 12:09:35 +000015
wdenk85ec0bc2003-03-31 16:34:49 +000016extern uint incaip_get_cpuclk(void);
17
Shinya Kuribayashib0c66af2008-03-25 21:30:07 +090018void _machine_restart(void)
19{
20 *INCA_IP_WDT_RST_REQ = 0x3f;
21}
22
wdenkc0218802003-03-27 12:09:35 +000023static ulong max_sdram_size(void)
24{
25 /* The only supported SDRAM data width is 16bit.
26 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020027#define CONFIG_SYS_DW 2
wdenkc0218802003-03-27 12:09:35 +000028
29 /* The only supported number of SDRAM banks is 4.
30 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020031#define CONFIG_SYS_NB 4
wdenkc0218802003-03-27 12:09:35 +000032
33 ulong cfgpb0 = *INCA_IP_SDRAM_MC_CFGPB0;
34 int cols = cfgpb0 & 0xF;
35 int rows = (cfgpb0 & 0xF0) >> 4;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020036 ulong size = (1 << (rows + cols)) * CONFIG_SYS_DW * CONFIG_SYS_NB;
wdenkc0218802003-03-27 12:09:35 +000037
38 return size;
39}
40
Becky Bruce9973e3c2008-06-09 16:03:40 -050041phys_size_t initdram(int board_type)
wdenkc0218802003-03-27 12:09:35 +000042{
43 int rows, cols, best_val = *INCA_IP_SDRAM_MC_CFGPB0;
44 ulong size, max_size = 0;
45 ulong our_address;
46
47 asm volatile ("move %0, $25" : "=r" (our_address) :);
48
49 /* Can't probe for RAM size unless we are running from Flash.
50 */
Shinya Kuribayashi7daf2eb2008-06-05 22:29:00 +090051 if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1))
wdenkc0218802003-03-27 12:09:35 +000052 {
53 return max_sdram_size();
54 }
55
56 for (cols = 0x8; cols <= 0xC; cols++)
57 {
58 for (rows = 0xB; rows <= 0xD; rows++)
59 {
60 *INCA_IP_SDRAM_MC_CFGPB0 = (0x14 << 8) |
Wolfgang Denk93e14592013-10-04 17:43:24 +020061 (rows << 4) | cols;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020062 size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
Wolfgang Denk93e14592013-10-04 17:43:24 +020063 max_sdram_size());
wdenkc0218802003-03-27 12:09:35 +000064
65 if (size > max_size)
66 {
67 best_val = *INCA_IP_SDRAM_MC_CFGPB0;
68 max_size = size;
69 }
70 }
71 }
72
73 *INCA_IP_SDRAM_MC_CFGPB0 = best_val;
74 return max_size;
75}
76
wdenk85ec0bc2003-03-31 16:34:49 +000077int checkboard (void)
78{
wdenk85ec0bc2003-03-31 16:34:49 +000079 unsigned long chipid = *INCA_IP_WDT_CHIPID;
80 int part_num;
81
82 puts ("Board: INCA-IP ");
83 part_num = (chipid >> 12) & 0xffff;
84 switch (part_num) {
85 case 0xc0:
86 printf ("Standard Version, ");
87 break;
88 case 0xc1:
89 printf ("Basic Version, ");
90 break;
91 default:
92 printf ("Unknown Part Number 0x%x ", part_num);
93 break;
94 }
95
96 printf ("Chip V1.%ld, ", (chipid >> 28));
97
98 printf("CPU Speed %d MHz\n", incaip_get_cpuclk()/1000000);
99
Jean-Christophe PLAGNIOL-VILLARD5c150102007-11-13 09:11:05 +0100100 set_io_port_base(0);
101
wdenk85ec0bc2003-03-31 16:34:49 +0000102 return 0;
103}
Ben Warren8218bd22008-08-31 10:16:59 -0700104
105#if defined(CONFIG_INCA_IP_SWITCH)
106int board_eth_init(bd_t *bis)
107{
108 return inca_switch_initialize(bis);
109}
110#endif