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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
wdenk71f95112003-06-15 22:40:42 +00002/*
Jerry Huang4a6ee172010-11-25 17:06:07 +00003 * Copyright 2008,2010 Freescale Semiconductor, Inc
Andy Fleming272cc702008-10-30 16:41:01 -05004 * Andy Fleming
5 *
6 * Based (loosely) on the Linux code
wdenk71f95112003-06-15 22:40:42 +00007 */
8
9#ifndef _MMC_H_
10#define _MMC_H_
wdenk71f95112003-06-15 22:40:42 +000011
Simon Glasscd93d622020-05-10 11:40:13 -060012#include <linux/bitops.h>
Andy Fleming272cc702008-10-30 16:41:01 -050013#include <linux/list.h>
Peng Fan3697e592016-09-01 11:13:38 +080014#include <linux/sizes.h>
Lad, Prabhakar0d986e62012-06-24 21:35:20 +000015#include <linux/compiler.h>
Masahiro Yamadaa7b2b6c2020-02-14 16:40:25 +090016#include <linux/dma-direction.h>
Mateusz Zalega07a2d422014-04-30 13:04:15 +020017#include <part.h>
Andy Fleming272cc702008-10-30 16:41:01 -050018
Masahiro Yamadabd602c52020-02-25 02:25:30 +090019struct bd_info;
20
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +010021#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
22#define MMC_SUPPORTS_TUNING
23#endif
24#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
25#define MMC_SUPPORTS_TUNING
26#endif
27
Pantelis Antoniou4b7cee52015-01-23 12:12:01 +020028/* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */
29#define SD_VERSION_SD (1U << 31)
30#define MMC_VERSION_MMC (1U << 30)
31
32#define MAKE_SDMMC_VERSION(a, b, c) \
33 ((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c))
34#define MAKE_SD_VERSION(a, b, c) \
35 (SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c))
36#define MAKE_MMC_VERSION(a, b, c) \
37 (MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c))
38
39#define EXTRACT_SDMMC_MAJOR_VERSION(x) \
40 (((u32)(x) >> 16) & 0xff)
41#define EXTRACT_SDMMC_MINOR_VERSION(x) \
42 (((u32)(x) >> 8) & 0xff)
43#define EXTRACT_SDMMC_CHANGE_VERSION(x) \
44 ((u32)(x) & 0xff)
45
46#define SD_VERSION_3 MAKE_SD_VERSION(3, 0, 0)
47#define SD_VERSION_2 MAKE_SD_VERSION(2, 0, 0)
48#define SD_VERSION_1_0 MAKE_SD_VERSION(1, 0, 0)
49#define SD_VERSION_1_10 MAKE_SD_VERSION(1, 10, 0)
50
51#define MMC_VERSION_UNKNOWN MAKE_MMC_VERSION(0, 0, 0)
52#define MMC_VERSION_1_2 MAKE_MMC_VERSION(1, 2, 0)
53#define MMC_VERSION_1_4 MAKE_MMC_VERSION(1, 4, 0)
54#define MMC_VERSION_2_2 MAKE_MMC_VERSION(2, 2, 0)
55#define MMC_VERSION_3 MAKE_MMC_VERSION(3, 0, 0)
56#define MMC_VERSION_4 MAKE_MMC_VERSION(4, 0, 0)
57#define MMC_VERSION_4_1 MAKE_MMC_VERSION(4, 1, 0)
58#define MMC_VERSION_4_2 MAKE_MMC_VERSION(4, 2, 0)
59#define MMC_VERSION_4_3 MAKE_MMC_VERSION(4, 3, 0)
Jean-Jacques Hiblotace1bed2018-02-09 12:09:28 +010060#define MMC_VERSION_4_4 MAKE_MMC_VERSION(4, 4, 0)
Pantelis Antoniou4b7cee52015-01-23 12:12:01 +020061#define MMC_VERSION_4_41 MAKE_MMC_VERSION(4, 4, 1)
62#define MMC_VERSION_4_5 MAKE_MMC_VERSION(4, 5, 0)
63#define MMC_VERSION_5_0 MAKE_MMC_VERSION(5, 0, 0)
Stefan Wahren1a3619c2016-06-16 17:54:06 +000064#define MMC_VERSION_5_1 MAKE_MMC_VERSION(5, 1, 0)
Andy Fleming272cc702008-10-30 16:41:01 -050065
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +020066#define MMC_CAP(mode) (1 << mode)
67#define MMC_MODE_HS (MMC_CAP(MMC_HS) | MMC_CAP(SD_HS))
68#define MMC_MODE_HS_52MHz MMC_CAP(MMC_HS_52)
69#define MMC_MODE_DDR_52MHz MMC_CAP(MMC_DDR_52)
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +020070#define MMC_MODE_HS200 MMC_CAP(MMC_HS_200)
Peng Fan3dd26262018-08-10 14:07:54 +080071#define MMC_MODE_HS400 MMC_CAP(MMC_HS_400)
Peng Fan44acd492019-07-10 14:43:07 +080072#define MMC_MODE_HS400_ES MMC_CAP(MMC_HS_400_ES)
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +020073
T Karthik Reddy86a94e72019-06-25 13:39:02 +020074#define MMC_CAP_NONREMOVABLE BIT(14)
75#define MMC_CAP_NEEDS_POLL BIT(15)
76#define MMC_CAP_CD_ACTIVE_HIGH BIT(16)
77
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +020078#define MMC_MODE_8BIT BIT(30)
79#define MMC_MODE_4BIT BIT(29)
Jean-Jacques Hiblotd0c221f2017-09-21 16:29:57 +020080#define MMC_MODE_1BIT BIT(28)
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +020081#define MMC_MODE_SPI BIT(27)
82
Łukasz Majewski62722032012-03-12 22:07:18 +000083
Andy Fleming272cc702008-10-30 16:41:01 -050084#define SD_DATA_4BIT 0x00040000
85
Pantelis Antoniou4b7cee52015-01-23 12:12:01 +020086#define IS_SD(x) ((x)->version & SD_VERSION_SD)
Andrew Gabbasov3f2da752015-03-19 07:44:02 -050087#define IS_MMC(x) ((x)->version & MMC_VERSION_MMC)
Andy Fleming272cc702008-10-30 16:41:01 -050088
89#define MMC_DATA_READ 1
90#define MMC_DATA_WRITE 2
91
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020092#define MMC_CMD_GO_IDLE_STATE 0
93#define MMC_CMD_SEND_OP_COND 1
94#define MMC_CMD_ALL_SEND_CID 2
95#define MMC_CMD_SET_RELATIVE_ADDR 3
96#define MMC_CMD_SET_DSR 4
Andy Fleming272cc702008-10-30 16:41:01 -050097#define MMC_CMD_SWITCH 6
Haavard Skinnemoen341188b2008-05-22 11:09:59 +020098#define MMC_CMD_SELECT_CARD 7
Andy Fleming272cc702008-10-30 16:41:01 -050099#define MMC_CMD_SEND_EXT_CSD 8
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200100#define MMC_CMD_SEND_CSD 9
101#define MMC_CMD_SEND_CID 10
Andy Fleming272cc702008-10-30 16:41:01 -0500102#define MMC_CMD_STOP_TRANSMISSION 12
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200103#define MMC_CMD_SEND_STATUS 13
104#define MMC_CMD_SET_BLOCKLEN 16
105#define MMC_CMD_READ_SINGLE_BLOCK 17
106#define MMC_CMD_READ_MULTIPLE_BLOCK 18
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200107#define MMC_CMD_SEND_TUNING_BLOCK 19
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +0200108#define MMC_CMD_SEND_TUNING_BLOCK_HS200 21
Pierre Aubert91fdabc2014-04-24 10:30:06 +0200109#define MMC_CMD_SET_BLOCK_COUNT 23
Andy Fleming272cc702008-10-30 16:41:01 -0500110#define MMC_CMD_WRITE_SINGLE_BLOCK 24
111#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
Lei Wene6f99a52011-06-22 17:03:31 +0000112#define MMC_CMD_ERASE_GROUP_START 35
113#define MMC_CMD_ERASE_GROUP_END 36
114#define MMC_CMD_ERASE 38
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200115#define MMC_CMD_APP_CMD 55
Thomas Choud52ebf12010-12-24 13:12:21 +0000116#define MMC_CMD_SPI_READ_OCR 58
117#define MMC_CMD_SPI_CRC_ON_OFF 59
Amar3690d6d2013-04-27 11:42:58 +0530118#define MMC_CMD_RES_MAN 62
119
120#define MMC_CMD62_ARG1 0xefac62ec
121#define MMC_CMD62_ARG2 0xcbaea7
122
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200123
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200124#define SD_CMD_SEND_RELATIVE_ADDR 3
Andy Fleming272cc702008-10-30 16:41:01 -0500125#define SD_CMD_SWITCH_FUNC 6
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200126#define SD_CMD_SEND_IF_COND 8
Otavio Salvadorf022d362015-02-17 10:42:43 -0200127#define SD_CMD_SWITCH_UHS18V 11
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200128
129#define SD_CMD_APP_SET_BUS_WIDTH 6
Peng Fan3697e592016-09-01 11:13:38 +0800130#define SD_CMD_APP_SD_STATUS 13
Lei Wene6f99a52011-06-22 17:03:31 +0000131#define SD_CMD_ERASE_WR_BLK_START 32
132#define SD_CMD_ERASE_WR_BLK_END 33
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200133#define SD_CMD_APP_SEND_OP_COND 41
Andy Fleming272cc702008-10-30 16:41:01 -0500134#define SD_CMD_APP_SEND_SCR 51
135
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +0200136static inline bool mmc_is_tuning_cmd(uint cmdidx)
137{
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200138 if ((cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) ||
139 (cmdidx == MMC_CMD_SEND_TUNING_BLOCK))
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +0200140 return true;
141 return false;
142}
143
Andy Fleming272cc702008-10-30 16:41:01 -0500144/* SCR definitions in different words */
145#define SD_HIGHSPEED_BUSY 0x00020000
146#define SD_HIGHSPEED_SUPPORTED 0x00020000
147
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200148#define UHS_SDR12_BUS_SPEED 0
149#define HIGH_SPEED_BUS_SPEED 1
150#define UHS_SDR25_BUS_SPEED 1
151#define UHS_SDR50_BUS_SPEED 2
152#define UHS_SDR104_BUS_SPEED 3
153#define UHS_DDR50_BUS_SPEED 4
154
155#define SD_MODE_UHS_SDR12 BIT(UHS_SDR12_BUS_SPEED)
156#define SD_MODE_UHS_SDR25 BIT(UHS_SDR25_BUS_SPEED)
157#define SD_MODE_UHS_SDR50 BIT(UHS_SDR50_BUS_SPEED)
158#define SD_MODE_UHS_SDR104 BIT(UHS_SDR104_BUS_SPEED)
159#define SD_MODE_UHS_DDR50 BIT(UHS_DDR50_BUS_SPEED)
160
Thomas Chouabe2c932011-04-19 03:48:31 +0000161#define OCR_BUSY 0x80000000
162#define OCR_HCS 0x40000000
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200163#define OCR_S18R 0x1000000
Raffaele Recalcati31cacba2011-03-11 02:01:13 +0000164#define OCR_VOLTAGE_MASK 0x007FFF80
165#define OCR_ACCESS_MODE 0x60000000
Andy Fleming272cc702008-10-30 16:41:01 -0500166
Eric Nelson1aa2d072015-12-07 07:50:01 -0700167#define MMC_ERASE_ARG 0x00000000
168#define MMC_SECURE_ERASE_ARG 0x80000000
169#define MMC_TRIM_ARG 0x00000001
170#define MMC_DISCARD_ARG 0x00000003
171#define MMC_SECURE_TRIM1_ARG 0x80000001
172#define MMC_SECURE_TRIM2_ARG 0x80008000
Lei Wene6f99a52011-06-22 17:03:31 +0000173
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000174#define MMC_STATUS_MASK (~0x0206BF7F)
Andrew Gabbasov6b2221b2014-04-03 04:34:32 -0500175#define MMC_STATUS_SWITCH_ERROR (1 << 7)
Thomas Chouabe2c932011-04-19 03:48:31 +0000176#define MMC_STATUS_RDY_FOR_DATA (1 << 8)
177#define MMC_STATUS_CURR_STATE (0xf << 9)
Thomas Choued018b22011-04-19 03:48:32 +0000178#define MMC_STATUS_ERROR (1 << 19)
Raffaele Recalcati5d4fc8d2011-03-11 02:01:12 +0000179
Jan Kloetzked617c422012-02-05 22:29:12 +0000180#define MMC_STATE_PRG (7 << 9)
Stefan Bosch8e2b0af2021-01-23 13:37:41 +0100181#define MMC_STATE_TRANS (4 << 9)
Jan Kloetzked617c422012-02-05 22:29:12 +0000182
Andy Fleming272cc702008-10-30 16:41:01 -0500183#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
184#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
185#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
186#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
187#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
188#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
189#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
190#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
191#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
192#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
193#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
194#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
195#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
196#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
197#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
198#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
199#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
200
201#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
202#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
203 addressed by index which are
204 1 in value field */
205#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
206 addressed by index, which are
207 1 in value field */
208#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
209
210#define SD_SWITCH_CHECK 0
211#define SD_SWITCH_SWITCH 1
212
213/*
214 * EXT_CSD fields
215 */
Diego Santa Cruza7f852b2014-12-23 10:50:22 +0100216#define EXT_CSD_ENH_START_ADDR 136 /* R/W */
217#define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */
Stephen Warrenf866a462013-06-11 15:14:01 -0600218#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
Markus Niebeld7b29122014-11-18 15:11:42 +0100219#define EXT_CSD_PARTITION_SETTING 155 /* R/W */
Oliver Metz1937e5a2013-10-01 20:32:07 +0200220#define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +0100221#define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */
Lei Wen0560db12011-10-03 20:35:10 +0000222#define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
Tom Rini33ace362014-02-07 14:15:20 -0500223#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
Tomas Melincd3d4882016-11-25 11:01:03 +0200224#define EXT_CSD_BKOPS_EN 163 /* R/W & R/W/E */
Diego Santa Cruz8dda5b0e2014-12-23 10:50:31 +0100225#define EXT_CSD_WR_REL_PARAM 166 /* R */
226#define EXT_CSD_WR_REL_SET 167 /* R/W */
Stephen Warrenf866a462013-06-11 15:14:01 -0600227#define EXT_CSD_RPMB_MULT 168 /* RO */
Heinrich Schuchardt9abfe332020-03-30 07:24:16 +0200228#define EXT_CSD_USER_WP 171 /* R/W & R/W/C_P & R/W/E_P */
229#define EXT_CSD_BOOT_WP 173 /* R/W & R/W/C_P */
230#define EXT_CSD_BOOT_WP_STATUS 174 /* R */
Lei Wen0560db12011-10-03 20:35:10 +0000231#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
Amar3690d6d2013-04-27 11:42:58 +0530232#define EXT_CSD_BOOT_BUS_WIDTH 177
Lei Wen0560db12011-10-03 20:35:10 +0000233#define EXT_CSD_PART_CONF 179 /* R/W */
234#define EXT_CSD_BUS_WIDTH 183 /* R/W */
Peng Fan44acd492019-07-10 14:43:07 +0800235#define EXT_CSD_STROBE_SUPPORT 184 /* R/W */
Lei Wen0560db12011-10-03 20:35:10 +0000236#define EXT_CSD_HS_TIMING 185 /* R/W */
237#define EXT_CSD_REV 192 /* RO */
238#define EXT_CSD_CARD_TYPE 196 /* RO */
Jean-Jacques Hiblot513e00b2019-07-02 10:53:55 +0200239#define EXT_CSD_PART_SWITCH_TIME 199 /* RO */
Lei Wen0560db12011-10-03 20:35:10 +0000240#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
Stephen Warrenf866a462013-06-11 15:14:01 -0600241#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
Lei Wen0560db12011-10-03 20:35:10 +0000242#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
Stephen Warren8948ea82012-07-30 10:55:43 +0000243#define EXT_CSD_BOOT_MULT 226 /* RO */
Jean-Jacques Hiblot39320c52019-07-02 10:53:54 +0200244#define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */
Tomas Melincd3d4882016-11-25 11:01:03 +0200245#define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
Andy Fleming272cc702008-10-30 16:41:01 -0500246
247/*
248 * EXT_CSD field definitions
249 */
250
Thomas Chouabe2c932011-04-19 03:48:31 +0000251#define EXT_CSD_CMD_SET_NORMAL (1 << 0)
252#define EXT_CSD_CMD_SET_SECURE (1 << 1)
253#define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
Andy Fleming272cc702008-10-30 16:41:01 -0500254
Thomas Chouabe2c932011-04-19 03:48:31 +0000255#define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
256#define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
Jaehoon Chungd22e3d42014-05-16 13:59:54 +0900257#define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2)
258#define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3)
259#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
260 | EXT_CSD_CARD_TYPE_DDR_1_2V)
Andy Fleming272cc702008-10-30 16:41:01 -0500261
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +0200262#define EXT_CSD_CARD_TYPE_HS200_1_8V BIT(4) /* Card can run at 200MHz */
263 /* SDR mode @1.8V I/O */
264#define EXT_CSD_CARD_TYPE_HS200_1_2V BIT(5) /* Card can run at 200MHz */
265 /* SDR mode @1.2V I/O */
266#define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \
267 EXT_CSD_CARD_TYPE_HS200_1_2V)
Peng Fan3dd26262018-08-10 14:07:54 +0800268#define EXT_CSD_CARD_TYPE_HS400_1_8V BIT(6)
269#define EXT_CSD_CARD_TYPE_HS400_1_2V BIT(7)
270#define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \
271 EXT_CSD_CARD_TYPE_HS400_1_2V)
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +0200272
Andy Fleming272cc702008-10-30 16:41:01 -0500273#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
274#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
275#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
Jaehoon Chungd22e3d42014-05-16 13:59:54 +0900276#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
277#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200278#define EXT_CSD_DDR_FLAG BIT(2) /* Flag for DDR mode */
Peng Fan44acd492019-07-10 14:43:07 +0800279#define EXT_CSD_BUS_WIDTH_STROBE BIT(7) /* Enhanced strobe mode */
Haavard Skinnemoen341188b2008-05-22 11:09:59 +0200280
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200281#define EXT_CSD_TIMING_LEGACY 0 /* no high speed */
282#define EXT_CSD_TIMING_HS 1 /* HS */
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +0200283#define EXT_CSD_TIMING_HS200 2 /* HS200 */
Peng Fan3dd26262018-08-10 14:07:54 +0800284#define EXT_CSD_TIMING_HS400 3 /* HS400 */
Peng Fan44acd492019-07-10 14:43:07 +0800285#define EXT_CSD_DRV_STR_SHIFT 4 /* Driver Strength shift */
Kishon Vijay Abraham I634d4842017-09-21 16:30:06 +0200286
Amar3690d6d2013-04-27 11:42:58 +0530287#define EXT_CSD_BOOT_ACK_ENABLE (1 << 6)
288#define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3)
289#define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0)
290#define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0)
291
292#define EXT_CSD_BOOT_ACK(x) (x << 6)
293#define EXT_CSD_BOOT_PART_NUM(x) (x << 3)
294#define EXT_CSD_PARTITION_ACCESS(x) (x << 0)
295
Angelo Dureghellobdb60992017-08-01 14:27:10 +0200296#define EXT_CSD_EXTRACT_BOOT_ACK(x) (((x) >> 6) & 0x1)
297#define EXT_CSD_EXTRACT_BOOT_PART(x) (((x) >> 3) & 0x7)
298#define EXT_CSD_EXTRACT_PARTITION_ACCESS(x) ((x) & 0x7)
299
Tom Rini5a99b9d2014-02-05 10:24:22 -0500300#define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3)
301#define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
302#define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
Amar3690d6d2013-04-27 11:42:58 +0530303
Markus Niebeld7b29122014-11-18 15:11:42 +0100304#define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0)
305
Diego Santa Cruzc3dbb4f2014-12-23 10:50:17 +0100306#define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */
307#define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */
308
Diego Santa Cruz8dda5b0e2014-12-23 10:50:31 +0100309#define EXT_CSD_HS_CTRL_REL (1 << 0) /* host controlled WR_REL_SET */
310
311#define EXT_CSD_WR_DATA_REL_USR (1 << 0) /* user data area WR_REL */
312#define EXT_CSD_WR_DATA_REL_GP(x) (1 << ((x)+1)) /* GP part (x+1) WR_REL */
313
Andy Fleming1de97f92008-10-30 16:31:39 -0500314#define R1_ILLEGAL_COMMAND (1 << 22)
315#define R1_APP_CMD (1 << 5)
316
Andy Fleming272cc702008-10-30 16:41:01 -0500317#define MMC_RSP_PRESENT (1 << 0)
Thomas Chouabe2c932011-04-19 03:48:31 +0000318#define MMC_RSP_136 (1 << 1) /* 136 bit response */
319#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
320#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
321#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
Andy Fleming272cc702008-10-30 16:41:01 -0500322
Thomas Chouabe2c932011-04-19 03:48:31 +0000323#define MMC_RSP_NONE (0)
324#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
Andy Fleming272cc702008-10-30 16:41:01 -0500325#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
326 MMC_RSP_BUSY)
Thomas Chouabe2c932011-04-19 03:48:31 +0000327#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
328#define MMC_RSP_R3 (MMC_RSP_PRESENT)
329#define MMC_RSP_R4 (MMC_RSP_PRESENT)
330#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
331#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
332#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
Andy Fleming272cc702008-10-30 16:41:01 -0500333
Lei Wenbc897b12011-05-02 16:26:26 +0000334#define MMCPART_NOAVAILABLE (0xff)
335#define PART_ACCESS_MASK (0x7)
336#define PART_SUPPORT (0x1)
Diego Santa Cruzc3dbb4f2014-12-23 10:50:17 +0100337#define ENHNCD_SUPPORT (0x2)
Oliver Metz1937e5a2013-10-01 20:32:07 +0200338#define PART_ENH_ATTRIB (0x1f)
wdenk71f95112003-06-15 22:40:42 +0000339
Kishon Vijay Abraham I83dc4222017-09-21 16:30:10 +0200340#define MMC_QUIRK_RETRY_SEND_CID BIT(0)
341#define MMC_QUIRK_RETRY_SET_BLOCKLEN BIT(1)
Joel Johnsond4a5fa32020-01-11 09:08:14 -0700342#define MMC_QUIRK_RETRY_APP_CMD BIT(2)
Kishon Vijay Abraham I83dc4222017-09-21 16:30:10 +0200343
Kishon Vijay Abraham Iaff5d3c2017-09-21 16:30:00 +0200344enum mmc_voltage {
345 MMC_SIGNAL_VOLTAGE_000 = 0,
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +0200346 MMC_SIGNAL_VOLTAGE_120 = 1,
347 MMC_SIGNAL_VOLTAGE_180 = 2,
348 MMC_SIGNAL_VOLTAGE_330 = 4,
Kishon Vijay Abraham Iaff5d3c2017-09-21 16:30:00 +0200349};
350
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +0200351#define MMC_ALL_SIGNAL_VOLTAGE (MMC_SIGNAL_VOLTAGE_120 |\
352 MMC_SIGNAL_VOLTAGE_180 |\
353 MMC_SIGNAL_VOLTAGE_330)
354
Simon Glass8bfa1952013-04-03 08:54:30 +0000355/* Maximum block size for MMC */
356#define MMC_MAX_BLOCK_LEN 512
357
Amar3690d6d2013-04-27 11:42:58 +0530358/* The number of MMC physical partitions. These consist of:
359 * boot partitions (2), general purpose partitions (4) in MMC v4.4.
360 */
361#define MMC_NUM_BOOT_PARTITION 2
Pierre Aubert91fdabc2014-04-24 10:30:06 +0200362#define MMC_PART_RPMB 3 /* RPMB partition number */
Amar3690d6d2013-04-27 11:42:58 +0530363
Ashok Reddy Soma17a42ab2020-10-23 04:58:58 -0600364/* timing specification used */
365#define MMC_TIMING_LEGACY 0
366#define MMC_TIMING_MMC_HS 1
367#define MMC_TIMING_SD_HS 2
368#define MMC_TIMING_UHS_SDR12 3
369#define MMC_TIMING_UHS_SDR25 4
370#define MMC_TIMING_UHS_SDR50 5
371#define MMC_TIMING_UHS_SDR104 6
372#define MMC_TIMING_UHS_DDR50 7
373#define MMC_TIMING_MMC_DDR52 8
374#define MMC_TIMING_MMC_HS200 9
375#define MMC_TIMING_MMC_HS400 10
376
Simon Glasse7ecf7c2015-06-23 15:38:48 -0600377/* Driver model support */
378
379/**
380 * struct mmc_uclass_priv - Holds information about a device used by the uclass
381 */
382struct mmc_uclass_priv {
383 struct mmc *mmc;
384};
385
386/**
387 * mmc_get_mmc_dev() - get the MMC struct pointer for a device
388 *
389 * Provided that the device is already probed and ready for use, this value
390 * will be available.
391 *
392 * @dev: Device
393 * @return associated mmc struct pointer if available, else NULL
394 */
Simon Glass3a905cd2020-04-08 08:33:00 -0600395struct mmc *mmc_get_mmc_dev(const struct udevice *dev);
Simon Glasse7ecf7c2015-06-23 15:38:48 -0600396
397/* End of driver model support */
398
Andy Fleming1de97f92008-10-30 16:31:39 -0500399struct mmc_cid {
400 unsigned long psn;
401 unsigned short oid;
402 unsigned char mid;
403 unsigned char prv;
404 unsigned char mdt;
405 char pnm[7];
406};
407
Andy Fleming272cc702008-10-30 16:41:01 -0500408struct mmc_cmd {
409 ushort cmdidx;
410 uint resp_type;
411 uint cmdarg;
Rabin Vincent0b453ff2009-04-05 13:30:55 +0530412 uint response[4];
Andy Fleming272cc702008-10-30 16:41:01 -0500413};
414
415struct mmc_data {
416 union {
417 char *dest;
418 const char *src; /* src buffers don't get written to */
419 };
420 uint flags;
421 uint blocks;
422 uint blocksize;
423};
424
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200425/* forward decl. */
426struct mmc;
427
Simon Glasse7881d82017-07-29 11:35:31 -0600428#if CONFIG_IS_ENABLED(DM_MMC)
Simon Glass8ca51e52016-06-12 23:30:22 -0600429struct dm_mmc_ops {
430 /**
Faiz Abbas32860bd2020-02-26 13:44:30 +0530431 * deferred_probe() - Some configurations that need to be deferred
432 * to just before enumerating the device
433 *
434 * @dev: Device to init
435 * @return 0 if Ok, -ve if error
436 */
437 int (*deferred_probe)(struct udevice *dev);
438 /**
Yangbo Lu390f9bd2020-09-01 16:57:59 +0800439 * reinit() - Re-initialization to clear old configuration for
440 * mmc rescan.
441 *
442 * @dev: Device to reinit
443 * @return 0 if Ok, -ve if error
444 */
445 int (*reinit)(struct udevice *dev);
446 /**
Simon Glass8ca51e52016-06-12 23:30:22 -0600447 * send_cmd() - Send a command to the MMC device
448 *
449 * @dev: Device to receive the command
450 * @cmd: Command to send
451 * @data: Additional data to send/receive
452 * @return 0 if OK, -ve on error
453 */
454 int (*send_cmd)(struct udevice *dev, struct mmc_cmd *cmd,
455 struct mmc_data *data);
456
457 /**
458 * set_ios() - Set the I/O speed/width for an MMC device
459 *
460 * @dev: Device to update
461 * @return 0 if OK, -ve on error
462 */
463 int (*set_ios)(struct udevice *dev);
464
465 /**
466 * get_cd() - See whether a card is present
467 *
468 * @dev: Device to check
469 * @return 0 if not present, 1 if present, -ve on error
470 */
471 int (*get_cd)(struct udevice *dev);
472
473 /**
474 * get_wp() - See whether a card has write-protect enabled
475 *
476 * @dev: Device to check
477 * @return 0 if write-enabled, 1 if write-protected, -ve on error
478 */
479 int (*get_wp)(struct udevice *dev);
Kishon Vijay Abraham Iec841202017-09-21 16:30:05 +0200480
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100481#ifdef MMC_SUPPORTS_TUNING
Kishon Vijay Abraham Iec841202017-09-21 16:30:05 +0200482 /**
483 * execute_tuning() - Start the tuning process
484 *
485 * @dev: Device to start the tuning
486 * @opcode: Command opcode to send
487 * @return 0 if OK, -ve on error
488 */
489 int (*execute_tuning)(struct udevice *dev, uint opcode);
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100490#endif
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200491
492 /**
493 * wait_dat0() - wait until dat0 is in the target state
494 * (CLK must be running during the wait)
495 *
496 * @dev: Device to check
497 * @state: target state
Sam Protsenko6cf8a902019-08-14 22:52:51 +0300498 * @timeout_us: timeout in us
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200499 * @return 0 if dat0 is in the target state, -ve on error
500 */
Sam Protsenko6cf8a902019-08-14 22:52:51 +0300501 int (*wait_dat0)(struct udevice *dev, int state, int timeout_us);
Peng Fan44acd492019-07-10 14:43:07 +0800502
503#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
504 /* set_enhanced_strobe() - set HS400 enhanced strobe */
505 int (*set_enhanced_strobe)(struct udevice *dev);
506#endif
Yann Gautier3602a562019-09-19 17:56:12 +0200507
508 /**
509 * host_power_cycle - host specific tasks in power cycle sequence
510 * Called between mmc_power_off() and
511 * mmc_power_on()
512 *
513 * @dev: Device to check
514 * @return 0 if not present, 1 if present, -ve on error
515 */
516 int (*host_power_cycle)(struct udevice *dev);
Marek Vasut145429a2020-04-04 12:45:05 +0200517
518 /**
519 * get_b_max - get maximum length of single transfer
520 * Called before reading blocks from the card,
521 * useful for system which have e.g. DMA limits
522 * on various memory ranges.
523 *
524 * @dev: Device to check
525 * @dst: Destination buffer in memory
526 * @blkcnt: Total number of blocks in this transfer
527 * @return maximum number of blocks for this transfer
528 */
529 int (*get_b_max)(struct udevice *dev, void *dst, lbaint_t blkcnt);
Yangbo Lud271e102020-09-01 16:58:04 +0800530
531 /**
532 * hs400_prepare_ddr - prepare to switch to DDR mode
533 *
534 * @dev: Device to check
535 * @return 0 if success, -ve on error
536 */
537 int (*hs400_prepare_ddr)(struct udevice *dev);
Simon Glass8ca51e52016-06-12 23:30:22 -0600538};
539
540#define mmc_get_ops(dev) ((struct dm_mmc_ops *)(dev)->driver->ops)
541
Simon Glass8ca51e52016-06-12 23:30:22 -0600542/* Transition functions for compatibility */
543int mmc_set_ios(struct mmc *mmc);
544int mmc_getcd(struct mmc *mmc);
545int mmc_getwp(struct mmc *mmc);
Kishon Vijay Abraham Iec841202017-09-21 16:30:05 +0200546int mmc_execute_tuning(struct mmc *mmc, uint opcode);
Sam Protsenko6cf8a902019-08-14 22:52:51 +0300547int mmc_wait_dat0(struct mmc *mmc, int state, int timeout_us);
Peng Fan44acd492019-07-10 14:43:07 +0800548int mmc_set_enhanced_strobe(struct mmc *mmc);
Yann Gautier3602a562019-09-19 17:56:12 +0200549int mmc_host_power_cycle(struct mmc *mmc);
Faiz Abbas32860bd2020-02-26 13:44:30 +0530550int mmc_deferred_probe(struct mmc *mmc);
Yangbo Lu390f9bd2020-09-01 16:57:59 +0800551int mmc_reinit(struct mmc *mmc);
Marek Vasut145429a2020-04-04 12:45:05 +0200552int mmc_get_b_max(struct mmc *mmc, void *dst, lbaint_t blkcnt);
Yangbo Lud271e102020-09-01 16:58:04 +0800553int mmc_hs400_prepare_ddr(struct mmc *mmc);
Simon Glass8ca51e52016-06-12 23:30:22 -0600554#else
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200555struct mmc_ops {
556 int (*send_cmd)(struct mmc *mmc,
557 struct mmc_cmd *cmd, struct mmc_data *data);
Jaehoon Chung07b0b9c2016-12-30 15:30:16 +0900558 int (*set_ios)(struct mmc *mmc);
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200559 int (*init)(struct mmc *mmc);
560 int (*getcd)(struct mmc *mmc);
561 int (*getwp)(struct mmc *mmc);
Yann Gautier3602a562019-09-19 17:56:12 +0200562 int (*host_power_cycle)(struct mmc *mmc);
Marek Vasut145429a2020-04-04 12:45:05 +0200563 int (*get_b_max)(struct mmc *mmc, void *dst, lbaint_t blkcnt);
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200564};
Yangbo Lud271e102020-09-01 16:58:04 +0800565
566static inline int mmc_hs400_prepare_ddr(struct mmc *mmc)
567{
568 return 0;
569}
Simon Glass8ca51e52016-06-12 23:30:22 -0600570#endif
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200571
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200572struct mmc_config {
573 const char *name;
Simon Glasse7881d82017-07-29 11:35:31 -0600574#if !CONFIG_IS_ENABLED(DM_MMC)
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200575 const struct mmc_ops *ops;
Simon Glass8ca51e52016-06-12 23:30:22 -0600576#endif
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200577 uint host_caps;
Andy Fleming272cc702008-10-30 16:41:01 -0500578 uint voltages;
Andy Fleming272cc702008-10-30 16:41:01 -0500579 uint f_min;
580 uint f_max;
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200581 uint b_max;
582 unsigned char part_type;
Jaehoon Chungcaee38a2021-02-16 10:16:52 +0900583#ifdef CONFIG_MMC_PWRSEQ
584 struct udevice *pwr_dev;
585#endif
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200586};
587
Peng Fan3697e592016-09-01 11:13:38 +0800588struct sd_ssr {
589 unsigned int au; /* In sectors */
590 unsigned int erase_timeout; /* In milliseconds */
591 unsigned int erase_offset; /* In milliseconds */
592};
593
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200594enum bus_mode {
595 MMC_LEGACY,
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200596 MMC_HS,
597 SD_HS,
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100598 MMC_HS_52,
599 MMC_DDR_52,
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200600 UHS_SDR12,
601 UHS_SDR25,
602 UHS_SDR50,
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200603 UHS_DDR50,
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100604 UHS_SDR104,
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200605 MMC_HS_200,
Peng Fan3dd26262018-08-10 14:07:54 +0800606 MMC_HS_400,
Peng Fan44acd492019-07-10 14:43:07 +0800607 MMC_HS_400_ES,
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200608 MMC_MODES_END
609};
610
611const char *mmc_mode_name(enum bus_mode mode);
Jean-Jacques Hiblot4c9d2aa2017-09-21 16:29:54 +0200612void mmc_dump_capabilities(const char *text, uint caps);
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200613
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200614static inline bool mmc_is_mode_ddr(enum bus_mode mode)
615{
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100616 if (mode == MMC_DDR_52)
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200617 return true;
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100618#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
619 else if (mode == UHS_DDR50)
620 return true;
621#endif
Peng Fan3dd26262018-08-10 14:07:54 +0800622#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
623 else if (mode == MMC_HS_400)
624 return true;
625#endif
Peng Fan44acd492019-07-10 14:43:07 +0800626#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
627 else if (mode == MMC_HS_400_ES)
628 return true;
629#endif
Jean-Jacques Hiblot3862b852017-09-21 16:29:58 +0200630 else
631 return false;
632}
633
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200634#define UHS_CAPS (MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) | \
635 MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_SDR104) | \
636 MMC_CAP(UHS_DDR50))
637
638static inline bool supports_uhs(uint caps)
639{
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100640#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200641 return (caps & UHS_CAPS) ? true : false;
Jean-Jacques Hiblotf99c2ef2017-11-30 17:44:01 +0100642#else
643 return false;
644#endif
Jean-Jacques Hiblotc10b85d2017-09-21 16:30:07 +0200645}
646
Simon Glass8ca51e52016-06-12 23:30:22 -0600647/*
648 * With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device
649 * with mmc_get_mmc_dev().
650 *
651 * TODO struct mmc should be in mmc_private but it's hard to fix right now
652 */
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200653struct mmc {
Simon Glassc4d660d2017-07-04 13:31:19 -0600654#if !CONFIG_IS_ENABLED(BLK)
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200655 struct list_head link;
Simon Glass33fb2112016-05-01 13:52:41 -0600656#endif
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200657 const struct mmc_config *cfg; /* provided configuration */
658 uint version;
659 void *priv;
660 uint has_init;
Andy Fleming272cc702008-10-30 16:41:01 -0500661 int high_capacity;
Kishon Vijay Abraham I35f67822017-09-21 16:30:03 +0200662 bool clk_disable; /* true if the clock can be turned off */
Andy Fleming272cc702008-10-30 16:41:01 -0500663 uint bus_width;
664 uint clock;
Faiz Abbas0d3c8582020-02-26 13:44:29 +0530665 uint saved_clock;
Kishon Vijay Abraham Iaff5d3c2017-09-21 16:30:00 +0200666 enum mmc_voltage signal_voltage;
Andy Fleming272cc702008-10-30 16:41:01 -0500667 uint card_caps;
Jean-Jacques Hiblot04a2ea22017-09-21 16:30:08 +0200668 uint host_caps;
Andy Fleming272cc702008-10-30 16:41:01 -0500669 uint ocr;
Markus Niebelab711882013-12-16 13:40:46 +0100670 uint dsr;
671 uint dsr_imp;
Andy Fleming272cc702008-10-30 16:41:01 -0500672 uint scr[2];
673 uint csd[4];
Rabin Vincent0b453ff2009-04-05 13:30:55 +0530674 uint cid[4];
Andy Fleming272cc702008-10-30 16:41:01 -0500675 ushort rca;
Diego Santa Cruzc3dbb4f2014-12-23 10:50:17 +0100676 u8 part_support;
677 u8 part_attr;
Diego Santa Cruz9e41a002014-12-23 10:50:33 +0100678 u8 wr_rel_set;
Tom Rini7ca0d3d2017-05-10 15:20:16 -0400679 u8 part_config;
Sam Protsenko6cf8a902019-08-14 22:52:51 +0300680 u8 gen_cmd6_time; /* units: 10 ms */
681 u8 part_switch_time; /* units: 10 ms */
Andy Fleming272cc702008-10-30 16:41:01 -0500682 uint tran_speed;
Jean-Jacques Hiblot35f9e192017-09-21 16:29:53 +0200683 uint legacy_speed; /* speed for the legacy mode provided by the card */
Andy Fleming272cc702008-10-30 16:41:01 -0500684 uint read_bl_len;
Jean-Jacques Hiblote6fa5a52018-01-04 15:23:34 +0100685#if CONFIG_IS_ENABLED(MMC_WRITE)
Andy Fleming272cc702008-10-30 16:41:01 -0500686 uint write_bl_len;
Diego Santa Cruza4ff9f82014-12-23 10:50:24 +0100687 uint erase_grp_size; /* in 512-byte sectors */
Jean-Jacques Hiblote6fa5a52018-01-04 15:23:34 +0100688#endif
Jean-Jacques Hiblotb7a6e2c2018-01-04 15:23:36 +0100689#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
Diego Santa Cruz037dc0a2014-12-23 10:50:25 +0100690 uint hc_wp_grp_size; /* in 512-byte sectors */
Jean-Jacques Hiblotb7a6e2c2018-01-04 15:23:36 +0100691#endif
Jean-Jacques Hiblot5b2e72f2018-01-04 15:23:33 +0100692#if CONFIG_IS_ENABLED(MMC_WRITE)
Peng Fan3697e592016-09-01 11:13:38 +0800693 struct sd_ssr ssr; /* SD status register */
Jean-Jacques Hiblot5b2e72f2018-01-04 15:23:33 +0100694#endif
Andy Fleming272cc702008-10-30 16:41:01 -0500695 u64 capacity;
Stephen Warrenf866a462013-06-11 15:14:01 -0600696 u64 capacity_user;
697 u64 capacity_boot;
698 u64 capacity_rpmb;
699 u64 capacity_gp[4];
Jean-Jacques Hiblot173c06d2018-01-04 15:23:35 +0100700#ifndef CONFIG_SPL_BUILD
Diego Santa Cruza7f852b2014-12-23 10:50:22 +0100701 u64 enh_user_start;
702 u64 enh_user_size;
Jean-Jacques Hiblot173c06d2018-01-04 15:23:35 +0100703#endif
Simon Glassc4d660d2017-07-04 13:31:19 -0600704#if !CONFIG_IS_ENABLED(BLK)
Simon Glass4101f682016-02-29 15:25:34 -0700705 struct blk_desc block_dev;
Simon Glass33fb2112016-05-01 13:52:41 -0600706#endif
Che-Liang Chioue9550442012-11-28 15:21:13 +0000707 char op_cond_pending; /* 1 if we are waiting on an op_cond command */
708 char init_in_progress; /* 1 if we have done mmc_start_init() */
709 char preinit; /* start init as early as possible */
Andrew Gabbasov786e8f82014-12-01 06:59:09 -0600710 int ddr_mode;
Simon Glassc4d660d2017-07-04 13:31:19 -0600711#if CONFIG_IS_ENABLED(DM_MMC)
Simon Glasscffe5d82016-05-01 13:52:34 -0600712 struct udevice *dev; /* Device for this MMC controller */
Jean-Jacques Hiblot06ec0452017-09-21 16:29:48 +0200713#if CONFIG_IS_ENABLED(DM_REGULATOR)
714 struct udevice *vmmc_supply; /* Main voltage regulator (Vcc)*/
715 struct udevice *vqmmc_supply; /* IO voltage regulator (Vccq)*/
716#endif
Simon Glasscffe5d82016-05-01 13:52:34 -0600717#endif
Jean-Jacques Hiblotdfda9d82017-09-21 16:29:51 +0200718 u8 *ext_csd;
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +0200719 u32 cardtype; /* cardtype read from the MMC */
720 enum mmc_voltage current_voltage;
Jean-Jacques Hiblot01298da2017-09-21 16:30:09 +0200721 enum bus_mode selected_mode; /* mode currently used */
722 enum bus_mode best_mode; /* best mode is the supported mode with the
723 * highest bandwidth. It may not always be the
724 * operating mode due to limitations when
725 * accessing the boot partitions
726 */
Kishon Vijay Abraham I83dc4222017-09-21 16:30:10 +0200727 u32 quirks;
Yangbo Lu8c968802020-09-01 16:58:03 +0800728 u8 hs400_tuning;
Aswath Govindraju19f7a342021-08-13 23:04:41 +0530729
730 enum bus_mode user_speed_mode; /* input speed mode from user */
Andy Fleming272cc702008-10-30 16:41:01 -0500731};
732
Nicolas Saenz Juliennec89c96d2021-01-12 13:55:29 +0100733#if CONFIG_IS_ENABLED(DM_MMC)
734#define mmc_to_dev(_mmc) _mmc->dev
735#else
736#define mmc_to_dev(_mmc) NULL
737#endif
738
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +0100739struct mmc_hwpart_conf {
740 struct {
741 uint enh_start; /* in 512-byte sectors */
742 uint enh_size; /* in 512-byte sectors, if 0 no enh area */
Diego Santa Cruz8dda5b0e2014-12-23 10:50:31 +0100743 unsigned wr_rel_change : 1;
744 unsigned wr_rel_set : 1;
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +0100745 } user;
746 struct {
747 uint size; /* in 512-byte sectors */
Diego Santa Cruz8dda5b0e2014-12-23 10:50:31 +0100748 unsigned enhanced : 1;
749 unsigned wr_rel_change : 1;
750 unsigned wr_rel_set : 1;
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +0100751 } gp_part[4];
752};
753
754enum mmc_hwpart_conf_mode {
755 MMC_HWPART_CONF_CHECK,
756 MMC_HWPART_CONF_SET,
757 MMC_HWPART_CONF_COMPLETE,
758};
759
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200760struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
Simon Glassad27dd52016-05-01 13:52:40 -0600761
762/**
763 * mmc_bind() - Set up a new MMC device ready for probing
764 *
765 * A child block device is bound with the IF_TYPE_MMC interface type. This
766 * allows the device to be used with CONFIG_BLK
767 *
768 * @dev: MMC device to set up
769 * @mmc: MMC struct
770 * @cfg: MMC configuration
771 * @return 0 if OK, -ve on error
772 */
773int mmc_bind(struct udevice *dev, struct mmc *mmc,
774 const struct mmc_config *cfg);
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200775void mmc_destroy(struct mmc *mmc);
Simon Glassad27dd52016-05-01 13:52:40 -0600776
777/**
778 * mmc_unbind() - Unbind a MMC device's child block device
779 *
780 * @dev: MMC device
781 * @return 0 if OK, -ve on error
782 */
783int mmc_unbind(struct udevice *dev);
Masahiro Yamadabd602c52020-02-25 02:25:30 +0900784int mmc_initialize(struct bd_info *bis);
Lokesh Vutla80f02012019-09-09 14:40:36 +0530785int mmc_init_device(int num);
Andy Fleming272cc702008-10-30 16:41:01 -0500786int mmc_init(struct mmc *mmc);
Jean-Jacques Hiblot9815e3b2017-09-21 16:30:12 +0200787int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error);
Jaehoon Chung2da23352021-05-31 08:31:49 +0900788int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data);
Jean-Jacques Hiblot7abff2c2017-11-30 17:43:55 +0100789
Marek Vasutfceea992019-01-29 04:45:51 +0100790#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
791 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
792 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
793int mmc_deinit(struct mmc *mmc);
794#endif
795
Jean-Jacques Hiblot7abff2c2017-11-30 17:43:55 +0100796/**
797 * mmc_of_parse() - Parse the device tree to get the capabilities of the host
798 *
799 * @dev: MMC device
800 * @cfg: MMC configuration
801 * @return 0 if OK, -ve on error
802 */
803int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg);
804
Jaehoon Chungcaee38a2021-02-16 10:16:52 +0900805#ifdef CONFIG_MMC_PWRSEQ
806/**
807 * mmc_pwrseq_get_power() - get a power device from device tree
808 *
809 * @dev: MMC device
810 * @cfg: MMC configuration
811 * @return 0 if OK, -ve on error
812 */
813int mmc_pwrseq_get_power(struct udevice *dev, struct mmc_config *cfg);
814#endif
815
Andy Fleming272cc702008-10-30 16:41:01 -0500816int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
Kishon Vijay Abraham I35f67822017-09-21 16:30:03 +0200817
818/**
Jean-Jacques Hiblotbc1e3272017-09-21 16:30:11 +0200819 * mmc_voltage_to_mv() - Convert a mmc_voltage in mV
820 *
821 * @voltage: The mmc_voltage to convert
822 * @return the value in mV if OK, -EINVAL on error (invalid mmc_voltage value)
823 */
824int mmc_voltage_to_mv(enum mmc_voltage voltage);
825
826/**
Kishon Vijay Abraham I35f67822017-09-21 16:30:03 +0200827 * mmc_set_clock() - change the bus clock
828 * @mmc: MMC struct
829 * @clock: bus frequency in Hz
830 * @disable: flag indicating if the clock must on or off
831 * @return 0 if OK, -ve on error
832 */
833int mmc_set_clock(struct mmc *mmc, uint clock, bool disable);
834
Jaehoon Chung65117182018-01-26 19:25:29 +0900835#define MMC_CLK_ENABLE false
836#define MMC_CLK_DISABLE true
837
Andy Fleming272cc702008-10-30 16:41:01 -0500838struct mmc *find_mmc_device(int dev_num);
Steve Sakoman89716962010-07-01 12:12:42 -0700839int mmc_set_dev(int dev_num);
Andy Fleming272cc702008-10-30 16:41:01 -0500840void print_mmc_devices(char separator);
Kever Yang46683f32016-07-22 17:22:50 +0800841
842/**
843 * get_mmc_num() - get the total MMC device number
844 *
845 * @return 0 if there is no MMC device, else the number of devices
846 */
Lei Wenea6ebe22011-05-02 16:26:25 +0000847int get_mmc_num(void);
Marek Vasutb5b838f2016-12-01 02:06:33 +0100848int mmc_switch_part(struct mmc *mmc, unsigned int part_num);
Diego Santa Cruzac9da0e2014-12-23 10:50:29 +0100849int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
850 enum mmc_hwpart_conf_mode mode);
Simon Glass8ca51e52016-06-12 23:30:22 -0600851
Simon Glasse7881d82017-07-29 11:35:31 -0600852#if !CONFIG_IS_ENABLED(DM_MMC)
Thierry Reding48972d92012-01-02 01:15:37 +0000853int mmc_getcd(struct mmc *mmc);
Jeroen Hofstee750121c2014-07-12 21:24:08 +0200854int board_mmc_getcd(struct mmc *mmc);
Nikita Kiryanovd23d8d72012-12-03 02:19:46 +0000855int mmc_getwp(struct mmc *mmc);
Jeroen Hofstee750121c2014-07-12 21:24:08 +0200856int board_mmc_getwp(struct mmc *mmc);
Simon Glass8ca51e52016-06-12 23:30:22 -0600857#endif
858
Markus Niebelab711882013-12-16 13:40:46 +0100859int mmc_set_dsr(struct mmc *mmc, u16 val);
Amar3690d6d2013-04-27 11:42:58 +0530860/* Function to change the size of boot partition and rpmb partitions */
861int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
862 unsigned long rpmbsize);
Tom Rini792970b2014-02-05 10:24:21 -0500863/* Function to modify the PARTITION_CONFIG field of EXT_CSD */
864int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
Tom Rini5a99b9d2014-02-05 10:24:22 -0500865/* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
866int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
Tom Rini33ace362014-02-07 14:15:20 -0500867/* Function to modify the RST_n_FUNCTION field of EXT_CSD */
868int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
Pierre Aubert91fdabc2014-04-24 10:30:06 +0200869/* Functions to read / write the RPMB partition */
870int mmc_rpmb_set_key(struct mmc *mmc, void *key);
871int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter);
872int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
873 unsigned short cnt, unsigned char *key);
874int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
875 unsigned short cnt, unsigned char *key);
Jens Wiklander4853ad32018-09-25 16:40:08 +0200876
877/**
878 * mmc_rpmb_route_frames() - route RPMB data frames
879 * @mmc Pointer to a MMC device struct
880 * @req Request data frames
881 * @reqlen Length of data frames in bytes
882 * @rsp Supplied buffer for response data frames
883 * @rsplen Length of supplied buffer for response data frames
884 *
885 * The RPMB data frames are routed to/from some external entity, for
886 * example a Trusted Exectuion Environment in an arm TrustZone protected
887 * secure world. It's expected that it's the external entity who is in
888 * control of the RPMB key.
889 *
890 * Returns 0 on success, < 0 on error.
891 */
892int mmc_rpmb_route_frames(struct mmc *mmc, void *req, unsigned long reqlen,
893 void *rsp, unsigned long rsplen);
894
Tomas Melincd3d4882016-11-25 11:01:03 +0200895#ifdef CONFIG_CMD_BKOPS_ENABLE
896int mmc_set_bkops_enable(struct mmc *mmc);
897#endif
898
Che-Liang Chioue9550442012-11-28 15:21:13 +0000899/**
900 * Start device initialization and return immediately; it does not block on
Jon Nettleton6c09eba2018-06-11 15:26:19 +0300901 * polling OCR (operation condition register) status. Useful for checking
902 * the presence of SD/eMMC when no card detect logic is available.
903 *
904 * @param mmc Pointer to a MMC device struct
Pali Rohára4c577f2021-07-14 16:37:29 +0200905 * @param quiet Be quiet, do not print error messages when card is not detected.
Jon Nettleton6c09eba2018-06-11 15:26:19 +0300906 * @return 0 on success, <0 on error.
907 */
Pali Rohára4c577f2021-07-14 16:37:29 +0200908int mmc_get_op_cond(struct mmc *mmc, bool quiet);
Jon Nettleton6c09eba2018-06-11 15:26:19 +0300909
910/**
911 * Start device initialization and return immediately; it does not block on
Che-Liang Chioue9550442012-11-28 15:21:13 +0000912 * polling OCR (operation condition register) status. Then you should call
913 * mmc_init, which would block on polling OCR status and complete the device
914 * initializatin.
915 *
916 * @param mmc Pointer to a MMC device struct
Baruch Siach31d95002018-06-11 15:26:18 +0300917 * @return 0 on success, <0 on error.
Che-Liang Chioue9550442012-11-28 15:21:13 +0000918 */
919int mmc_start_init(struct mmc *mmc);
920
921/**
922 * Set preinit flag of mmc device.
923 *
924 * This will cause the device to be pre-inited during mmc_initialize(),
925 * which may save boot time if the device is not accessed until later.
926 * Some eMMC devices take 200-300ms to init, but unfortunately they
927 * must be sent a series of commands to even get them to start preparing
928 * for operation.
929 *
930 * @param mmc Pointer to a MMC device struct
931 * @param preinit preinit flag value
932 */
933void mmc_set_preinit(struct mmc *mmc, int preinit);
934
Paul Burton8687d5c2013-09-04 16:12:26 +0100935#ifdef CONFIG_MMC_SPI
Tom Rini0b2da7e2014-03-28 16:55:29 -0400936#define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI)
Paul Burton8687d5c2013-09-04 16:12:26 +0100937#else
938#define mmc_host_is_spi(mmc) 0
939#endif
Reinhard Meyer1592ef82010-08-13 10:31:06 +0200940
Sean Anderson68fd6022020-09-15 10:44:45 -0400941#define mmc_dev(x) ((x)->dev)
942
Paul Kocialkowski95de9ab2014-11-08 20:55:45 +0100943void board_mmc_power_init(void);
Masahiro Yamadabd602c52020-02-25 02:25:30 +0900944int board_mmc_init(struct bd_info *bis);
945int cpu_mmc_init(struct bd_info *bis);
Jeroen Hofsteeaeb80552014-10-08 22:58:05 +0200946int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
Rajesh Bhagat43d17c42019-01-12 07:30:51 +0000947# ifdef CONFIG_SYS_MMC_ENV_PART
948extern uint mmc_get_env_part(struct mmc *mmc);
949# endif
Clemens Gruberaa844fe2016-01-26 16:20:38 +0100950int mmc_get_env_dev(void);
Fabio Estevam3c7ca962014-02-15 14:51:59 -0200951
Jean-Jacques Hiblot513e00b2019-07-02 10:53:55 +0200952/* Minimum partition switch timeout in units of 10-milliseconds */
953#define MMC_MIN_PART_SWITCH_TIME 30 /* 300 ms */
954
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200955/* Set block count limit because of 16 bit register limit on some hardware*/
956#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
957#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
958#endif
959
Simon Glasscb5ec332016-05-01 13:52:27 -0600960/**
961 * mmc_get_blk_desc() - Get the block descriptor for an MMC device
962 *
963 * @mmc: MMC device
964 * @return block device if found, else NULL
965 */
966struct blk_desc *mmc_get_blk_desc(struct mmc *mmc);
967
Heinrich Schuchardt1601ea22020-03-30 07:24:17 +0200968/**
969 * mmc_send_ext_csd() - read the extended CSD register
970 *
971 * @mmc: MMC device
972 * @ext_csd a cache aligned buffer of length MMC_MAX_BLOCK_LEN allocated by
973 * the caller, e.g. using
974 * ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN)
975 * Return: 0 for success
976 */
977int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd);
978
Heinrich Schuchardt0469d842020-03-30 07:24:19 +0200979/**
980 * mmc_boot_wp() - power on write protect boot partitions
981 *
982 * The boot partitions are write protected until the next power cycle.
983 *
984 * Return: 0 for success
985 */
986int mmc_boot_wp(struct mmc *mmc);
987
Masahiro Yamadaa7b2b6c2020-02-14 16:40:25 +0900988static inline enum dma_data_direction mmc_get_dma_dir(struct mmc_data *data)
989{
990 return data->flags & MMC_DATA_WRITE ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
991}
992
wdenk71f95112003-06-15 22:40:42 +0000993#endif /* _MMC_H_ */