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Wolfgang Denk6ccec442006-10-24 14:42:37 +02001/*
2 * Copyright (C) 2005-2006 Atmel Corporation
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Wolfgang Denk6ccec442006-10-24 14:42:37 +02005 */
6#include <common.h>
7
8#include <asm/io.h>
9#include <asm/sdram.h>
Haavard Skinnemoend38da532008-01-23 17:20:14 +010010#include <asm/arch/clk.h>
Haavard Skinnemoen44453b22008-04-30 14:19:28 +020011#include <asm/arch/hmatrix.h>
Haavard Skinnemoen1f36f732010-08-12 13:52:54 +070012#include <asm/arch/mmu.h>
Haavard Skinnemoenab0df362008-08-29 21:09:49 +020013#include <asm/arch/portmux.h>
Ben Warren89973f82008-08-31 22:22:04 -070014#include <netdev.h>
Wolfgang Denk6ccec442006-10-24 14:42:37 +020015
16DECLARE_GLOBAL_DATA_PTR;
17
Haavard Skinnemoen1f36f732010-08-12 13:52:54 +070018struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
19 {
20 .virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
21 .nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
22 .phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
23 | MMU_VMR_CACHE_NONE,
24 }, {
25 .virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
26 .nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT,
27 .phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
28 | MMU_VMR_CACHE_WRBACK,
29 },
30};
31
Haavard Skinnemoena23e2772008-05-19 11:36:28 +020032static const struct sdram_config sdram_config = {
33#if defined(CONFIG_ATSTK1006)
34 /* Dual MT48LC16M16A2-7E (64 MB) on daughterboard */
35 .data_bits = SDRAM_DATA_32BIT,
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010036 .row_bits = 13,
37 .col_bits = 9,
38 .bank_bits = 2,
39 .cas = 2,
40 .twr = 2,
41 .trc = 7,
42 .trp = 2,
43 .trcd = 2,
44 .tras = 4,
45 .txsr = 7,
46 /* 7.81 us */
47 .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010048#else
Haavard Skinnemoena23e2772008-05-19 11:36:28 +020049 /* MT48LC2M32B2P-5 (8 MB) on motherboard */
50#ifdef CONFIG_ATSTK1004
51 .data_bits = SDRAM_DATA_16BIT,
52#else
53 .data_bits = SDRAM_DATA_32BIT,
54#endif
55#ifdef CONFIG_ATSTK1000_16MB_SDRAM
56 /* MT48LC4M32B2P-6 (16 MB) on mod'ed motherboard */
57 .row_bits = 12,
58#else
Wolfgang Denk6ccec442006-10-24 14:42:37 +020059 .row_bits = 11,
Haavard Skinnemoena23e2772008-05-19 11:36:28 +020060#endif
Wolfgang Denk6ccec442006-10-24 14:42:37 +020061 .col_bits = 8,
62 .bank_bits = 2,
63 .cas = 3,
64 .twr = 2,
65 .trc = 7,
66 .trp = 2,
67 .trcd = 2,
68 .tras = 5,
69 .txsr = 5,
Haavard Skinnemoend38da532008-01-23 17:20:14 +010070 /* 15.6 us */
71 .refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010072#endif
Haavard Skinnemoena23e2772008-05-19 11:36:28 +020073};
Wolfgang Denk6ccec442006-10-24 14:42:37 +020074
Haavard Skinnemoendf548d32006-11-19 18:06:53 +010075int board_early_init_f(void)
76{
Haavard Skinnemoen44453b22008-04-30 14:19:28 +020077 /* Enable SDRAM in the EBI mux */
78 hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
Haavard Skinnemoendf548d32006-11-19 18:06:53 +010079
Haavard Skinnemoenab0df362008-08-29 21:09:49 +020080 portmux_enable_ebi(sdram_config.data_bits, 23, 0, PORTMUX_DRIVE_HIGH);
81 portmux_enable_usart1(PORTMUX_DRIVE_MIN);
Haavard Skinnemoen9a24f472006-12-17 17:14:30 +010082#if defined(CONFIG_MACB)
Haavard Skinnemoenab0df362008-08-29 21:09:49 +020083 portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_LOW);
84 portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_LOW);
Haavard Skinnemoen9a24f472006-12-17 17:14:30 +010085#endif
Haavard Skinnemoen8e687512006-12-17 18:56:46 +010086#if defined(CONFIG_MMC)
Haavard Skinnemoenab0df362008-08-29 21:09:49 +020087 portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
Haavard Skinnemoen8e687512006-12-17 18:56:46 +010088#endif
Haavard Skinnemoendf548d32006-11-19 18:06:53 +010089
90 return 0;
91}
92
Becky Bruce9973e3c2008-06-09 16:03:40 -050093phys_size_t initdram(int board_type)
Wolfgang Denk6ccec442006-10-24 14:42:37 +020094{
Haavard Skinnemoena23e2772008-05-19 11:36:28 +020095 unsigned long expected_size;
96 unsigned long actual_size;
97 void *sdram_base;
98
Haavard Skinnemoen9cec2fc2010-08-12 13:52:53 +070099 sdram_base = uncached(EBI_SDRAM_BASE);
Haavard Skinnemoena23e2772008-05-19 11:36:28 +0200100
101 expected_size = sdram_init(sdram_base, &sdram_config);
102 actual_size = get_ram_size(sdram_base, expected_size);
103
Haavard Skinnemoena23e2772008-05-19 11:36:28 +0200104 if (expected_size != actual_size)
Haavard Skinnemoen7f4b0092008-07-23 10:55:15 +0200105 printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
Haavard Skinnemoena23e2772008-05-19 11:36:28 +0200106 actual_size >> 20, expected_size >> 20);
107
108 return actual_size;
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200109}
110
Haavard Skinnemoen25e68542008-08-31 18:46:35 +0200111int board_early_init_r(void)
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200112{
113 gd->bd->bi_phy_id[0] = 0x10;
114 gd->bd->bi_phy_id[1] = 0x11;
Haavard Skinnemoen25e68542008-08-31 18:46:35 +0200115 return 0;
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200116}
Ben Warrenc8c845c2008-07-05 00:08:48 -0700117
Ben Warrenc8c845c2008-07-05 00:08:48 -0700118#ifdef CONFIG_CMD_NET
119int board_eth_init(bd_t *bi)
120{
Andreas Bießmannf4278b72010-11-04 23:15:31 +0000121 macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
122 macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);
Ben Warrenc8c845c2008-07-05 00:08:48 -0700123 return 0;
124}
125#endif