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Nikita Kiryanovbaaa7dd2015-02-03 13:32:20 +02001/*
2 * atmel_lcd.h - Atmel LCD Controller structures
3 *
4 * (C) Copyright 2001
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#ifndef _ATMEL_LCD_H_
11#define _ATMEL_LCD_H_
12
13typedef struct vidinfo {
14 ushort vl_col; /* Number of columns (i.e. 640) */
15 ushort vl_row; /* Number of rows (i.e. 480) */
Hannes Petermaier604c7d42015-03-27 08:01:38 +010016 ushort vl_rot; /* Rotation of Display (0, 1, 2, 3) */
17 u_long vl_clk; /* pixel clock in ps */
Nikita Kiryanovbaaa7dd2015-02-03 13:32:20 +020018
19 /* LCD configuration register */
20 u_long vl_sync; /* Horizontal / vertical sync */
21 u_long vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
22 u_long vl_tft; /* 0 = passive, 1 = TFT */
23 u_long vl_cont_pol_low; /* contrast polarity is low */
24 u_long vl_clk_pol; /* clock polarity */
25
26 /* Horizontal control register. */
27 u_long vl_hsync_len; /* Length of horizontal sync */
28 u_long vl_left_margin; /* Time from sync to picture */
29 u_long vl_right_margin; /* Time from picture to sync */
30
31 /* Vertical control register. */
32 u_long vl_vsync_len; /* Length of vertical sync */
33 u_long vl_upper_margin; /* Time from sync to picture */
34 u_long vl_lower_margin; /* Time from picture to sync */
35
36 u_long mmio; /* Memory mapped registers */
37} vidinfo_t;
38
39#endif