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wdenk62219a22002-10-02 20:40:41 +00001/*
2 * (C) Copyright 2000
3 * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
4 *
5 * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
6 * Marius Groeger <mgroeger@sysgo.de>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 *
26 * Back ported to the 8xx platform (from the 8260 platform) by
27 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
28 */
29
30#include <common.h>
31
32#ifdef CONFIG_HARD_I2C
33
34#include <commproc.h>
35#include <i2c.h>
36#ifdef CONFIG_LWMON
37#include <watchdog.h>
38#endif
39
40/* define to enable debug messages */
41#undef DEBUG_I2C
42
43/*-----------------------------------------------------------------------
44 * Set default values
45 */
46#ifndef CFG_I2C_SPEED
47#define CFG_I2C_SPEED 50000
48#endif
49
50#ifndef CFG_I2C_SLAVE
51#define CFG_I2C_SLAVE 0xFE
52#endif
53/*-----------------------------------------------------------------------
54 */
55
56/* tx/rx timeout (we need the i2c early, so we don't use get_timer()) */
57#define TOUT_LOOP 1000000
58
59#define NUM_RX_BDS 4
60#define NUM_TX_BDS 4
61#define MAX_TX_SPACE 256
62#define I2C_RXTX_LEN 128 /* maximum tx/rx buffer length */
63
64typedef struct I2C_BD
65{
66 unsigned short status;
67 unsigned short length;
68 unsigned char *addr;
69} I2C_BD;
70#define BD_I2C_TX_START 0x0400 /* special status for i2c: Start condition */
71
72#define BD_I2C_TX_CL 0x0001 /* collision error */
73#define BD_I2C_TX_UN 0x0002 /* underflow error */
74#define BD_I2C_TX_NAK 0x0004 /* no acknowledge error */
75#define BD_I2C_TX_ERR (BD_I2C_TX_NAK|BD_I2C_TX_UN|BD_I2C_TX_CL)
76
77#define BD_I2C_RX_ERR BD_SC_OV
78
79typedef void (*i2c_ecb_t)(int, int); /* error callback function */
80
81/* This structure keeps track of the bd and buffer space usage. */
82typedef struct i2c_state {
83 int rx_idx; /* index to next free Rx BD */
84 int tx_idx; /* index to next free Tx BD */
85 void *rxbd; /* pointer to next free Rx BD */
86 void *txbd; /* pointer to next free Tx BD */
87 int tx_space; /* number of Tx bytes left */
88 unsigned char *tx_buf; /* pointer to free Tx area */
89 i2c_ecb_t err_cb; /* error callback function */
90} i2c_state_t;
91
92
93/* flags for i2c_send() and i2c_receive() */
94#define I2CF_ENABLE_SECONDARY 0x01 /* secondary_address is valid */
95#define I2CF_START_COND 0x02 /* tx: generate start condition */
96#define I2CF_STOP_COND 0x04 /* tx: generate stop condition */
97
98/* return codes */
99#define I2CERR_NO_BUFFERS 0x01 /* no more BDs or buffer space */
100#define I2CERR_MSG_TOO_LONG 0x02 /* tried to send/receive to much data */
101#define I2CERR_TIMEOUT 0x03 /* timeout in i2c_doio() */
102#define I2CERR_QUEUE_EMPTY 0x04 /* i2c_doio called without send/receive */
103
104/* error callback flags */
105#define I2CECB_RX_ERR 0x10 /* this is a receive error */
106#define I2CECB_RX_ERR_OV 0x02 /* receive overrun error */
107#define I2CECB_RX_MASK 0x0f /* mask for error bits */
108#define I2CECB_TX_ERR 0x20 /* this is a transmit error */
109#define I2CECB_TX_CL 0x01 /* transmit collision error */
110#define I2CECB_TX_UN 0x02 /* transmit underflow error */
111#define I2CECB_TX_NAK 0x04 /* transmit no ack error */
112#define I2CECB_TX_MASK 0x0f /* mask for error bits */
113#define I2CECB_TIMEOUT 0x40 /* this is a timeout error */
114
115#ifdef DEBUG_I2C
116#define PRINTD(x) printf x
117#else
118#define PRINTD(x)
119#endif
120
121/*
122 * Returns the best value of I2BRG to meet desired clock speed of I2C with
123 * input parameters (clock speed, filter, and predivider value).
124 * It returns computer speed value and the difference between it and desired
125 * speed.
126 */
127static inline int
128i2c_roundrate(int hz, int speed, int filter, int modval,
129 int *brgval, int *totspeed)
130{
131 int moddiv = 1 << (5-(modval & 3)), brgdiv, div;
132
133 PRINTD(("\t[I2C] trying hz=%d, speed=%d, filter=%d, modval=%d\n",
134 hz, speed, filter, modval));
135
136 div = moddiv * speed;
137 brgdiv = (hz + div - 1) / div;
138
139 PRINTD(("\t\tmoddiv=%d, brgdiv=%d\n", moddiv, brgdiv));
140
141 *brgval = ((brgdiv + 1) / 2) - 3 - (2*filter);
142
143 if ((*brgval < 0) || (*brgval > 255)) {
144 PRINTD(("\t\trejected brgval=%d\n", *brgval));
145 return -1;
146 }
147
148 brgdiv = 2 * (*brgval + 3 + (2 * filter));
149 div = moddiv * brgdiv ;
150 *totspeed = hz / div;
151
152 PRINTD(("\t\taccepted brgval=%d, totspeed=%d\n", *brgval, *totspeed));
153
154 return 0;
155}
156
157/*
158 * Sets the I2C clock predivider and divider to meet required clock speed.
159 */
160static int
161i2c_setrate (int hz, int speed)
162{
163 immap_t *immap = (immap_t *) CFG_IMMR;
164 volatile i2c8xx_t *i2c = (i2c8xx_t *) & immap->im_i2c;
165 int brgval,
166 modval, /* 0-3 */
167 bestspeed_diff = speed,
168 bestspeed_brgval = 0,
169 bestspeed_modval = 0,
170 bestspeed_filter = 0,
171 totspeed,
172 filter = 0; /* Use this fixed value */
173
174 for (modval = 0; modval < 4; modval++) {
175 if (i2c_roundrate(hz,speed,filter,modval,&brgval,&totspeed) == 0) {
176 int diff = speed - totspeed;
177
178 if ((diff >= 0) && (diff < bestspeed_diff)) {
179 bestspeed_diff = diff;
180 bestspeed_modval = modval;
181 bestspeed_brgval = brgval;
182 bestspeed_filter = filter;
183 }
184 }
185 }
186
187 PRINTD (("[I2C] Best is:\n"));
188 PRINTD (("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n",
189 hz,
190 speed,
191 bestspeed_filter,
192 bestspeed_modval,
193 bestspeed_brgval,
194 bestspeed_diff));
195
196 i2c->i2c_i2mod |= ((bestspeed_modval & 3) << 1) | (bestspeed_filter << 3);
197 i2c->i2c_i2brg = bestspeed_brgval & 0xff;
198
199 PRINTD (("[I2C] i2mod=%08x i2brg=%08x\n", i2c->i2c_i2mod,
200 i2c->i2c_i2brg));
201
202 return 1;
203}
204
205void
206i2c_init(int speed, int slaveaddr)
207{
208 DECLARE_GLOBAL_DATA_PTR;
209
210 volatile immap_t *immap = (immap_t *)CFG_IMMR ;
211 volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
212 volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c;
213 volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
214 ulong rbase, tbase;
215 volatile I2C_BD *rxbd, *txbd;
216 uint dpaddr;
217
wdenk47cd00f2003-03-06 13:39:27 +0000218#ifdef CFG_I2C_INIT_BOARD
219 /* call board specific i2c bus reset routine before accessing the */
220 /* environment, which might be in a chip on that bus. For details */
221 /* about this problem see doc/I2C_Edge_Conditions. */
222 i2c_init_board();
223#endif
224
wdenk62219a22002-10-02 20:40:41 +0000225#ifdef CFG_I2C_UCODE_PATCH
226 iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
227#else
228 /* Disable relocation */
229 iip->iic_rpbase = 0;
230#endif
231
232#ifdef CFG_ALLOC_DPRAM
233 dpaddr = iip->iic_rbase;
234 if (dpaddr == 0) {
235 /* need to allocate dual port ram */
236 dpaddr = dpram_alloc_align(
237 (NUM_RX_BDS * sizeof(I2C_BD)) + (NUM_TX_BDS * sizeof(I2C_BD)) +
238 MAX_TX_SPACE, 8);
239 }
240#else
241 dpaddr = CPM_I2C_BASE;
242#endif
243
244 /*
245 * initialise data in dual port ram:
246 *
247 * dpaddr->rbase -> rx BD (NUM_RX_BDS * sizeof(I2C_BD) bytes)
248 * tbase -> tx BD (NUM_TX_BDS * sizeof(I2C_BD) bytes)
249 * tx buffer (MAX_TX_SPACE bytes)
250 */
251
252 rbase = dpaddr;
253 tbase = rbase + NUM_RX_BDS * sizeof(I2C_BD);
254
255 /* Initialize Port B I2C pins. */
256 cp->cp_pbpar |= 0x00000030;
257 cp->cp_pbdir |= 0x00000030;
258 cp->cp_pbodr |= 0x00000030;
259
260 /* Disable interrupts */
261 i2c->i2c_i2mod = 0x00;
262 i2c->i2c_i2cmr = 0x00;
263 i2c->i2c_i2cer = 0xff;
264 i2c->i2c_i2add = slaveaddr;
265
266 /*
267 * Set the I2C BRG Clock division factor from desired i2c rate
268 * and current CPU rate (we assume sccr dfbgr field is 0;
269 * divide BRGCLK by 1)
270 */
271 PRINTD(("[I2C] Setting rate...\n"));
272 i2c_setrate (gd->cpu_clk, CFG_I2C_SPEED) ;
273
274 /* Set I2C controller in master mode */
275 i2c->i2c_i2com = 0x01;
276
277 /* Set SDMA bus arbitration level to 5 (SDCR) */
278 immap->im_siu_conf.sc_sdcr = 0x0001 ;
279
280 /* Initialize Tx/Rx parameters */
281 iip->iic_rbase = rbase;
282 iip->iic_tbase = tbase;
283 rxbd = (I2C_BD *)((unsigned char *)&cp->cp_dpmem[iip->iic_rbase]);
284 txbd = (I2C_BD *)((unsigned char *)&cp->cp_dpmem[iip->iic_tbase]);
285
286 PRINTD(("[I2C] rbase = %04x\n", iip->iic_rbase));
287 PRINTD(("[I2C] tbase = %04x\n", iip->iic_tbase));
288 PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd));
289 PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
290
291 /* Set big endian byte order */
292 iip->iic_tfcr = 0x10;
293 iip->iic_rfcr = 0x10;
294
295 /* Set maximum receive size. */
296 iip->iic_mrblr = I2C_RXTX_LEN;
297
298#ifdef CFG_I2C_UCODE_PATCH
299 /*
300 * Initialize required parameters if using microcode patch.
301 */
302 iip->iic_rbptr = iip->iic_rbase;
303 iip->iic_tbptr = iip->iic_tbase;
304 iip->iic_rstate = 0;
305 iip->iic_tstate = 0;
306#else
307 cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_I2C, CPM_CR_INIT_TRX) | CPM_CR_FLG;
308 do {
309 __asm__ __volatile__ ("eieio");
310 } while (cp->cp_cpcr & CPM_CR_FLG);
311#endif
312
313 /* Clear events and interrupts */
314 i2c->i2c_i2cer = 0xff;
315 i2c->i2c_i2cmr = 0x00;
316}
317
318static void
319i2c_newio(i2c_state_t *state)
320{
321 volatile immap_t *immap = (immap_t *)CFG_IMMR ;
322 volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
323 volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
324
325 PRINTD(("[I2C] i2c_newio\n"));
326
327#ifdef CFG_I2C_UCODE_PATCH
328 iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
329#endif
330 state->rx_idx = 0;
331 state->tx_idx = 0;
332 state->rxbd = (void*)&cp->cp_dpmem[iip->iic_rbase];
333 state->txbd = (void*)&cp->cp_dpmem[iip->iic_tbase];
334 state->tx_space = MAX_TX_SPACE;
335 state->tx_buf = (uchar*)state->txbd + NUM_TX_BDS * sizeof(I2C_BD);
336 state->err_cb = NULL;
337
338 PRINTD(("[I2C] rxbd = %08x\n", (int)state->rxbd));
339 PRINTD(("[I2C] txbd = %08x\n", (int)state->txbd));
340 PRINTD(("[I2C] tx_buf = %08x\n", (int)state->tx_buf));
341
342 /* clear the buffer memory */
343 memset((char *)state->tx_buf, 0, MAX_TX_SPACE);
344}
345
346static int
347i2c_send(i2c_state_t *state,
348 unsigned char address,
349 unsigned char secondary_address,
350 unsigned int flags,
351 unsigned short size,
352 unsigned char *dataout)
353{
354 volatile I2C_BD *txbd;
355 int i,j;
356
357 PRINTD(("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n",
358 address, secondary_address, flags, size));
359
360 /* trying to send message larger than BD */
361 if (size > I2C_RXTX_LEN)
362 return I2CERR_MSG_TOO_LONG;
363
364 /* no more free bds */
365 if (state->tx_idx >= NUM_TX_BDS || state->tx_space < (2 + size))
366 return I2CERR_NO_BUFFERS;
367
368 txbd = (I2C_BD *)state->txbd;
369 txbd->addr = state->tx_buf;
370
371 PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
372
373 if (flags & I2CF_START_COND) {
374 PRINTD(("[I2C] Formatting addresses...\n"));
375 if (flags & I2CF_ENABLE_SECONDARY) {
376 txbd->length = size + 2; /* Length of msg + dest addr */
377 txbd->addr[0] = address << 1;
378 txbd->addr[1] = secondary_address;
379 i = 2;
380 } else {
381 txbd->length = size + 1; /* Length of msg + dest addr */
382 txbd->addr[0] = address << 1; /* Write dest addr to BD */
383 i = 1;
384 }
385 } else {
386 txbd->length = size; /* Length of message */
387 i = 0;
388 }
389
390 /* set up txbd */
391 txbd->status = BD_SC_READY;
392 if (flags & I2CF_START_COND)
393 txbd->status |= BD_I2C_TX_START;
394 if (flags & I2CF_STOP_COND)
395 txbd->status |= BD_SC_LAST | BD_SC_WRAP;
396
397 /* Copy data to send into buffer */
398 PRINTD(("[I2C] copy data...\n"));
399 for(j = 0; j < size; i++, j++)
400 txbd->addr[i] = dataout[j];
401
402 PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
403 txbd->length,
404 txbd->status,
405 txbd->addr[0],
406 txbd->addr[1]));
407
408 /* advance state */
409 state->tx_buf += txbd->length;
410 state->tx_space -= txbd->length;
411 state->tx_idx++;
412 state->txbd = (void*)(txbd + 1);
413
414 return 0;
415}
416
417static int
418i2c_receive(i2c_state_t *state,
419 unsigned char address,
420 unsigned char secondary_address,
421 unsigned int flags,
422 unsigned short size_to_expect,
423 unsigned char *datain)
424{
425 volatile I2C_BD *rxbd, *txbd;
426
427 PRINTD(("[I2C] i2c_receive %02d %02d %02d\n", address, secondary_address, flags));
428
429 /* Expected to receive too much */
430 if (size_to_expect > I2C_RXTX_LEN)
431 return I2CERR_MSG_TOO_LONG;
432
433 /* no more free bds */
434 if (state->tx_idx >= NUM_TX_BDS || state->rx_idx >= NUM_RX_BDS
435 || state->tx_space < 2)
436 return I2CERR_NO_BUFFERS;
437
438 rxbd = (I2C_BD *)state->rxbd;
439 txbd = (I2C_BD *)state->txbd;
440
441 PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd));
442 PRINTD(("[I2C] txbd = %08x\n", (int)txbd));
443
444 txbd->addr = state->tx_buf;
445
446 /* set up TXBD for destination address */
447 if (flags & I2CF_ENABLE_SECONDARY) {
448 txbd->length = 2;
449 txbd->addr[0] = address << 1; /* Write data */
450 txbd->addr[1] = secondary_address; /* Internal address */
451 txbd->status = BD_SC_READY;
452 } else {
453 txbd->length = 1 + size_to_expect;
454 txbd->addr[0] = (address << 1) | 0x01;
455 txbd->status = BD_SC_READY;
456 memset(&txbd->addr[1], 0, txbd->length);
457 }
458
459 /* set up rxbd for reception */
460 rxbd->status = BD_SC_EMPTY;
461 rxbd->length = size_to_expect;
462 rxbd->addr = datain;
463
464 txbd->status |= BD_I2C_TX_START;
465 if (flags & I2CF_STOP_COND) {
466 txbd->status |= BD_SC_LAST | BD_SC_WRAP;
467 rxbd->status |= BD_SC_WRAP;
468 }
469
470 PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
471 txbd->length,
472 txbd->status,
473 txbd->addr[0],
474 txbd->addr[1]));
475 PRINTD(("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
476 rxbd->length,
477 rxbd->status,
478 rxbd->addr[0],
479 rxbd->addr[1]));
480
481 /* advance state */
482 state->tx_buf += txbd->length;
483 state->tx_space -= txbd->length;
484 state->tx_idx++;
485 state->txbd = (void*)(txbd + 1);
486 state->rx_idx++;
487 state->rxbd = (void*)(rxbd + 1);
488
489 return 0;
490}
491
492
493static int i2c_doio(i2c_state_t *state)
494{
495 volatile immap_t *immap = (immap_t *)CFG_IMMR ;
496 volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
497 volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c;
498 volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
499 volatile I2C_BD *txbd, *rxbd;
500 volatile int j = 0;
501
502 PRINTD(("[I2C] i2c_doio\n"));
503
504#ifdef CFG_I2C_UCODE_PATCH
505 iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
506#endif
507
508 if (state->tx_idx <= 0 && state->rx_idx <= 0) {
509 PRINTD(("[I2C] No I/O is queued\n"));
510 return I2CERR_QUEUE_EMPTY;
511 }
512
513 iip->iic_rbptr = iip->iic_rbase;
514 iip->iic_tbptr = iip->iic_tbase;
515
516 /* Enable I2C */
517 PRINTD(("[I2C] Enabling I2C...\n"));
518 i2c->i2c_i2mod |= 0x01;
519
520 /* Begin transmission */
521 i2c->i2c_i2com |= 0x80;
522
523 /* Loop until transmit & receive completed */
524
525 if (state->tx_idx > 0) {
526 txbd = ((I2C_BD*)state->txbd) - 1;
527 PRINTD(("[I2C] Transmitting...(txbd=0x%08lx)\n", (ulong)txbd));
528 while((txbd->status & BD_SC_READY) && (j++ < TOUT_LOOP)) {
529 if (ctrlc()) {
530 return (-1);
531 }
532 __asm__ __volatile__ ("eieio");
533 }
534 }
535
536 if ((state->rx_idx > 0) && (j < TOUT_LOOP)) {
537 rxbd = ((I2C_BD*)state->rxbd) - 1;
538 PRINTD(("[I2C] Receiving...(rxbd=0x%08lx)\n", (ulong)rxbd));
539 while((rxbd->status & BD_SC_EMPTY) && (j++ < TOUT_LOOP)) {
540 if (ctrlc()) {
541 return (-1);
542 }
543 __asm__ __volatile__ ("eieio");
544 }
545 }
546
547 /* Turn off I2C */
548 i2c->i2c_i2mod &= ~0x01;
549
550 if (state->err_cb != NULL) {
551 int n, i, b;
552
553 /*
554 * if we have an error callback function, look at the
555 * error bits in the bd status and pass them back
556 */
557
558 if ((n = state->tx_idx) > 0) {
559 for (i = 0; i < n; i++) {
560 txbd = ((I2C_BD*)state->txbd) - (n - i);
561 if ((b = txbd->status & BD_I2C_TX_ERR) != 0)
562 (*state->err_cb)(I2CECB_TX_ERR|b, i);
563 }
564 }
565
566 if ((n = state->rx_idx) > 0) {
567 for (i = 0; i < n; i++) {
568 rxbd = ((I2C_BD*)state->rxbd) - (n - i);
569 if ((b = rxbd->status & BD_I2C_RX_ERR) != 0)
570 (*state->err_cb)(I2CECB_RX_ERR|b, i);
571 }
572 }
573
574 if (j >= TOUT_LOOP)
575 (*state->err_cb)(I2CECB_TIMEOUT, 0);
576 }
577
578 return (j >= TOUT_LOOP) ? I2CERR_TIMEOUT : 0;
579}
580
581static int had_tx_nak;
582
583static void
584i2c_test_callback(int flags, int xnum)
585{
586 if ((flags & I2CECB_TX_ERR) && (flags & I2CECB_TX_NAK))
587 had_tx_nak = 1;
588}
589
590int i2c_probe(uchar chip)
591{
592 i2c_state_t state;
593 int rc;
594 uchar buf[1];
595
596 i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
597
598 i2c_newio(&state);
599
600 state.err_cb = i2c_test_callback;
601 had_tx_nak = 0;
602
603 rc = i2c_receive(&state, chip, 0, I2CF_START_COND|I2CF_STOP_COND, 1, buf);
604
605 if (rc != 0)
606 return (rc);
607
608 rc = i2c_doio(&state);
609
610 if ((rc != 0) && (rc != I2CERR_TIMEOUT))
611 return (rc);
612
613 return (had_tx_nak);
614}
615
616int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
617{
618 DECLARE_GLOBAL_DATA_PTR;
619
620 i2c_state_t state;
621 uchar xaddr[4];
622 int rc;
623
624#ifdef CONFIG_LWMON
625 WATCHDOG_RESET();
626#endif
627
628 xaddr[0] = (addr >> 24) & 0xFF;
629 xaddr[1] = (addr >> 16) & 0xFF;
630 xaddr[2] = (addr >> 8) & 0xFF;
631 xaddr[3] = addr & 0xFF;
632
633#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
634 /*
635 * EEPROM chips that implement "address overflow" are ones like
636 * Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the
637 * extra bits end up in the "chip address" bit slots. This makes
638 * a 24WC08 (1Kbyte) chip look like four 256 byte chips.
639 *
640 * Note that we consider the length of the address field to still
641 * be one byte because the extra address bits are hidden in the
642 * chip address.
643 */
644 chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
645#endif
646
647 i2c_newio(&state);
648
649 rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, &xaddr[4-alen]);
650 if (rc != 0) {
651 if (gd->have_console)
652 printf("i2c_read: i2c_send failed (%d)\n", rc);
653 return 1;
654 }
655
656 rc = i2c_receive(&state, chip, 0, I2CF_STOP_COND, len, buffer);
657 if (rc != 0) {
658 if (gd->have_console)
659 printf("i2c_read: i2c_receive failed (%d)\n", rc);
660 return 1;
661 }
662
663 rc = i2c_doio(&state);
664 if (rc != 0) {
665 if (gd->have_console)
666 printf("i2c_read: i2c_doio failed (%d)\n", rc);
667 return 1;
668 }
669 return 0;
670}
671
672int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
673{
674 DECLARE_GLOBAL_DATA_PTR;
675
676 i2c_state_t state;
677 uchar xaddr[4];
678 int rc;
679
680 xaddr[0] = (addr >> 24) & 0xFF;
681 xaddr[1] = (addr >> 16) & 0xFF;
682 xaddr[2] = (addr >> 8) & 0xFF;
683 xaddr[3] = addr & 0xFF;
684
685#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
686 /*
687 * EEPROM chips that implement "address overflow" are ones like
688 * Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the
689 * extra bits end up in the "chip address" bit slots. This makes
690 * a 24WC08 (1Kbyte) chip look like four 256 byte chips.
691 *
692 * Note that we consider the length of the address field to still
693 * be one byte because the extra address bits are hidden in the
694 * chip address.
695 */
696 chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
697#endif
698
699 i2c_newio(&state);
700
701 rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, &xaddr[4-alen]);
702 if (rc != 0) {
703 if (gd->have_console)
704 printf("i2c_write: first i2c_send failed (%d)\n", rc);
705 return 1;
706 }
707
708 rc = i2c_send(&state, 0, 0, I2CF_STOP_COND, len, buffer);
709 if (rc != 0) {
710 if (gd->have_console)
711 printf("i2c_write: second i2c_send failed (%d)\n", rc);
712 return 1;
713 }
714
715 rc = i2c_doio(&state);
716 if (rc != 0) {
717 if (gd->have_console)
718 printf("i2c_write: i2c_doio failed (%d)\n", rc);
719 return 1;
720 }
721 return 0;
722}
723
724uchar
725i2c_reg_read(uchar i2c_addr, uchar reg)
726{
727 char buf;
728
729 i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
730
731 i2c_read(i2c_addr, reg, 1, &buf, 1);
732
733 return (buf);
734}
735
736void
737i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
738{
739 i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
740
741 i2c_write(i2c_addr, reg, 1, &val, 1);
742}
743
744#endif /* CONFIG_HARD_I2C */