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Priyanka Jain58c3e622018-11-28 13:04:27 +00001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
Meenakshi Aggarwal69b38942020-01-10 20:13:19 +05303 * Copyright 2018-2020 NXP
Priyanka Jain58c3e622018-11-28 13:04:27 +00004 */
5
6#ifndef __LX2_COMMON_H
7#define __LX2_COMMON_H
8
9#include <asm/arch/stream_id_lsch3.h>
10#include <asm/arch/config.h>
11#include <asm/arch/soc.h>
12
13#define CONFIG_REMAKE_ELF
14#define CONFIG_FSL_LAYERSCAPE
15#define CONFIG_GICV3
16#define CONFIG_FSL_TZPC_BP147
17#define CONFIG_FSL_MEMAC
18
19#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
20#define CONFIG_SYS_FLASH_BASE 0x20000000
21
22#define CONFIG_SKIP_LOWLEVEL_INIT
23#define CONFIG_BOARD_EARLY_INIT_F 1
24
25/* DDR */
26#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
27#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */
28#define CONFIG_VERY_BIG_RAM
29#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
30#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
31#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
32#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2
33#define CONFIG_SYS_SDRAM_SIZE 0x200000000UL
34#define CONFIG_DDR_SPD
35#define CONFIG_DDR_ECC
36#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
37#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
38#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
39#define SPD_EEPROM_ADDRESS1 0x51
40#define SPD_EEPROM_ADDRESS2 0x52
41#define SPD_EEPROM_ADDRESS3 0x53
42#define SPD_EEPROM_ADDRESS4 0x54
43#define SPD_EEPROM_ADDRESS5 0x55
44#define SPD_EEPROM_ADDRESS6 0x56
45#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
46#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
47#define CONFIG_DIMM_SLOTS_PER_CTLR 2
48#define CONFIG_CHIP_SELECTS_PER_CTRL 4
49#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
50#define CONFIG_SYS_MONITOR_LEN (936 * 1024)
51
52/* Miscellaneous configurable options */
53#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
54
55/* SMP Definitinos */
56#define CPU_RELEASE_ADDR secondary_boot_func
57
58/* Generic Timer Definitions */
59/*
60 * This is not an accurate number. It is used in start.S. The frequency
61 * will be udpated later when get_bus_freq(0) is available.
62 */
63
64#define COUNTER_FREQUENCY 25000000 /* 25MHz */
65
66/* Size of malloc() pool */
67#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
68
69/* Serial Port */
70#define CONFIG_PL01X_SERIAL
71#define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4)
72#define CONFIG_SYS_SERIAL0 0x21c0000
73#define CONFIG_SYS_SERIAL1 0x21d0000
74#define CONFIG_SYS_SERIAL2 0x21e0000
75#define CONFIG_SYS_SERIAL3 0x21f0000
76/*below might needs to be removed*/
77#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
78 (void *)CONFIG_SYS_SERIAL1, \
79 (void *)CONFIG_SYS_SERIAL2, \
80 (void *)CONFIG_SYS_SERIAL3 }
81#define CONFIG_BAUDRATE 115200
82#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
83
84/* MC firmware */
85#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
86#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
87#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
88#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
89#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
90
91/* Define phy_reset function to boot the MC based on mcinitcmd.
92 * This happens late enough to properly fixup u-boot env MAC addresses.
93 */
94#define CONFIG_RESET_PHY_R
95
96/*
97 * Carve out a DDR region which will not be used by u-boot/Linux
98 *
99 * It will be used by MC and Debug Server. The MC region must be
100 * 512MB aligned, so the min size to hide is 512MB.
101 */
102#ifdef CONFIG_FSL_MC_ENET
Meenakshi Aggarwal43ad41e2019-02-27 14:41:02 +0530103#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024)
Priyanka Jain58c3e622018-11-28 13:04:27 +0000104#endif
105
106/* I2C bus multiplexer */
107#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
108#define I2C_MUX_CH_DEFAULT 0x8
109
110/* RTC */
111#define RTC
112#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
113
114/* EEPROM */
115#define CONFIG_ID_EEPROM
116#define CONFIG_SYS_I2C_EEPROM_NXID
117#define CONFIG_SYS_EEPROM_BUS_NUM 0
118#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
119#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
120#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
121#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
122
123/* Qixis */
124#define CONFIG_FSL_QIXIS
125#define CONFIG_QIXIS_I2C_ACCESS
126#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
127
128/* PCI */
129#ifdef CONFIG_PCI
130#define CONFIG_SYS_PCI_64BIT
131#define CONFIG_PCI_SCAN_SHOW
132#endif
133
134/* MMC */
135#ifdef CONFIG_MMC
136#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
137#endif
138
139/* SATA */
140
141#ifdef CONFIG_SCSI
142#define CONFIG_SCSI_AHCI_PLAT
143#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
144#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2
145#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
146#define CONFIG_SYS_SCSI_MAX_LUN 1
147#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
148 CONFIG_SYS_SCSI_MAX_LUN)
149#endif
150
151/* USB */
152#ifdef CONFIG_USB
153#define CONFIG_HAS_FSL_XHCI_USB
154#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
155#endif
156
157/* FlexSPI */
158#ifdef CONFIG_NXP_FSPI
159#define NXP_FSPI_FLASH_SIZE SZ_64M
160#define NXP_FSPI_FLASH_NUM 1
161#endif
162
163#ifndef __ASSEMBLY__
164unsigned long get_board_sys_clk(void);
165unsigned long get_board_ddr_clk(void);
166#endif
167
168#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
169#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
170#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
171
172#define CONFIG_HWCONFIG
173#define HWCONFIG_BUFFER_SIZE 128
174
175#define CONFIG_SYS_MMC_ENV_DEV 0
Priyanka Jain58c3e622018-11-28 13:04:27 +0000176
177/* Allow to overwrite serial and ethaddr */
178#define CONFIG_ENV_OVERWRITE
179
180/* Monitor Command Prompt */
181#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
182#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
183 sizeof(CONFIG_SYS_PROMPT) + 16)
184#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
Priyanka Jain58c3e622018-11-28 13:04:27 +0000185#define CONFIG_SYS_MAXARGS 64 /* max command args */
186
187#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
188
189/* Initial environment variables */
Kuldeep Singhb9804c32020-03-12 15:13:00 +0530190#define XSPI_MC_INIT_CMD \
191 "sf probe 0:0 && " \
192 "sf read 0x80640000 0x640000 0x80000 && " \
193 "env exists secureboot && " \
194 "esbc_validate 0x80640000 && " \
195 "esbc_validate 0x80680000; " \
196 "sf read 0x80a00000 0xa00000 0x300000 && " \
197 "sf read 0x80e00000 0xe00000 0x100000; " \
198 "fsl_mc start mc 0x80a00000 0x80e00000\0"
Priyanka Jain58c3e622018-11-28 13:04:27 +0000199
200#define SD_MC_INIT_CMD \
Pankaj Bansalf002b3f2019-07-17 10:33:54 +0000201 "mmc read 0x80a00000 0x5000 0x1200;" \
202 "mmc read 0x80e00000 0x7000 0x800;" \
Udit Agarwal19e97e42018-12-14 04:43:32 +0000203 "env exists secureboot && " \
Priyanka Singh20858a22020-01-22 10:31:22 +0000204 "mmc read 0x80640000 0x3200 0x20 && " \
205 "mmc read 0x80680000 0x3400 0x20 && " \
206 "esbc_validate 0x80640000 && " \
207 "esbc_validate 0x80680000 ;" \
Pankaj Bansalf002b3f2019-07-17 10:33:54 +0000208 "fsl_mc start mc 0x80a00000 0x80e00000\0"
Priyanka Jain58c3e622018-11-28 13:04:27 +0000209
Meenakshi Aggarwal3a67cbf2020-04-27 19:56:40 +0530210#define SD2_MC_INIT_CMD \
211 "mmc dev 1; mmc read 0x80a00000 0x5000 0x1200;" \
212 "mmc read 0x80e00000 0x7000 0x800;" \
213 "env exists secureboot && " \
214 "mmc read 0x80640000 0x3200 0x20 && " \
215 "mmc read 0x80680000 0x3400 0x20 && " \
216 "esbc_validate 0x80640000 && " \
217 "esbc_validate 0x80680000 ;" \
218 "fsl_mc start mc 0x80a00000 0x80e00000\0"
219
Priyanka Jain3e1a9b52019-01-24 05:22:18 +0000220#define EXTRA_ENV_SETTINGS \
221 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
222 "ramdisk_addr=0x800000\0" \
223 "ramdisk_size=0x2000000\0" \
224 "fdt_high=0xa0000000\0" \
225 "initrd_high=0xffffffffffffffff\0" \
226 "fdt_addr=0x64f00000\0" \
227 "kernel_start=0x1000000\0" \
Priyanka Singh20858a22020-01-22 10:31:22 +0000228 "kernelheader_start=0x600000\0" \
Priyanka Jain3e1a9b52019-01-24 05:22:18 +0000229 "scriptaddr=0x80000000\0" \
230 "scripthdraddr=0x80080000\0" \
231 "fdtheader_addr_r=0x80100000\0" \
232 "kernelheader_addr_r=0x80200000\0" \
233 "kernel_addr_r=0x81000000\0" \
234 "kernelheader_size=0x40000\0" \
235 "fdt_addr_r=0x90000000\0" \
236 "load_addr=0xa0000000\0" \
237 "kernel_size=0x2800000\0" \
238 "kernel_addr_sd=0x8000\0" \
Priyanka Singh20858a22020-01-22 10:31:22 +0000239 "kernelhdr_addr_sd=0x3000\0" \
Priyanka Jain3e1a9b52019-01-24 05:22:18 +0000240 "kernel_size_sd=0x1d000\0" \
Udit Agarwald749bf92019-11-20 08:49:06 +0000241 "kernelhdr_size_sd=0x20\0" \
Priyanka Jain3e1a9b52019-01-24 05:22:18 +0000242 "console=ttyAMA0,38400n8\0" \
243 BOOTENV \
244 "mcmemsize=0x70000000\0" \
245 XSPI_MC_INIT_CMD \
Priyanka Jain3e1a9b52019-01-24 05:22:18 +0000246 "scan_dev_for_boot_part=" \
247 "part list ${devtype} ${devnum} devplist; " \
248 "env exists devplist || setenv devplist 1; " \
249 "for distro_bootpart in ${devplist}; do " \
250 "if fstype ${devtype} " \
251 "${devnum}:${distro_bootpart} " \
252 "bootfstype; then " \
253 "run scan_dev_for_boot; " \
254 "fi; " \
255 "done\0" \
Priyanka Jain3e1a9b52019-01-24 05:22:18 +0000256 "boot_a_script=" \
257 "load ${devtype} ${devnum}:${distro_bootpart} " \
258 "${scriptaddr} ${prefix}${script}; " \
259 "env exists secureboot && load ${devtype} " \
260 "${devnum}:${distro_bootpart} " \
261 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
262 "&& esbc_validate ${scripthdraddr};" \
263 "source ${scriptaddr}\0"
264
265#define XSPI_NOR_BOOTCOMMAND \
Kuldeep Singhb9804c32020-03-12 15:13:00 +0530266 "sf probe 0:0; " \
267 "sf read 0x806c0000 0x6c0000 0x40000; " \
268 "env exists mcinitcmd && env exists secureboot" \
269 " && esbc_validate 0x806c0000; " \
270 "sf read 0x80d00000 0xd00000 0x100000; " \
Priyanka Jain3e1a9b52019-01-24 05:22:18 +0000271 "env exists mcinitcmd && " \
Kuldeep Singhb9804c32020-03-12 15:13:00 +0530272 "fsl_mc lazyapply dpl 0x80d00000; " \
Priyanka Jain3e1a9b52019-01-24 05:22:18 +0000273 "run distro_bootcmd;run xspi_bootcmd; " \
274 "env exists secureboot && esbc_halt;"
275
276#define SD_BOOTCOMMAND \
277 "env exists mcinitcmd && mmcinfo; " \
Pankaj Bansalf002b3f2019-07-17 10:33:54 +0000278 "mmc read 0x80d00000 0x6800 0x800; " \
Priyanka Jain3e1a9b52019-01-24 05:22:18 +0000279 "env exists mcinitcmd && env exists secureboot " \
Priyanka Singh20858a22020-01-22 10:31:22 +0000280 " && mmc read 0x806C0000 0x3600 0x20 " \
281 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
Pankaj Bansalf002b3f2019-07-17 10:33:54 +0000282 "&& fsl_mc lazyapply dpl 0x80d00000;" \
Priyanka Jain3e1a9b52019-01-24 05:22:18 +0000283 "run distro_bootcmd;run sd_bootcmd;" \
284 "env exists secureboot && esbc_halt;"
285
Meenakshi Aggarwalb7e7a462020-02-19 23:30:45 +0530286#define SD2_BOOTCOMMAND \
Meenakshi Aggarwal3a67cbf2020-04-27 19:56:40 +0530287 "mmc dev 1; env exists mcinitcmd && mmcinfo; " \
Meenakshi Aggarwalb7e7a462020-02-19 23:30:45 +0530288 "mmc read 0x80d00000 0x6800 0x800; " \
289 "env exists mcinitcmd && env exists secureboot " \
Meenakshi Aggarwal3a67cbf2020-04-27 19:56:40 +0530290 " && mmc read 0x806C0000 0x3600 0x20 " \
291 "&& esbc_validate 0x806C0000;env exists mcinitcmd " \
Meenakshi Aggarwalb7e7a462020-02-19 23:30:45 +0530292 "&& fsl_mc lazyapply dpl 0x80d00000;" \
293 "run distro_bootcmd;run sd2_bootcmd;" \
294 "env exists secureboot && esbc_halt;"
295
Priyanka Jain3e1a9b52019-01-24 05:22:18 +0000296#define BOOT_TARGET_DEVICES(func) \
297 func(USB, usb, 0) \
298 func(MMC, mmc, 0) \
Meenakshi Aggarwalb7e7a462020-02-19 23:30:45 +0530299 func(MMC, mmc, 1) \
Meenakshi Aggarwalc5076a02020-03-11 20:51:47 +0530300 func(SCSI, scsi, 0) \
301 func(DHCP, dhcp, na)
Priyanka Jain3e1a9b52019-01-24 05:22:18 +0000302#include <config_distro_bootcmd.h>
303
Priyanka Jain58c3e622018-11-28 13:04:27 +0000304#endif /* __LX2_COMMON_H */