blob: ee873b09141c1f02fc75c5131af18be927b61cbb [file] [log] [blame]
Ying Zhangc9e1f582014-01-24 15:50:09 +08001/* Copyright 2013 Freescale Semiconductor, Inc.
2 *
3 * SPDX-License-Identifier: GPL-2.0+
4 */
5
6#include <common.h>
7#include <ns16550.h>
8#include <malloc.h>
9#include <mmc.h>
10#include <nand.h>
11#include <i2c.h>
12#include <fsl_esdhc.h>
13#include <spi_flash.h>
14
15DECLARE_GLOBAL_DATA_PTR;
16
Tom Rinia7e8c152014-02-25 12:44:13 -050017phys_size_t get_effective_memsize(void)
Ying Zhangc9e1f582014-01-24 15:50:09 +080018{
19 return CONFIG_SYS_L2_SIZE;
20}
21
22void board_init_f(ulong bootflag)
23{
24 u32 plat_ratio;
25 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
Jaiprakash Singh39b0bbb2015-03-20 19:28:27 -070026 struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
Ying Zhangc9e1f582014-01-24 15:50:09 +080027
28 console_init_f();
29
30 /* Clock configuration to access CPLD using IFC(GPCM) */
Jaiprakash Singh39b0bbb2015-03-20 19:28:27 -070031 setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
Ying Zhangc9e1f582014-01-24 15:50:09 +080032
33#ifdef CONFIG_P1010RDB_PB
34 setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
35#endif
36
37 /* initialize selected port with appropriate baud rate */
38 plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
39 plat_ratio >>= 1;
40 gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
41
42 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
43 gd->bus_clk / 16 / CONFIG_BAUDRATE);
44
45#ifdef CONFIG_SPL_MMC_BOOT
46 puts("\nSD boot...\n");
47#elif defined(CONFIG_SPL_SPI_BOOT)
48 puts("\nSPI Flash boot...\n");
49#endif
50 /* copy code to RAM and jump to it - this should not return */
51 /* NOTE - code has to be copied out of NAND buffer before
52 * other blocks can be read.
53 */
54 relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
55}
56
57void board_init_r(gd_t *gd, ulong dest_addr)
58{
59 /* Pointer is writable since we allocated a register for it */
60 gd = (gd_t *)CONFIG_SPL_GD_ADDR;
61 bd_t *bd;
62
63 memset(gd, 0, sizeof(gd_t));
64 bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
65 memset(bd, 0, sizeof(bd_t));
66 gd->bd = bd;
67 bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
68 bd->bi_memsize = CONFIG_SYS_L2_SIZE;
69
70 probecpu();
71 get_clocks();
72 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
73 CONFIG_SPL_RELOC_MALLOC_SIZE);
74
75#ifndef CONFIG_SPL_NAND_BOOT
76 env_init();
77#endif
78#ifdef CONFIG_SPL_MMC_BOOT
79 mmc_initialize(bd);
80#endif
81
82 /* relocate environment function pointers etc. */
83#ifdef CONFIG_SPL_NAND_BOOT
84 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
85 (uchar *)CONFIG_ENV_ADDR);
86 gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
87 gd->env_valid = 1;
88#else
89 env_relocate();
90#endif
91
92 i2c_init_all();
93
94 gd->ram_size = initdram(0);
95#ifdef CONFIG_SPL_NAND_BOOT
96 puts("\nTertiary program loader running in sram...");
97#else
98 puts("\nSecond program loader running in sram...");
99#endif
100
101#ifdef CONFIG_SPL_MMC_BOOT
102 mmc_boot();
103#elif defined(CONFIG_SPL_SPI_BOOT)
104 spi_boot();
105#elif defined(CONFIG_SPL_NAND_BOOT)
106 nand_boot();
107#endif
108}