blob: 20dfb9e0e250ab843f18f8f38ee1a1ac0f580047 [file] [log] [blame]
Jon Loeligerdebb7352006-04-26 17:58:56 -05001/*
Becky Bruce1605cc92011-10-03 19:10:51 -05002 * Copyright 2004, 2007, 2011 Freescale Semiconductor.
Jon Loeligerdebb7352006-04-26 17:58:56 -05003 * Srikanth Srinivasan <srikanth.srinivaan@freescale.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/* U-Boot - Startup Code for 86xx PowerPC based Embedded Boards
25 *
26 *
27 * The processor starts at 0xfff00100 and the code is executed
28 * from flash. The code is organized to be at an other address
29 * in memory, but as long we don't jump around before relocating.
30 * board_init lies at a quite high address and when the cpu has
31 * jumped there, everything is ok.
32 */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020033#include <asm-offsets.h>
Jon Loeligerdebb7352006-04-26 17:58:56 -050034#include <config.h>
35#include <mpc86xx.h>
36#include <version.h>
37
38#include <ppc_asm.tmpl>
39#include <ppc_defs.h>
40
41#include <asm/cache.h>
42#include <asm/mmu.h>
Peter Tyserd98b0522010-10-14 23:33:24 -050043#include <asm/u-boot.h>
Jon Loeligerdebb7352006-04-26 17:58:56 -050044
Jon Loeligercfc7a7f2007-08-02 14:42:20 -050045/*
46 * Need MSR_DR | MSR_IR enabled to access I/O (printf) in exceptions
47 */
Jon Loeligerdebb7352006-04-26 17:58:56 -050048
49/*
50 * Set up GOT: Global Offset Table
51 *
Joakim Tjernlund0f8aa152010-01-19 14:41:56 +010052 * Use r12 to access the GOT
Jon Loeligerdebb7352006-04-26 17:58:56 -050053 */
54 START_GOT
55 GOT_ENTRY(_GOT2_TABLE_)
56 GOT_ENTRY(_FIXUP_TABLE_)
57
58 GOT_ENTRY(_start)
59 GOT_ENTRY(_start_of_vectors)
60 GOT_ENTRY(_end_of_vectors)
61 GOT_ENTRY(transfer_to_handler)
62
63 GOT_ENTRY(__init_end)
Simon Glass3929fb02013-03-14 06:54:53 +000064 GOT_ENTRY(__bss_end)
Jon Loeligerdebb7352006-04-26 17:58:56 -050065 GOT_ENTRY(__bss_start)
66 END_GOT
67
68/*
69 * r3 - 1st arg to board_init(): IMMP pointer
70 * r4 - 2nd arg to board_init(): boot flag
71 */
72 .text
Jon Loeligerffff3ae2006-08-22 12:06:18 -050073 .long 0x27051956 /* U-Boot Magic Number */
Jon Loeligerdebb7352006-04-26 17:58:56 -050074 .globl version_string
75version_string:
Andreas Bießmann09c2e902011-07-18 20:24:04 +020076 .ascii U_BOOT_VERSION_STRING, "\0"
Jon Loeligerdebb7352006-04-26 17:58:56 -050077
78 . = EXC_OFF_SYS_RESET
79 .globl _start
80_start:
Jon Loeligerdebb7352006-04-26 17:58:56 -050081 b boot_cold
Jon Loeligerdebb7352006-04-26 17:58:56 -050082
83 /* the boot code is located below the exception table */
84
85 .globl _start_of_vectors
86_start_of_vectors:
87
88/* Machine check */
89 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
90
91/* Data Storage exception. */
92 STD_EXCEPTION(0x300, DataStorage, UnknownException)
93
94/* Instruction Storage exception. */
95 STD_EXCEPTION(0x400, InstStorage, UnknownException)
96
97/* External Interrupt exception. */
98 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
99
100/* Alignment exception. */
101 . = 0x600
102Alignment:
Rafal Jaworowski02032e82007-06-22 14:58:04 +0200103 EXCEPTION_PROLOG(SRR0, SRR1)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500104 mfspr r4,DAR
105 stw r4,_DAR(r21)
106 mfspr r5,DSISR
107 stw r5,_DSISR(r21)
108 addi r3,r1,STACK_FRAME_OVERHEAD
Joakim Tjernlundfc4e1882010-01-19 14:41:55 +0100109 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500110
111/* Program check exception */
112 . = 0x700
113ProgramCheck:
Rafal Jaworowski02032e82007-06-22 14:58:04 +0200114 EXCEPTION_PROLOG(SRR0, SRR1)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500115 addi r3,r1,STACK_FRAME_OVERHEAD
Joakim Tjernlundfc4e1882010-01-19 14:41:55 +0100116 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
117 MSR_KERNEL, COPY_EE)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500118
119 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
120
121 /* I guess we could implement decrementer, and may have
122 * to someday for timekeeping.
123 */
124 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
125 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
126 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
127 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
128 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
129 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
130 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
131 STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
132 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
133 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
134 STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
135 STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
136 STD_EXCEPTION(0x1500, Reserved5, UnknownException)
137 STD_EXCEPTION(0x1600, Reserved6, UnknownException)
138 STD_EXCEPTION(0x1700, Reserved7, UnknownException)
139 STD_EXCEPTION(0x1800, Reserved8, UnknownException)
140 STD_EXCEPTION(0x1900, Reserved9, UnknownException)
141 STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
142 STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
143 STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
144 STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
145 STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
146 STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
147
148 .globl _end_of_vectors
149_end_of_vectors:
150
151 . = 0x2000
152
153boot_cold:
Becky Bruce1266df82008-11-03 15:44:01 -0600154 /*
155 * NOTE: Only Cpu 0 will ever come here. Other cores go to an
156 * address specified by the BPTR
157 */
Jon Loeligercfc7a7f2007-08-02 14:42:20 -05001581:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#ifdef CONFIG_SYS_RAMBOOT
Jon Loeligerdebb7352006-04-26 17:58:56 -0500160 /* disable everything */
Jon Loeligercfc7a7f2007-08-02 14:42:20 -0500161 li r0, 0
Jon Loeligerdebb7352006-04-26 17:58:56 -0500162 mtspr HID0, r0
163 sync
164 mtmsr 0
Jon Loeligercfc7a7f2007-08-02 14:42:20 -0500165#endif
166
Dave Liudc2adad2008-10-28 17:46:12 +0800167 /* Invalidate BATs */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500168 bl invalidate_bats
169 sync
Dave Liudc2adad2008-10-28 17:46:12 +0800170 /* Invalidate all of TLB before MMU turn on */
171 bl clear_tlbs
172 sync
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500173
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#ifdef CONFIG_SYS_L2
Jon Loeligerdebb7352006-04-26 17:58:56 -0500175 /* init the L2 cache */
Jon Loeligercfc7a7f2007-08-02 14:42:20 -0500176 lis r3, L2_INIT@h
Jon Loeligerdebb7352006-04-26 17:58:56 -0500177 ori r3, r3, L2_INIT@l
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500178 mtspr l2cr, r3
Jon Loeligerdebb7352006-04-26 17:58:56 -0500179 /* invalidate the L2 cache */
180 bl l2cache_invalidate
181 sync
182#endif
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500183
Jon Loeligerdebb7352006-04-26 17:58:56 -0500184 /*
185 * Calculate absolute address in FLASH and jump there
186 *------------------------------------------------------*/
Becky Brucebf9a8c32008-11-05 14:55:35 -0600187 lis r3, CONFIG_SYS_MONITOR_BASE_EARLY@h
188 ori r3, r3, CONFIG_SYS_MONITOR_BASE_EARLY@l
Jon Loeligerdebb7352006-04-26 17:58:56 -0500189 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
190 mtlr r3
191 blr
192
193in_flash:
194 /* let the C-code set up the rest */
195 /* */
196 /* Be careful to keep code relocatable ! */
197 /*------------------------------------------------------*/
198 /* perform low-level init */
199
200 /* enable extended addressing */
201 bl enable_ext_addr
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500202
Jon Loeligerdebb7352006-04-26 17:58:56 -0500203 /* setup the bats */
Becky Bruce1a41f7c2008-01-23 16:31:00 -0600204 bl early_bats
Jon Loeligerdebb7352006-04-26 17:58:56 -0500205
Jon Loeligerdebb7352006-04-26 17:58:56 -0500206 /*
207 * Cache must be enabled here for stack-in-cache trick.
208 * This means we need to enable the BATS.
209 * Cache should be turned on after BATs, since by default
210 * everything is write-through.
211 */
212
213 /* enable address translation */
Becky Brucec1e1cf62008-11-05 14:55:34 -0600214 mfmsr r5
215 ori r5, r5, (MSR_IR | MSR_DR)
216 lis r3,addr_trans_enabled@h
217 ori r3, r3, addr_trans_enabled@l
218 mtspr SPRN_SRR0,r3
219 mtspr SPRN_SRR1,r5
220 rfi
Jon Loeligerdebb7352006-04-26 17:58:56 -0500221
Becky Brucec1e1cf62008-11-05 14:55:34 -0600222addr_trans_enabled:
Jon Loeligerdebb7352006-04-26 17:58:56 -0500223 /* enable and invalidate the data cache */
224/* bl l1dcache_enable */
Wolfgang Denk47a69892006-10-24 15:32:57 +0200225 bl dcache_enable
Jon Loeligerdebb7352006-04-26 17:58:56 -0500226 sync
227
228#if 1
229 bl icache_enable
230#endif
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500231
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#ifdef CONFIG_SYS_INIT_RAM_LOCK
Jon Loeligerdebb7352006-04-26 17:58:56 -0500233 bl lock_ram_in_cache
234 sync
235#endif
236
Becky Bruce3111d322008-11-06 17:37:35 -0600237#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
238 bl setup_ccsrbar
239#endif
240
Jon Loeligerdebb7352006-04-26 17:58:56 -0500241 /* set up the stack pointer in our newly created
242 * cache-ram (r1) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
244 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
Jon Loeligerdebb7352006-04-26 17:58:56 -0500245
Wolfgang Denk47a69892006-10-24 15:32:57 +0200246 li r0, 0 /* Make room for stack frame header and */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500247 stwu r0, -4(r1) /* clear final stack frame so that */
248 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
249
250 GET_GOT /* initialize GOT access */
Wolfgang Denk8c4734e2011-04-20 22:11:21 +0200251
Wolfgang Denk47a69892006-10-24 15:32:57 +0200252 /* run low-level CPU init code (from Flash) */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500253 bl cpu_init_f
254 sync
255
Wolfgang Denk47a69892006-10-24 15:32:57 +0200256#ifdef RUN_DIAG
Jon Loeligerdebb7352006-04-26 17:58:56 -0500257
Wolfgang Denk47a69892006-10-24 15:32:57 +0200258 /* Load PX_AUX register address in r4 */
Becky Brucec759a012008-11-06 17:36:04 -0600259 lis r4, PIXIS_BASE@h
Wolfgang Denk47a69892006-10-24 15:32:57 +0200260 ori r4, r4, 0x6
261 /* Load contents of PX_AUX in r3 bits 24 to 31*/
262 lbz r3, 0(r4)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500263
Wolfgang Denk47a69892006-10-24 15:32:57 +0200264 /* Mask and obtain the bit in r3 */
265 rlwinm. r3, r3, 0, 24, 24
266 /* If not zero, jump and continue with u-boot */
267 bne diag_done
Jon Loeligerdebb7352006-04-26 17:58:56 -0500268
Wolfgang Denk47a69892006-10-24 15:32:57 +0200269 /* Load back contents of PX_AUX in r3 bits 24 to 31 */
270 lbz r3, 0(r4)
271 /* Set the MSB of the register value */
272 ori r3, r3, 0x80
273 /* Write value in r3 back to PX_AUX */
274 stb r3, 0(r4)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500275
Wolfgang Denk47a69892006-10-24 15:32:57 +0200276 /* Get the address to jump to in r3*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277 lis r3, CONFIG_SYS_DIAG_ADDR@h
278 ori r3, r3, CONFIG_SYS_DIAG_ADDR@l
Jon Loeligerdebb7352006-04-26 17:58:56 -0500279
Wolfgang Denk47a69892006-10-24 15:32:57 +0200280 /* Load the LR with the branch address */
281 mtlr r3
Jon Loeligerdebb7352006-04-26 17:58:56 -0500282
Wolfgang Denk47a69892006-10-24 15:32:57 +0200283 /* Branch to diagnostic */
284 blr
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500285
286diag_done:
287#endif
Jon Loeligerdebb7352006-04-26 17:58:56 -0500288
Wolfgang Denk47a69892006-10-24 15:32:57 +0200289/* bl l2cache_enable */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500290
Wolfgang Denk47a69892006-10-24 15:32:57 +0200291 /* run 1st part of board init code (from Flash) */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500292 bl board_init_f
293 sync
294
Peter Tyser52ebd9c2010-09-14 19:13:53 -0500295 /* NOTREACHED - board_init_f() does not return */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500296
297 .globl invalidate_bats
298invalidate_bats:
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500299
Jon Loeligercfc7a7f2007-08-02 14:42:20 -0500300 li r0, 0
Jon Loeligerdebb7352006-04-26 17:58:56 -0500301 /* invalidate BATs */
302 mtspr IBAT0U, r0
303 mtspr IBAT1U, r0
304 mtspr IBAT2U, r0
305 mtspr IBAT3U, r0
Wolfgang Denk47a69892006-10-24 15:32:57 +0200306 mtspr IBAT4U, r0
307 mtspr IBAT5U, r0
308 mtspr IBAT6U, r0
309 mtspr IBAT7U, r0
Jon Loeligerdebb7352006-04-26 17:58:56 -0500310
311 isync
312 mtspr DBAT0U, r0
313 mtspr DBAT1U, r0
314 mtspr DBAT2U, r0
315 mtspr DBAT3U, r0
Wolfgang Denk47a69892006-10-24 15:32:57 +0200316 mtspr DBAT4U, r0
317 mtspr DBAT5U, r0
318 mtspr DBAT6U, r0
319 mtspr DBAT7U, r0
Jon Loeligerdebb7352006-04-26 17:58:56 -0500320
321 isync
322 sync
323 blr
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500324
Becky Bruce1605cc92011-10-03 19:10:51 -0500325#define CONFIG_BAT_PAIR(n) \
326 lis r4, CONFIG_SYS_IBAT##n##L@h; \
327 ori r4, r4, CONFIG_SYS_IBAT##n##L@l; \
328 lis r3, CONFIG_SYS_IBAT##n##U@h; \
329 ori r3, r3, CONFIG_SYS_IBAT##n##U@l; \
330 mtspr IBAT##n##L, r4; \
331 mtspr IBAT##n##U, r3; \
332 lis r4, CONFIG_SYS_DBAT##n##L@h; \
333 ori r4, r4, CONFIG_SYS_DBAT##n##L@l; \
334 lis r3, CONFIG_SYS_DBAT##n##U@h; \
335 ori r3, r3, CONFIG_SYS_DBAT##n##U@l; \
336 mtspr DBAT##n##L, r4; \
337 mtspr DBAT##n##U, r3;
338
339/*
340 * setup_bats:
341 *
342 * Set up the final BAT registers now that setup is done.
343 *
344 * Assumes that:
345 * 1) Address translation is enabled upon entry
346 * 2) The boot rom is still accessible via 1:1 translation
347 */
348 .globl setup_bats
349setup_bats:
350 mflr r5
351 sync
352
353 /*
354 * When we disable address translation, we will get 1:1 (VA==PA)
355 * translation. The only place we know for sure is safe for that is
356 * the bootrom where we originally started out. Pop back into there.
357 */
358 lis r4, CONFIG_SYS_MONITOR_BASE_EARLY@h
359 ori r4, r4, CONFIG_SYS_MONITOR_BASE_EARLY@l
360 addi r4, r4, trans_disabled - _start + EXC_OFF_SYS_RESET
361
362 /* disable address translation */
363 mfmsr r3
364 rlwinm r3, r3, 0, 28, 25
365 mtspr SRR0, r4
366 mtspr SRR1, r3
367 rfi
368
369trans_disabled:
370#if defined(CONFIG_SYS_DBAT0U) && defined(CONFIG_SYS_DBAT0L) \
371 && defined(CONFIG_SYS_IBAT0U) && defined(CONFIG_SYS_IBAT0L)
372 CONFIG_BAT_PAIR(0)
373#endif
374 CONFIG_BAT_PAIR(1)
375 CONFIG_BAT_PAIR(2)
376 CONFIG_BAT_PAIR(3)
377 CONFIG_BAT_PAIR(4)
378 CONFIG_BAT_PAIR(5)
379 CONFIG_BAT_PAIR(6)
380 CONFIG_BAT_PAIR(7)
381
382 sync
383 isync
384
385 /* Turn translation back on and return */
386 mfmsr r3
387 ori r3, r3, (MSR_IR | MSR_DR)
388 mtspr SPRN_SRR0,r5
389 mtspr SPRN_SRR1,r3
390 rfi
391
Becky Bruce1a41f7c2008-01-23 16:31:00 -0600392/*
393 * early_bats:
394 *
395 * Set up bats needed early on - this is usually the BAT for the
Becky Bruce104992f2008-11-02 18:19:32 -0600396 * stack-in-cache, the Flash, and CCSR space
Becky Bruce1a41f7c2008-01-23 16:31:00 -0600397 */
398 .globl early_bats
399early_bats:
Becky Bruce104992f2008-11-02 18:19:32 -0600400 /* IBAT 3 */
401 lis r4, CONFIG_SYS_IBAT3L@h
402 ori r4, r4, CONFIG_SYS_IBAT3L@l
403 lis r3, CONFIG_SYS_IBAT3U@h
404 ori r3, r3, CONFIG_SYS_IBAT3U@l
405 mtspr IBAT3L, r4
406 mtspr IBAT3U, r3
407 isync
408
409 /* DBAT 3 */
410 lis r4, CONFIG_SYS_DBAT3L@h
411 ori r4, r4, CONFIG_SYS_DBAT3L@l
412 lis r3, CONFIG_SYS_DBAT3U@h
413 ori r3, r3, CONFIG_SYS_DBAT3U@l
414 mtspr DBAT3L, r4
415 mtspr DBAT3U, r3
416 isync
417
Becky Bruce1a41f7c2008-01-23 16:31:00 -0600418 /* IBAT 5 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200419 lis r4, CONFIG_SYS_IBAT5L@h
420 ori r4, r4, CONFIG_SYS_IBAT5L@l
421 lis r3, CONFIG_SYS_IBAT5U@h
422 ori r3, r3, CONFIG_SYS_IBAT5U@l
Becky Bruce1a41f7c2008-01-23 16:31:00 -0600423 mtspr IBAT5L, r4
424 mtspr IBAT5U, r3
Jon Loeligerdebb7352006-04-26 17:58:56 -0500425 isync
426
Becky Bruce1a41f7c2008-01-23 16:31:00 -0600427 /* DBAT 5 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200428 lis r4, CONFIG_SYS_DBAT5L@h
429 ori r4, r4, CONFIG_SYS_DBAT5L@l
430 lis r3, CONFIG_SYS_DBAT5U@h
431 ori r3, r3, CONFIG_SYS_DBAT5U@l
Becky Bruce1a41f7c2008-01-23 16:31:00 -0600432 mtspr DBAT5L, r4
433 mtspr DBAT5U, r3
434 isync
Jon Loeligerdebb7352006-04-26 17:58:56 -0500435
Becky Bruce1a41f7c2008-01-23 16:31:00 -0600436 /* IBAT 6 */
Becky Brucebf9a8c32008-11-05 14:55:35 -0600437 lis r4, CONFIG_SYS_IBAT6L_EARLY@h
438 ori r4, r4, CONFIG_SYS_IBAT6L_EARLY@l
439 lis r3, CONFIG_SYS_IBAT6U_EARLY@h
440 ori r3, r3, CONFIG_SYS_IBAT6U_EARLY@l
Becky Bruce1a41f7c2008-01-23 16:31:00 -0600441 mtspr IBAT6L, r4
442 mtspr IBAT6U, r3
443 isync
444
445 /* DBAT 6 */
Becky Brucebf9a8c32008-11-05 14:55:35 -0600446 lis r4, CONFIG_SYS_DBAT6L_EARLY@h
447 ori r4, r4, CONFIG_SYS_DBAT6L_EARLY@l
448 lis r3, CONFIG_SYS_DBAT6U_EARLY@h
449 ori r3, r3, CONFIG_SYS_DBAT6U_EARLY@l
Becky Bruce1a41f7c2008-01-23 16:31:00 -0600450 mtspr DBAT6L, r4
451 mtspr DBAT6U, r3
452 isync
Becky Bruce3111d322008-11-06 17:37:35 -0600453
454#if(CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
455 /* IBAT 7 */
456 lis r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@h
457 ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_IBATL@l
458 lis r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@h
459 ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_IBATU@l
460 mtspr IBAT7L, r4
461 mtspr IBAT7U, r3
462 isync
463
464 /* DBAT 7 */
465 lis r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@h
466 ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_DBATL@l
467 lis r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@h
468 ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_DBATU@l
469 mtspr DBAT7L, r4
470 mtspr DBAT7U, r3
471 isync
472#endif
Becky Bruce1a41f7c2008-01-23 16:31:00 -0600473 blr
474
475 .globl clear_tlbs
476clear_tlbs:
477 addis r3, 0, 0x0000
478 addis r5, 0, 0x4
479 isync
480tlblp:
481 tlbie r3
482 sync
483 addi r3, r3, 0x1000
484 cmp 0, 0, r3, r5
485 blt tlblp
Jon Loeligerdebb7352006-04-26 17:58:56 -0500486 blr
487
Jon Loeligerdebb7352006-04-26 17:58:56 -0500488 .globl disable_addr_trans
489disable_addr_trans:
490 /* disable address translation */
491 mflr r4
492 mfmsr r3
493 andi. r0, r3, (MSR_IR | MSR_DR)
494 beqlr
495 andc r3, r3, r0
496 mtspr SRR0, r4
497 mtspr SRR1, r3
498 rfi
499
500/*
501 * This code finishes saving the registers to the exception frame
502 * and jumps to the appropriate handler for the exception.
503 * Register r21 is pointer into trap frame, r1 has new stack pointer.
504 */
505 .globl transfer_to_handler
506transfer_to_handler:
507 stw r22,_NIP(r21)
508 lis r22,MSR_POW@h
509 andc r23,r23,r22
510 stw r23,_MSR(r21)
511 SAVE_GPR(7, r21)
512 SAVE_4GPRS(8, r21)
513 SAVE_8GPRS(12, r21)
514 SAVE_8GPRS(24, r21)
515 mflr r23
516 andi. r24,r23,0x3f00 /* get vector offset */
517 stw r24,TRAP(r21)
518 li r22,0
519 stw r22,RESULT(r21)
520 mtspr SPRG2,r22 /* r1 is now kernel sp */
521 lwz r24,0(r23) /* virtual address of handler */
522 lwz r23,4(r23) /* where to go when done */
523 mtspr SRR0,r24
524 mtspr SRR1,r20
525 mtlr r23
526 SYNC
527 rfi /* jump to handler, enable MMU */
528
529int_return:
530 mfmsr r28 /* Disable interrupts */
531 li r4,0
532 ori r4,r4,MSR_EE
533 andc r28,r28,r4
534 SYNC /* Some chip revs need this... */
535 mtmsr r28
536 SYNC
537 lwz r2,_CTR(r1)
538 lwz r0,_LINK(r1)
539 mtctr r2
540 mtlr r0
541 lwz r2,_XER(r1)
542 lwz r0,_CCR(r1)
543 mtspr XER,r2
544 mtcrf 0xFF,r0
545 REST_10GPRS(3, r1)
546 REST_10GPRS(13, r1)
547 REST_8GPRS(23, r1)
548 REST_GPR(31, r1)
549 lwz r2,_NIP(r1) /* Restore environment */
550 lwz r0,_MSR(r1)
551 mtspr SRR0,r2
552 mtspr SRR1,r0
553 lwz r0,GPR0(r1)
554 lwz r2,GPR2(r1)
555 lwz r1,GPR1(r1)
556 SYNC
557 rfi
558
559 .globl dc_read
560dc_read:
561 blr
562
563 .globl get_pvr
564get_pvr:
565 mfspr r3, PVR
566 blr
567
568 .globl get_svr
569get_svr:
570 mfspr r3, SVR
571 blr
572
573
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500574/*
Wolfgang Denk47a69892006-10-24 15:32:57 +0200575 * Function: in8
576 * Description: Input 8 bits
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500577 */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500578 .globl in8
579in8:
580 lbz r3,0x0000(r3)
581 blr
582
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500583/*
Wolfgang Denk47a69892006-10-24 15:32:57 +0200584 * Function: out8
585 * Description: Output 8 bits
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500586 */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500587 .globl out8
588out8:
589 stb r4,0x0000(r3)
590 blr
591
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500592/*
Wolfgang Denk47a69892006-10-24 15:32:57 +0200593 * Function: out16
594 * Description: Output 16 bits
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500595 */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500596 .globl out16
597out16:
598 sth r4,0x0000(r3)
599 blr
600
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500601/*
Wolfgang Denk47a69892006-10-24 15:32:57 +0200602 * Function: out16r
603 * Description: Byte reverse and output 16 bits
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500604 */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500605 .globl out16r
606out16r:
607 sthbrx r4,r0,r3
608 blr
609
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500610/*
Wolfgang Denk47a69892006-10-24 15:32:57 +0200611 * Function: out32
612 * Description: Output 32 bits
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500613 */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500614 .globl out32
615out32:
616 stw r4,0x0000(r3)
617 blr
618
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500619/*
Wolfgang Denk47a69892006-10-24 15:32:57 +0200620 * Function: out32r
621 * Description: Byte reverse and output 32 bits
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500622 */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500623 .globl out32r
624out32r:
625 stwbrx r4,r0,r3
626 blr
627
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500628/*
Wolfgang Denk47a69892006-10-24 15:32:57 +0200629 * Function: in16
630 * Description: Input 16 bits
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500631 */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500632 .globl in16
633in16:
634 lhz r3,0x0000(r3)
635 blr
636
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500637/*
Wolfgang Denk47a69892006-10-24 15:32:57 +0200638 * Function: in16r
639 * Description: Input 16 bits and byte reverse
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500640 */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500641 .globl in16r
642in16r:
643 lhbrx r3,r0,r3
644 blr
645
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500646/*
Wolfgang Denk47a69892006-10-24 15:32:57 +0200647 * Function: in32
648 * Description: Input 32 bits
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500649 */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500650 .globl in32
651in32:
652 lwz 3,0x0000(3)
653 blr
654
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500655/*
Wolfgang Denk47a69892006-10-24 15:32:57 +0200656 * Function: in32r
657 * Description: Input 32 bits and byte reverse
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500658 */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500659 .globl in32r
660in32r:
661 lwbrx r3,r0,r3
662 blr
663
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500664/*
Jon Loeligerdebb7352006-04-26 17:58:56 -0500665 * void relocate_code (addr_sp, gd, addr_moni)
666 *
667 * This "function" does not return, instead it continues in RAM
668 * after relocating the monitor code.
669 *
670 * r3 = dest
671 * r4 = src
672 * r5 = length in bytes
673 * r6 = cachelinesize
674 */
675 .globl relocate_code
676relocate_code:
677
Wolfgang Denk47a69892006-10-24 15:32:57 +0200678 mr r1, r3 /* Set new stack pointer */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500679 mr r9, r4 /* Save copy of Global Data pointer */
680 mr r10, r5 /* Save copy of Destination Address */
Haiying Wang67256672006-08-15 15:13:15 -0400681
Joakim Tjernlund0f8aa152010-01-19 14:41:56 +0100682 GET_GOT
Jon Loeligerdebb7352006-04-26 17:58:56 -0500683 mr r3, r5 /* Destination Address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200684 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
685 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
Jon Loeligerdebb7352006-04-26 17:58:56 -0500686 lwz r5, GOT(__init_end)
687 sub r5, r5, r4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200688 li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500689
690 /*
691 * Fix GOT pointer:
692 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200693 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
Jon Loeligerdebb7352006-04-26 17:58:56 -0500694 *
695 * Offset:
696 */
697 sub r15, r10, r4
698
699 /* First our own GOT */
Joakim Tjernlund0f8aa152010-01-19 14:41:56 +0100700 add r12, r12, r15
Jon Loeligerdebb7352006-04-26 17:58:56 -0500701 /* then the one used by the C code */
702 add r30, r30, r15
703
704 /*
705 * Now relocate code
706 */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500707 cmplw cr1,r3,r4
708 addi r0,r5,3
709 srwi. r0,r0,2
710 beq cr1,4f /* In place copy is not necessary */
711 beq 7f /* Protect against 0 count */
712 mtctr r0
713 bge cr1,2f
714
715 la r8,-4(r4)
716 la r7,-4(r3)
7171: lwzu r0,4(r8)
718 stwu r0,4(r7)
719 bdnz 1b
720 b 4f
721
7222: slwi r0,r0,2
723 add r8,r4,r0
724 add r7,r3,r0
7253: lwzu r0,-4(r8)
726 stwu r0,-4(r7)
727 bdnz 3b
Jon Loeligerdebb7352006-04-26 17:58:56 -0500728/*
729 * Now flush the cache: note that we must start from a cache aligned
730 * address. Otherwise we might miss one cache line.
731 */
7324: cmpwi r6,0
733 add r5,r3,r5
734 beq 7f /* Always flush prefetch queue in any case */
735 subi r0,r6,1
736 andc r3,r3,r0
737 mr r4,r3
7385: dcbst 0,r4
739 add r4,r4,r6
740 cmplw r4,r5
741 blt 5b
742 sync /* Wait for all dcbst to complete on bus */
743 mr r4,r3
7446: icbi 0,r4
745 add r4,r4,r6
746 cmplw r4,r5
747 blt 6b
Wolfgang Denk47a69892006-10-24 15:32:57 +02007487: sync /* Wait for all icbi to complete on bus */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500749 isync
750
751/*
752 * We are done. Do not return, instead branch to second part of board
753 * initialization, now running from RAM.
754 */
755 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
756 mtlr r0
757 blr
758
759in_ram:
Jon Loeligerdebb7352006-04-26 17:58:56 -0500760 /*
Joakim Tjernlund0f8aa152010-01-19 14:41:56 +0100761 * Relocation Function, r12 point to got2+0x8000
Jon Loeligerdebb7352006-04-26 17:58:56 -0500762 *
763 * Adjust got2 pointers, no need to check for 0, this code
764 * already puts a few entries in the table.
765 */
766 li r0,__got2_entries@sectoff@l
767 la r3,GOT(_GOT2_TABLE_)
768 lwz r11,GOT(_GOT2_TABLE_)
769 mtctr r0
770 sub r11,r3,r11
771 addi r3,r3,-4
7721: lwzu r0,4(r3)
Joakim Tjernlundafc3ba02009-10-08 02:03:51 +0200773 cmpwi r0,0
774 beq- 2f
Jon Loeligerdebb7352006-04-26 17:58:56 -0500775 add r0,r0,r11
776 stw r0,0(r3)
Joakim Tjernlundafc3ba02009-10-08 02:03:51 +02007772: bdnz 1b
Jon Loeligerdebb7352006-04-26 17:58:56 -0500778
779 /*
780 * Now adjust the fixups and the pointers to the fixups
781 * in case we need to move ourselves again.
782 */
Joakim Tjernlundafc3ba02009-10-08 02:03:51 +0200783 li r0,__fixup_entries@sectoff@l
Jon Loeligerdebb7352006-04-26 17:58:56 -0500784 lwz r3,GOT(_FIXUP_TABLE_)
785 cmpwi r0,0
786 mtctr r0
787 addi r3,r3,-4
788 beq 4f
7893: lwzu r4,4(r3)
790 lwzux r0,r4,r11
Joakim Tjernlundd1e0b102010-10-14 11:51:44 +0200791 cmpwi r0,0
Jon Loeligerdebb7352006-04-26 17:58:56 -0500792 add r0,r0,r11
Joakim Tjernlund34bbf612010-11-04 19:02:00 +0100793 stw r4,0(r3)
Joakim Tjernlundd1e0b102010-10-14 11:51:44 +0200794 beq- 5f
Jon Loeligerdebb7352006-04-26 17:58:56 -0500795 stw r0,0(r4)
Joakim Tjernlundd1e0b102010-10-14 11:51:44 +02007965: bdnz 3b
Jon Loeligerdebb7352006-04-26 17:58:56 -05007974:
798/* clear_bss: */
799 /*
800 * Now clear BSS segment
801 */
802 lwz r3,GOT(__bss_start)
Simon Glass3929fb02013-03-14 06:54:53 +0000803 lwz r4,GOT(__bss_end)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500804
805 cmplw 0, r3, r4
806 beq 6f
807
808 li r0, 0
8095:
810 stw r0, 0(r3)
811 addi r3, r3, 4
812 cmplw 0, r3, r4
813 bne 5b
8146:
Haiying Wang6cfea332006-05-10 09:38:06 -0500815 mr r3, r9 /* Init Date pointer */
816 mr r4, r10 /* Destination Address */
817 bl board_init_r
Jon Loeligerdebb7352006-04-26 17:58:56 -0500818
819 /* not reached - end relocate_code */
820/*-----------------------------------------------------------------------*/
821
822 /*
823 * Copy exception vector code to low memory
824 *
825 * r3: dest_addr
826 * r7: source address, r8: end address, r9: target address
827 */
828 .globl trap_init
829trap_init:
Joakim Tjernlund0f8aa152010-01-19 14:41:56 +0100830 mflr r4 /* save link register */
831 GET_GOT
Jon Loeligerdebb7352006-04-26 17:58:56 -0500832 lwz r7, GOT(_start)
833 lwz r8, GOT(_end_of_vectors)
834
835 li r9, 0x100 /* reset vector always at 0x100 */
836
837 cmplw 0, r7, r8
838 bgelr /* return if r7>=r8 - just in case */
Jon Loeligerdebb7352006-04-26 17:58:56 -05008391:
840 lwz r0, 0(r7)
841 stw r0, 0(r9)
842 addi r7, r7, 4
843 addi r9, r9, 4
844 cmplw 0, r7, r8
845 bne 1b
846
847 /*
848 * relocate `hdlr' and `int_return' entries
849 */
850 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
851 li r8, Alignment - _start + EXC_OFF_SYS_RESET
8522:
853 bl trap_reloc
854 addi r7, r7, 0x100 /* next exception vector */
855 cmplw 0, r7, r8
856 blt 2b
857
858 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
859 bl trap_reloc
860
861 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
862 bl trap_reloc
863
864 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
865 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
8663:
867 bl trap_reloc
868 addi r7, r7, 0x100 /* next exception vector */
869 cmplw 0, r7, r8
870 blt 3b
871
872 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
873 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
8744:
875 bl trap_reloc
876 addi r7, r7, 0x100 /* next exception vector */
877 cmplw 0, r7, r8
878 blt 4b
879
880 /* enable execptions from RAM vectors */
881 mfmsr r7
882 li r8,MSR_IP
883 andc r7,r7,r8
Jon Loeligercfc7a7f2007-08-02 14:42:20 -0500884 ori r7,r7,MSR_ME /* Enable Machine Check */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500885 mtmsr r7
886
887 mtlr r4 /* restore link register */
888 blr
889
Jon Loeligerdebb7352006-04-26 17:58:56 -0500890.globl enable_ext_addr
891enable_ext_addr:
892 mfspr r0, HID0
Wolfgang Denk47a69892006-10-24 15:32:57 +0200893 lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h
Jon Loeligerdebb7352006-04-26 17:58:56 -0500894 ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l
Wolfgang Denk47a69892006-10-24 15:32:57 +0200895 mtspr HID0, r0
Jon Loeligerdebb7352006-04-26 17:58:56 -0500896 sync
897 isync
898 blr
899
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200900#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500901.globl setup_ccsrbar
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500902setup_ccsrbar:
Jon Loeligerdebb7352006-04-26 17:58:56 -0500903 /* Special sequence needed to update CCSRBAR itself */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200904 lis r4, CONFIG_SYS_CCSRBAR_DEFAULT@h
905 ori r4, r4, CONFIG_SYS_CCSRBAR_DEFAULT@l
Jon Loeligerdebb7352006-04-26 17:58:56 -0500906
Becky Bruce3111d322008-11-06 17:37:35 -0600907 lis r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@h
908 ori r5, r5, CONFIG_SYS_CCSRBAR_PHYS_LOW@l
909 srwi r5,r5,12
910 li r6, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
911 rlwimi r5,r6,20,8,11
912 stw r5, 0(r4) /* Store physical value of CCSR */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500913 isync
914
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200915 lis r5, CONFIG_SYS_TEXT_BASE@h
916 ori r5,r5,CONFIG_SYS_TEXT_BASE@l
Jon Loeligerdebb7352006-04-26 17:58:56 -0500917 lwz r5, 0(r5)
918 isync
919
Becky Bruce3111d322008-11-06 17:37:35 -0600920 /* Use VA of CCSR to do read */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200921 lis r3, CONFIG_SYS_CCSRBAR@h
922 lwz r5, CONFIG_SYS_CCSRBAR@l(r3)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500923 isync
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500924
Jon Loeligerdebb7352006-04-26 17:58:56 -0500925 blr
926#endif
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500927
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200928#ifdef CONFIG_SYS_INIT_RAM_LOCK
Jon Loeligerdebb7352006-04-26 17:58:56 -0500929lock_ram_in_cache:
930 /* Allocate Initial RAM in data cache.
931 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200932 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
933 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
Wolfgang Denk553f0982010-10-26 13:32:32 +0200934 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200935 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
Nick Spence39243842008-08-28 14:09:15 -0700936 mtctr r4
Jon Loeligerdebb7352006-04-26 17:58:56 -05009371:
938 dcbz r0, r3
939 addi r3, r3, 32
940 bdnz 1b
941#if 1
942/* Lock the data cache */
943 mfspr r0, HID0
944 ori r0, r0, 0x1000
945 sync
946 mtspr HID0, r0
947 sync
948 blr
949#endif
950#if 0
951 /* Lock the first way of the data cache */
952 mfspr r0, LDSTCR
953 ori r0, r0, 0x0080
954#if defined(CONFIG_ALTIVEC)
955 dssall
956#endif
957 sync
958 mtspr LDSTCR, r0
959 sync
960 isync
961 blr
962#endif
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500963
Jon Loeligerdebb7352006-04-26 17:58:56 -0500964.globl unlock_ram_in_cache
965unlock_ram_in_cache:
966 /* invalidate the INIT_RAM section */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200967 lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
968 ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
Wolfgang Denk553f0982010-10-26 13:32:32 +0200969 li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200970 (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
Nick Spence39243842008-08-28 14:09:15 -0700971 mtctr r4
Jon Loeligerdebb7352006-04-26 17:58:56 -05009721: icbi r0, r3
973 addi r3, r3, 32
974 bdnz 1b
Wolfgang Denk47a69892006-10-24 15:32:57 +0200975 sync /* Wait for all icbi to complete on bus */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500976 isync
977#if 1
978/* Unlock the data cache and invalidate it */
Wolfgang Denk47a69892006-10-24 15:32:57 +0200979 mfspr r0, HID0
980 li r3,0x1000
981 andc r0,r0,r3
Jon Loeligerdebb7352006-04-26 17:58:56 -0500982 li r3,0x0400
983 or r0,r0,r3
984 sync
Wolfgang Denk47a69892006-10-24 15:32:57 +0200985 mtspr HID0, r0
Jon Loeligerdebb7352006-04-26 17:58:56 -0500986 sync
987 blr
988#endif
Jon Loeligerffff3ae2006-08-22 12:06:18 -0500989#if 0
Jon Loeligerdebb7352006-04-26 17:58:56 -0500990 /* Unlock the first way of the data cache */
Wolfgang Denk47a69892006-10-24 15:32:57 +0200991 mfspr r0, LDSTCR
992 li r3,0x0080
993 andc r0,r0,r3
Jon Loeligerdebb7352006-04-26 17:58:56 -0500994#ifdef CONFIG_ALTIVEC
995 dssall
996#endif
997 sync
Wolfgang Denk47a69892006-10-24 15:32:57 +0200998 mtspr LDSTCR, r0
Jon Loeligerdebb7352006-04-26 17:58:56 -0500999 sync
1000 isync
1001 li r3,0x0400
1002 or r0,r0,r3
1003 sync
Wolfgang Denk47a69892006-10-24 15:32:57 +02001004 mtspr HID0, r0
Jon Loeligerdebb7352006-04-26 17:58:56 -05001005 sync
1006 blr
1007#endif
1008#endif