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wdenkf12e5682003-07-07 20:07:54 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2000-2005
wdenkf12e5682003-07-07 20:07:54 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
37#define CONFIG_TQM860M 1 /* ...on a TQM8xxM module */
38
39#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
40#undef CONFIG_8xx_CONS_SMC2
41#undef CONFIG_8xx_CONS_NONE
42
43#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
44
wdenkae3af052003-08-07 22:18:11 +000045#define CONFIG_BOOTCOUNT_LIMIT
wdenkf12e5682003-07-07 20:07:54 +000046
wdenkae3af052003-08-07 22:18:11 +000047#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenkf12e5682003-07-07 20:07:54 +000048
49#define CONFIG_BOARD_TYPES 1 /* support board types */
50
51#define CONFIG_PREBOOT "echo;" \
52 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
53 "echo"
54
55#undef CONFIG_BOOTARGS
56
57#define CONFIG_EXTRA_ENV_SETTINGS \
58 "netdev=eth0\0" \
59 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010060 "nfsroot=${serverip}:${rootpath}\0" \
wdenkf12e5682003-07-07 20:07:54 +000061 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010062 "addip=setenv bootargs ${bootargs} " \
63 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
64 ":${hostname}:${netdev}:off panic=1\0" \
wdenkf12e5682003-07-07 20:07:54 +000065 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010066 "bootm ${kernel_addr}\0" \
wdenkf12e5682003-07-07 20:07:54 +000067 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010068 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
69 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenkf12e5682003-07-07 20:07:54 +000070 "rootpath=/opt/eldk/ppc_8xx\0" \
71 "bootfile=/tftpboot/TQM860M/uImage\0" \
72 "kernel_addr=40080000\0" \
73 "ramdisk_addr=40180000\0" \
74 ""
75#define CONFIG_BOOTCOMMAND "run flash_self"
76
77#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
78#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
79
80#undef CONFIG_WATCHDOG /* watchdog disabled */
81
82#define CONFIG_STATUS_LED 1 /* Status LED enabled */
83
84#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
85
Jon Loeliger37d4bb72007-07-09 21:38:02 -050086/*
87 * BOOTP options
88 */
89#define CONFIG_BOOTP_SUBNETMASK
90#define CONFIG_BOOTP_GATEWAY
91#define CONFIG_BOOTP_HOSTNAME
92#define CONFIG_BOOTP_BOOTPATH
93#define CONFIG_BOOTP_BOOTFILESIZE
94
wdenkf12e5682003-07-07 20:07:54 +000095
96#define CONFIG_MAC_PARTITION
97#define CONFIG_DOS_PARTITION
98
99#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
100
wdenkf12e5682003-07-07 20:07:54 +0000101
Jon Loeliger26946902007-07-04 22:30:50 -0500102/*
103 * Command line configuration.
104 */
105#include <config_cmd_default.h>
106
107#define CONFIG_CMD_ASKENV
108#define CONFIG_CMD_DATE
109#define CONFIG_CMD_DHCP
110#define CONFIG_CMD_ELF
111#define CONFIG_CMD_IDE
112#define CONFIG_CMD_NFS
113#define CONFIG_CMD_SNTP
114
wdenkf12e5682003-07-07 20:07:54 +0000115
116/*
117 * Miscellaneous configurable options
118 */
119#define CFG_LONGHELP /* undef to save memory */
120#define CFG_PROMPT "=> " /* Monitor Command Prompt */
121
Wolfgang Denk2751a952006-10-28 02:29:14 +0200122#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
123#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
wdenkf12e5682003-07-07 20:07:54 +0000124#ifdef CFG_HUSH_PARSER
125#define CFG_PROMPT_HUSH_PS2 "> "
126#endif
127
Jon Loeliger26946902007-07-04 22:30:50 -0500128#if defined(CONFIG_CMD_KGDB)
wdenkf12e5682003-07-07 20:07:54 +0000129#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
130#else
131#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
132#endif
133#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
134#define CFG_MAXARGS 16 /* max number of command args */
135#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
136
137#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
138#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
139
140#define CFG_LOAD_ADDR 0x100000 /* default load address */
141
142#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
143
144#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
145
146/*
147 * Low Level Configuration Settings
148 * (address mappings, register initial values, etc.)
149 * You should know what you are doing if you make changes here.
150 */
151/*-----------------------------------------------------------------------
152 * Internal Memory Mapped Register
153 */
154#define CFG_IMMR 0xFFF00000
155
156/*-----------------------------------------------------------------------
157 * Definitions for initial stack pointer and data area (in DPRAM)
158 */
159#define CFG_INIT_RAM_ADDR CFG_IMMR
160#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
161#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
162#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
163#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
164
165/*-----------------------------------------------------------------------
166 * Start addresses for the final memory configuration
167 * (Set up by the startup code)
168 * Please note that CFG_SDRAM_BASE _must_ start at 0
169 */
170#define CFG_SDRAM_BASE 0x00000000
171#define CFG_FLASH_BASE 0x40000000
172#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
173#define CFG_MONITOR_BASE CFG_FLASH_BASE
174#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
175
176/*
177 * For booting Linux, the board info and command line data
178 * have to be in the first 8 MB of memory, since this is
179 * the maximum mapped by the Linux kernel during initialization.
180 */
181#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
182
183/*-----------------------------------------------------------------------
184 * FLASH organization
185 */
186#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
187#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
188
189#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
190#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
191
192#define CFG_ENV_IS_IN_FLASH 1
193#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
194#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
195#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
196
197/* Address and size of Redundant Environment Sector */
198#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
199#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
200
201/*-----------------------------------------------------------------------
202 * Hardware Information Block
203 */
204#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
205#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
206#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
207
208/*-----------------------------------------------------------------------
209 * Cache Configuration
210 */
211#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500212#if defined(CONFIG_CMD_KGDB)
wdenkf12e5682003-07-07 20:07:54 +0000213#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
214#endif
215
216/*-----------------------------------------------------------------------
217 * SYPCR - System Protection Control 11-9
218 * SYPCR can only be written once after reset!
219 *-----------------------------------------------------------------------
220 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
221 */
222#if defined(CONFIG_WATCHDOG)
223#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
224 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
225#else
226#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
227#endif
228
229/*-----------------------------------------------------------------------
230 * SIUMCR - SIU Module Configuration 11-6
231 *-----------------------------------------------------------------------
232 * PCMCIA config., multi-function pin tri-state
233 */
234#ifndef CONFIG_CAN_DRIVER
235#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
236#else /* we must activate GPL5 in the SIUMCR for CAN */
237#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
238#endif /* CONFIG_CAN_DRIVER */
239
240/*-----------------------------------------------------------------------
241 * TBSCR - Time Base Status and Control 11-26
242 *-----------------------------------------------------------------------
243 * Clear Reference Interrupt Status, Timebase freezing enabled
244 */
245#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
246
247/*-----------------------------------------------------------------------
248 * RTCSC - Real-Time Clock Status and Control Register 11-27
249 *-----------------------------------------------------------------------
250 */
251#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
252
253/*-----------------------------------------------------------------------
254 * PISCR - Periodic Interrupt Status and Control 11-31
255 *-----------------------------------------------------------------------
256 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
257 */
258#define CFG_PISCR (PISCR_PS | PISCR_PITF)
259
260/*-----------------------------------------------------------------------
261 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
262 *-----------------------------------------------------------------------
263 * Reset PLL lock status sticky bit, timer expired status bit and timer
264 * interrupt status bit
wdenkf12e5682003-07-07 20:07:54 +0000265 */
wdenkf12e5682003-07-07 20:07:54 +0000266#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenkf12e5682003-07-07 20:07:54 +0000267
268/*-----------------------------------------------------------------------
269 * SCCR - System Clock and reset Control Register 15-27
270 *-----------------------------------------------------------------------
271 * Set clock output, timebase and RTC source and divider,
272 * power management and some other internal clocks
273 */
274#define SCCR_MASK SCCR_EBDF11
wdenke9132ea2004-04-24 23:23:30 +0000275#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenkf12e5682003-07-07 20:07:54 +0000276 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
277 SCCR_DFALCD00)
wdenkf12e5682003-07-07 20:07:54 +0000278
279/*-----------------------------------------------------------------------
280 * PCMCIA stuff
281 *-----------------------------------------------------------------------
282 *
283 */
284#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
285#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
286#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
287#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
288#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
289#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
290#define CFG_PCMCIA_IO_ADDR (0xEC000000)
291#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
292
293/*-----------------------------------------------------------------------
294 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
295 *-----------------------------------------------------------------------
296 */
297
298#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
299
300#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
301#undef CONFIG_IDE_LED /* LED for ide not supported */
302#undef CONFIG_IDE_RESET /* reset for ide not supported */
303
304#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
305#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
306
307#define CFG_ATA_IDE0_OFFSET 0x0000
308
309#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
310
311/* Offset for data I/O */
312#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
313
314/* Offset for normal register accesses */
315#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
316
317/* Offset for alternate registers */
318#define CFG_ATA_ALT_OFFSET 0x0100
319
320/*-----------------------------------------------------------------------
321 *
322 *-----------------------------------------------------------------------
323 *
324 */
325#define CFG_DER 0
326
327/*
328 * Init Memory Controller:
329 *
330 * BR0/1 and OR0/1 (FLASH)
331 */
332
333#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
334#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
335
336/* used to re-map FLASH both when starting from SRAM or FLASH:
337 * restrict access enough to keep SRAM working (if any)
338 * but not too much to meddle with FLASH accesses
339 */
340#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
341#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
342
343/*
344 * FLASH timing:
345 */
wdenkf12e5682003-07-07 20:07:54 +0000346#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
347 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenkf12e5682003-07-07 20:07:54 +0000348
349#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
350#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
351#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
352
353#define CFG_OR1_REMAP CFG_OR0_REMAP
354#define CFG_OR1_PRELIM CFG_OR0_PRELIM
355#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
356
357/*
358 * BR2/3 and OR2/3 (SDRAM)
359 *
360 */
361#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
362#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
363#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
364
365/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
366#define CFG_OR_TIMING_SDRAM 0x00000A00
367
368#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
369#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
370
371#ifndef CONFIG_CAN_DRIVER
372#define CFG_OR3_PRELIM CFG_OR2_PRELIM
373#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
374#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
375#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
376#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
377#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
378#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
379 BR_PS_8 | BR_MS_UPMB | BR_V )
380#endif /* CONFIG_CAN_DRIVER */
381
382/*
383 * Memory Periodic Timer Prescaler
384 *
385 * The Divider for PTA (refresh timer) configuration is based on an
386 * example SDRAM configuration (64 MBit, one bank). The adjustment to
387 * the number of chip selects (NCS) and the actually needed refresh
388 * rate is done by setting MPTPR.
389 *
390 * PTA is calculated from
391 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
392 *
393 * gclk CPU clock (not bus clock!)
394 * Trefresh Refresh cycle * 4 (four word bursts used)
395 *
396 * 4096 Rows from SDRAM example configuration
397 * 1000 factor s -> ms
398 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
399 * 4 Number of refresh cycles per period
400 * 64 Refresh cycle in ms per number of rows
401 * --------------------------------------------
402 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
403 *
404 * 50 MHz => 50.000.000 / Divider = 98
405 * 66 Mhz => 66.000.000 / Divider = 129
406 * 80 Mhz => 80.000.000 / Divider = 156
407 */
wdenke9132ea2004-04-24 23:23:30 +0000408
409#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
410#define CFG_MAMR_PTA 98
wdenkf12e5682003-07-07 20:07:54 +0000411
412/*
413 * For 16 MBit, refresh rates could be 31.3 us
414 * (= 64 ms / 2K = 125 / quad bursts).
415 * For a simpler initialization, 15.6 us is used instead.
416 *
417 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
418 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
419 */
420#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
421#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
422
423/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
424#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
425#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
426
427/*
428 * MAMR settings for SDRAM
429 */
430
431/* 8 column SDRAM */
432#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
433 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
434 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
435/* 9 column SDRAM */
436#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
437 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
438 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
439
440
441/*
442 * Internal Definitions
443 *
444 * Boot Flags
445 */
446#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
447#define BOOTFLAG_WARM 0x02 /* Software reboot */
448
449#define CONFIG_SCC1_ENET
450#define CONFIG_FEC_ENET
451#define CONFIG_ETHPRIME "SCC ETHERNET"
452
453#endif /* __CONFIG_H */