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wdenkca0e7742004-06-09 15:37:23 +00001/*
2 * (C) Copyright 2002
3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
4 *
5 * (C) Copyright 2002
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
wdenkca0e7742004-06-09 15:37:23 +000031/* High Level Configuration Options */
32#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
33#define CONFIG_XSENGINE 1
34#define CONFIG_MMC 1
Jean-Christophe PLAGNIOL-VILLARDe78220f2007-10-19 06:33:45 +020035#define CONFIG_DOS_PARTITION 1
Jean-Christophe PLAGNIOL-VILLARD41243822008-02-10 17:05:20 +010036#define BOARD_LATE_INIT 1
wdenkca0e7742004-06-09 15:37:23 +000037#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020038/* we will never enable dcache, because we have to setup MMU first */
39#define CONFIG_SYS_NO_DCACHE
40
Micha Kalfon94a33122009-02-11 19:50:11 +020041#define CONFIG_SYS_HZ 1000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020042#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
wdenkca0e7742004-06-09 15:37:23 +000043
44#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
45#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
46#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
47#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
48#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
49#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
50#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
51#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
52#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053#define CONFIG_SYS_DRAM_BASE 0xa0000000
54#define CONFIG_SYS_DRAM_SIZE 0x04000000
wdenkca0e7742004-06-09 15:37:23 +000055
56/* FLASH organization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
58#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
wdenkca0e7742004-06-09 15:37:23 +000059#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
60#define PHYS_FLASH_2 0x00000000 /* Flash Bank #2 */
61#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 127 KB sectors */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020062#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
Wolfgang Denk700a0c62005-08-08 01:03:24 +020063
64/*
65 * JFFS2 partitions
66 */
67/* No command line, one static partition, whole device */
Stefan Roese68d7d652009-03-19 13:30:36 +010068#undef CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +020069#define CONFIG_JFFS2_DEV "nor0"
70#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
71#define CONFIG_JFFS2_PART_OFFSET 0x00000000
72
73/* mtdparts command line support */
74/* Note: fake mtd_id used, no linux mtd map file */
75/*
Stefan Roese68d7d652009-03-19 13:30:36 +010076#define CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +020077#define MTDIDS_DEFAULT "nor0=xsengine-0"
78#define MTDPARTS_DEFAULT "mtdparts=xsengine-0:256k(uboot),1m(kernel1),8m(kernel2)"
79*/
wdenkca0e7742004-06-09 15:37:23 +000080
81/* Environment settings */
82#define CONFIG_ENV_OVERWRITE
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020083#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020084#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x40000) /* Addr of Environment Sector (after monitor)*/
85#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE /* Size of the Environment Sector */
86#define CONFIG_ENV_SIZE 0x4000 /* 16kB Total Size of Environment Sector */
wdenkca0e7742004-06-09 15:37:23 +000087
88/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089#define CONFIG_SYS_FLASH_ERASE_TOUT (75*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
90#define CONFIG_SYS_FLASH_WRITE_TOUT (50*CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenkca0e7742004-06-09 15:37:23 +000091
92/* Size of malloc() pool */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024)
94#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
wdenkca0e7742004-06-09 15:37:23 +000095
96/* Hardware drivers */
97#define CONFIG_DRIVER_SMC91111
98#define CONFIG_SMC91111_BASE 0x04000300
Jean-Christophe PLAGNIOL-VILLARD41243822008-02-10 17:05:20 +010099#define CONFIG_SMC_USE_32_BIT 1
wdenkca0e7742004-06-09 15:37:23 +0000100
101/* select serial console configuration */
Jean-Christophe PLAGNIOL-VILLARD379be582009-05-16 22:48:46 +0200102#define CONFIG_PXA_SERIAL
wdenkca0e7742004-06-09 15:37:23 +0000103#define CONFIG_FFUART 1
104
105/* allow to overwrite serial and ethaddr */
106#define CONFIG_BAUDRATE 115200
wdenkca0e7742004-06-09 15:37:23 +0000107
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500108/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500109 * BOOTP options
110 */
111#define CONFIG_BOOTP_BOOTFILESIZE
112#define CONFIG_BOOTP_BOOTPATH
113#define CONFIG_BOOTP_GATEWAY
114#define CONFIG_BOOTP_HOSTNAME
115
116
117/*
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500118 * Command line configuration.
119 */
120#include <config_cmd_default.h>
121
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500122#define CONFIG_CMD_FAT
123#define CONFIG_CMD_PING
124#define CONFIG_CMD_JFFS2
125
wdenkca0e7742004-06-09 15:37:23 +0000126
127#define CONFIG_BOOTDELAY 3
128#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF
129#define CONFIG_NETMASK 255.255.255.0
130#define CONFIG_IPADDR 192.168.1.50
131#define CONFIG_SERVERIP 192.168.1.2
132#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=jffs2 console=ttyS1,115200"
133#define CONFIG_CMDLINE_TAG
134
135/* Miscellaneous configurable options */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_HUSH_PARSER 1
137#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
138#define CONFIG_SYS_LONGHELP /* undef to save memory */
139#define CONFIG_SYS_PROMPT "XS-Engine u-boot> " /* Monitor Command Prompt */
140#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
141#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
142#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
143#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
144#define CONFIG_SYS_MEMTEST_START 0xA0400000 /* memtest works on */
145#define CONFIG_SYS_MEMTEST_END 0xA0800000 /* 4 ... 8 MB in DRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* valid baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_LOAD_ADDR 0xA0000000 /* load kernel to this address */
wdenkca0e7742004-06-09 15:37:23 +0000148
Jean-Christophe PLAGNIOL-VILLARDb03d92e2009-02-20 03:47:50 +0100149#ifdef CONFIG_MMC
150#define CONFIG_PXA_MMC
151#define CONFIG_CMD_MMC
152#define CONFIG_SYS_MMC_BASE 0xF0000000
153#endif
154
wdenkca0e7742004-06-09 15:37:23 +0000155/* Stack sizes - The stack sizes are set up in start.S using the settings below */
156#define CONFIG_STACKSIZE (128*1024) /* regular stack */
157#ifdef CONFIG_USE_IRQ
158#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
159#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
160#endif
161
162/* GP set register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_GPSR0_VAL 0x0000A000 /* CS1, PROG(FPGA) */
164#define CONFIG_SYS_GPSR1_VAL 0x00020000 /* nPWE */
165#define CONFIG_SYS_GPSR2_VAL 0x0000C000 /* CS2, CS3 */
wdenkca0e7742004-06-09 15:37:23 +0000166
167/* GP clear register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define CONFIG_SYS_GPCR0_VAL 0x00000000
169#define CONFIG_SYS_GPCR1_VAL 0x00000000
170#define CONFIG_SYS_GPCR2_VAL 0x00000000
wdenkca0e7742004-06-09 15:37:23 +0000171
172/* GP direction register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_GPDR0_VAL 0x0000A000 /* CS1, PROG(FPGA) */
174#define CONFIG_SYS_GPDR1_VAL 0x00022A80 /* nPWE, FFUART + BTUART pins */
175#define CONFIG_SYS_GPDR2_VAL 0x0000C000 /* CS2, CS3 */
wdenkca0e7742004-06-09 15:37:23 +0000176
177/* GP rising edge detect register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_GRER0_VAL 0x00000000
179#define CONFIG_SYS_GRER1_VAL 0x00000000
180#define CONFIG_SYS_GRER2_VAL 0x00000000
wdenkca0e7742004-06-09 15:37:23 +0000181
182/* GP falling edge detect register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_GFER0_VAL 0x00000000
184#define CONFIG_SYS_GFER1_VAL 0x00000000
185#define CONFIG_SYS_GFER2_VAL 0x00000000
wdenkca0e7742004-06-09 15:37:23 +0000186
187/* GP alternate function register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_GAFR0_L_VAL 0x80000000 /* CS1 */
189#define CONFIG_SYS_GAFR0_U_VAL 0x00000010 /* RDY */
190#define CONFIG_SYS_GAFR1_L_VAL 0x09988050 /* FFUART + BTUART pins */
191#define CONFIG_SYS_GAFR1_U_VAL 0x00000008 /* nPWE */
192#define CONFIG_SYS_GAFR2_L_VAL 0xA0000000 /* CS2, CS3 */
193#define CONFIG_SYS_GAFR2_U_VAL 0x00000000
wdenkca0e7742004-06-09 15:37:23 +0000194
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_PSSR_VAL 0x00000020 /* Power manager sleep status */
196#define CONFIG_SYS_CCCR_VAL 0x00000161 /* 100 MHz memory, 400 MHz CPU */
197#define CONFIG_SYS_CKEN_VAL 0x000000C0 /* BTUART and FFUART enabled */
198#define CONFIG_SYS_ICMR_VAL 0x00000000 /* No interrupts enabled */
wdenkca0e7742004-06-09 15:37:23 +0000199
200/* Memory settings */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_MSC0_VAL 0x25F425F0
wdenkca0e7742004-06-09 15:37:23 +0000202
203/* MDCNFG: SDRAM Configuration Register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_MDCNFG_VAL 0x000009C9
wdenkca0e7742004-06-09 15:37:23 +0000205
206/* MDREFR: SDRAM Refresh Control Register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_MDREFR_VAL 0x00018018
wdenkca0e7742004-06-09 15:37:23 +0000208
209/* MDMRS: Mode Register Set Configuration Register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_MDMRS_VAL 0x00220022
wdenkca0e7742004-06-09 15:37:23 +0000211
212#endif /* __CONFIG_H */