blob: dd5ea95e331e4586762920eeccb12537c6703ac2 [file] [log] [blame]
Prabhakar Kushwahaf1593262013-04-16 13:28:25 +05301/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Prabhakar Kushwahaf1593262013-04-16 13:28:25 +05305 */
6
7#include <common.h>
8#include <ns16550.h>
9#include <asm/io.h>
10#include <nand.h>
11#include <linux/compiler.h>
12#include <asm/fsl_law.h>
13#include <asm/fsl_ddr_sdram.h>
14#include <asm/global_data.h>
15
16DECLARE_GLOBAL_DATA_PTR;
17
18/*
19 * Fixed sdram init -- doesn't use serial presence detect.
20 */
21static void sdram_init(void)
22{
23 ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
24
25 __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
26 __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
27#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
28 __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
29 __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
30#endif
31 __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
32 __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
33 __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
34 __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2);
35
36 __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
37 __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode);
38 __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2);
39
40 __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval);
41 __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
42 __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl);
43
44 __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl);
45 __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
46 __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
47 __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
48
49 /* Set, but do not enable the memory */
50 __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
51
52 asm volatile("sync;isync");
53 udelay(500);
54
55 /* Let the controller go */
56 out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
57
58 set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1);
59}
60
61void board_init_f(ulong bootflag)
62{
63 u32 plat_ratio;
64 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
65
66 /* initialize selected port with appropriate baud rate */
67 plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
68 plat_ratio >>= 1;
69 gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
70
71 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
72 gd->bus_clk / 16 / CONFIG_BAUDRATE);
73
74 puts("\nNAND boot... ");
75
76 /* Initialize the DDR3 */
77 sdram_init();
78
79 /* copy code to RAM and jump to it - this should not return */
80 /* NOTE - code has to be copied out of NAND buffer before
81 * other blocks can be read.
82 */
83 relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
84}
85
86void board_init_r(gd_t *gd, ulong dest_addr)
87{
88 nand_boot();
89}
90
91void putc(char c)
92{
93 if (c == '\n')
94 NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
95
96 NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
97}
98
99void puts(const char *str)
100{
101 while (*str)
102 putc(*str++);
103}