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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001
3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkc6097192002-11-03 00:24:07 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020015#define CONFIG_SYS_GT_6426x GT_64260 /* with a 64260 system controller */
wdenkc6097192002-11-03 00:24:07 +000016#define CONFIG_ETHER_PORT_MII /* use two MII ports */
17#define CONFIG_INTEL_LXT97X /* Intel LXT97X phy */
18
19#ifndef __ASSEMBLY__
20#include <galileo/core.h>
21#endif
22
23#include "../board/evb64260/local.h"
24
25#define CONFIG_EVB64260 1 /* this is an EVB64260 board */
26#define CONFIG_ZUMA_V2 1 /* always define this for ZUMA v2 */
27
Wolfgang Denk2ae18242010-10-06 09:05:45 +020028#define CONFIG_SYS_TEXT_BASE 0xfff00000
29
wdenkc6097192002-11-03 00:24:07 +000030/* #define CONFIG_ZUMA_V2_OLD 1 */ /* backwards compat for old V2 board */
31
32#define CONFIG_BAUDRATE 38400 /* console baudrate = 38400 */
33
34#define CONFIG_ECC /* enable ECC support */
35
36#define CONFIG_750CX /* we have a 750CX/CXe (override local.h) */
37
38/* which initialization functions to call for this board */
39#define CONFIG_MISC_INIT_R
wdenkc837dcb2004-01-20 23:12:12 +000040#define CONFIG_BOARD_EARLY_INIT_F
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041#define CONFIG_SYS_BOARD_ASM_INIT
wdenkc6097192002-11-03 00:24:07 +000042
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020043#define CONFIG_SYS_BOARD_NAME "Zuma APv2"
wdenkc6097192002-11-03 00:24:07 +000044
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020045#define CONFIG_SYS_HUSH_PARSER
wdenkc6097192002-11-03 00:24:07 +000046
47/*
48 * The following defines let you select what serial you want to use
49 * for your console driver.
50 *
51 * what to do:
52 * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053 * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1
wdenkc6097192002-11-03 00:24:07 +000054 * to 0 below.
55 *
56 * to use the MPSC, #define CONFIG_MPSC. If you have wired up another
57 * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
58 */
59#define CONFIG_MPSC
60
61#define CONFIG_MPSC_PORT 0
62
wdenkc6097192002-11-03 00:24:07 +000063
64/* define this if you want to enable GT MAC filtering */
65#define CONFIG_GT_USE_MAC_HASH_TABLE
66
67#if 1
68#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
69#else
70#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
71#endif
72#define CONFIG_ZERO_BOOTDELAY_CHECK
73
74#undef CONFIG_BOOTARGS
75
76#define CONFIG_BOOTCOMMAND \
77 "tftpboot && " \
78 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \
79 "ip=$ipaddr:$serverip:$gatewayip:" \
80 "$netmask:$hostname:eth0:none panic=5 && bootm"
81
82#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */
wdenkc6097192002-11-03 00:24:07 +000084
85#undef CONFIG_WATCHDOG /* watchdog disabled */
86#undef CONFIG_ALTIVEC /* undef to disable */
87
Jon Loeliger37d4bb72007-07-09 21:38:02 -050088/*
89 * BOOTP options
90 */
91#define CONFIG_BOOTP_SUBNETMASK
92#define CONFIG_BOOTP_GATEWAY
93#define CONFIG_BOOTP_HOSTNAME
94#define CONFIG_BOOTP_BOOTPATH
95#define CONFIG_BOOTP_BOOTFILESIZE
wdenkc6097192002-11-03 00:24:07 +000096
97#define CONFIG_MII /* enable MII commands */
98
Jon Loeligera5562902007-07-08 15:31:57 -050099
100/*
101 * Command line configuration.
102 */
103#include <config_cmd_default.h>
104
105#define CONFIG_CMD_ASKENV
106#define CONFIG_CMD_BSP
107#define CONFIG_CMD_JFFS2
108#define CONFIG_CMD_MII
109#define CONFIG_CMD_DATE
110
wdenkc6097192002-11-03 00:24:07 +0000111
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200112/*
113 * JFFS2 partitions
114 *
115 */
116/* No command line, one static partition, whole device */
Stefan Roese68d7d652009-03-19 13:30:36 +0100117#undef CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200118#define CONFIG_JFFS2_DEV "nor0"
119#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
120#define CONFIG_JFFS2_PART_OFFSET 0x00000000
121
122/* mtdparts command line support */
123/* Note: fake mtd_id used, no linux mtd map file */
124/*
Stefan Roese68d7d652009-03-19 13:30:36 +0100125#define CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200126#define MTDIDS_DEFAULT "nor1=zuma-1,nor2=zuma-2"
127#define MTDPARTS_DEFAULT "mtdparts=zuma-1:-(jffs2),zuma-2:-(user)"
128*/
wdenkc6097192002-11-03 00:24:07 +0000129
wdenkc6097192002-11-03 00:24:07 +0000130/*
131 * Miscellaneous configurable options
132 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_LONGHELP /* undef to save memory */
134#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligera5562902007-07-08 15:31:57 -0500135#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000137#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000139#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
141#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
142#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkc6097192002-11-03 00:24:07 +0000143
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
145#define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */
wdenkc6097192002-11-03 00:24:07 +0000146
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */
wdenkc6097192002-11-03 00:24:07 +0000148
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */
wdenkc6097192002-11-03 00:24:07 +0000150
Wolfgang Denkee80fa72010-06-13 18:38:23 +0200151#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz */
wdenkc6097192002-11-03 00:24:07 +0000152
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
wdenkc6097192002-11-03 00:24:07 +0000154
155/*
156 * Low Level Configuration Settings
157 * (address mappings, register initial values, etc.)
158 * You should know what you are doing if you make changes here.
159 */
160
161/*-----------------------------------------------------------------------
162 * Definitions for initial stack pointer and data area
163 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200165#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200166#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_INIT_RAM_LOCK
wdenkc6097192002-11-03 00:24:07 +0000168
169
170/*-----------------------------------------------------------------------
171 * Start addresses for the final memory configuration
172 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkc6097192002-11-03 00:24:07 +0000174 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_SDRAM_BASE 0x00000000
176#define CONFIG_SYS_FLASH_BASE 0xfff00000
177#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
178#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
179#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
180#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
wdenkc6097192002-11-03 00:24:07 +0000181
182/* areas to map different things with the GT in physical space */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_DRAM_BANKS 4
184#define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */
wdenkc6097192002-11-03 00:24:07 +0000185
186/* What to put in the bats. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000
wdenkc6097192002-11-03 00:24:07 +0000188
189/* Peripheral Device section */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_GT_REGS 0xf8000000 /* later mapped GT_REGS */
191#define CONFIG_SYS_DEV_BASE 0xf0000000
192#define CONFIG_SYS_DEV0_SIZE _64M /* zuma flash @ 0xf000.0000*/
193#define CONFIG_SYS_DEV1_SIZE _8M /* zuma IDE @ 0xf400.0000 */
194#define CONFIG_SYS_DEV2_SIZE _8M /* unused */
195#define CONFIG_SYS_DEV3_SIZE _8M /* unused */
wdenkc6097192002-11-03 00:24:07 +0000196
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_DEV0_PAR 0xc498243c
wdenkc6097192002-11-03 00:24:07 +0000198 /* c 4 9 8 2 4 3 c */
199 /* 33 22|2222|22 22|111 1|11 11|1 1 | | */
200 /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
201 /* 11|00|0100|10 01|100|0 00|10 0|100 0|011 1|100 */
202 /* 3| 0|.... ..| 1| 4 | 0 | 4 | 8 | 7 | 4 */
203
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_DEV1_PAR 0xc01b6ac5
wdenkc6097192002-11-03 00:24:07 +0000205 /* c 0 1 b 6 a c 5 */
206 /* 33 22|2222|22 22|111 1|11 11|1 1 | | */
207 /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
208 /* 11|00|0000|00 01|101|1 01|10 1|010 1|100 0|101 */
209 /* 3| 0|.... ..| 1| 5 | 5 | 5 | 5 | 8 | 5 */
210
211
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_8BIT_BOOT_PAR 0xc00b5e7c
wdenkc6097192002-11-03 00:24:07 +0000213
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_MPP_CONTROL_0 0x00007777 /* GPP[7:4] : REQ0[1:0] GNT0[1:0] */
215#define CONFIG_SYS_MPP_CONTROL_1 0x00000000 /* GPP[15:12] : GPP[11:8] */
216#define CONFIG_SYS_MPP_CONTROL_2 0x00008888 /* GPP[23:20] : REQ1[1:0] GNT1[1:0] */
217#define CONFIG_SYS_MPP_CONTROL_3 0x00000000 /* GPP[31:28] (int[3:0]) */
wdenkc6097192002-11-03 00:24:07 +0000218 /* GPP[27:24] (27 is int4, rest are GPP) */
219
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_SERIAL_PORT_MUX 0x00001101 /* 11=MPSC1/MPSC0 01=ETH, 0=only MII */
221#define CONFIG_SYS_GPP_LEVEL_CONTROL 0xf8000000 /* interrupt inputs: GPP[31:27] */
wdenkc6097192002-11-03 00:24:07 +0000222
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_SDRAM_CONFIG 0xe4e18200 /* 0x448 */
wdenkc6097192002-11-03 00:24:07 +0000224 /* idmas use buffer 1,1
225 comm use buffer 1
226 pci use buffer 0,0 (pci1->0 pci0->0)
227 cpu use buffer 1 (R*18)
228 normal load (see also ifdef HVL)
229 standard SDRAM (see also ifdef REG)
230 non staggered refresh */
231 /* 31:26 25 23 20 19 18 16 */
232 /* 111001 00 111 0 0 00 1 */
233
234 /* refresh count=0x200
235 phy interleave disable (by default,
236 set later by dram config..)
237 virt interleave enable */
238 /* 15 14 13:0 */
239 /* 1 0 0x200 */
240
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE
242#define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE)
243#define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE)
244#define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE)
wdenkc6097192002-11-03 00:24:07 +0000245
246/*-----------------------------------------------------------------------
247 * PCI stuff
248 */
249
250#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
251#define PCI_HOST_FORCE 1 /* configure as pci host */
252#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
253
254#define CONFIG_PCI /* include pci support */
255#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
256#define CONFIG_PCI_PNP /* do pci plug-and-play */
257
258/* PCI MEMORY MAP section */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000
260#define CONFIG_SYS_PCI0_MEM_SIZE _128M
261#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000
262#define CONFIG_SYS_PCI1_MEM_SIZE _128M
wdenkc6097192002-11-03 00:24:07 +0000263
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE)
265#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE)
wdenkc6097192002-11-03 00:24:07 +0000266
267/* PCI I/O MAP section */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000
269#define CONFIG_SYS_PCI0_IO_SIZE _16M
270#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000
271#define CONFIG_SYS_PCI1_IO_SIZE _16M
wdenkc6097192002-11-03 00:24:07 +0000272
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE)
274#define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000
275#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE)
276#define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000
wdenkc6097192002-11-03 00:24:07 +0000277
278
279/*----------------------------------------------------------------------
280 * Initial BAT mappings
281 */
282
283/* NOTES:
284 * 1) GUARDED and WRITE_THRU not allowed in IBATS
285 * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
286 */
287
288/* SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
290#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
291#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
292#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
wdenkc6097192002-11-03 00:24:07 +0000293
294/* init ram */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
296#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
297#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
298#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
wdenkc6097192002-11-03 00:24:07 +0000299
300/* PCI0, PCI1 memory space (starting at PCI0 base, mapped in one BAT) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
302#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
303#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
304#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
wdenkc6097192002-11-03 00:24:07 +0000305
306/* GT regs, bootrom, all the devices, PCI I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
308#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
309#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
310#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
wdenkc6097192002-11-03 00:24:07 +0000311
312/*
313 * For booting Linux, the board info and command line data
314 * have to be in the first 8 MB of memory, since this is
315 * the maximum mapped by the Linux kernel during initialization.
316 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
wdenkc6097192002-11-03 00:24:07 +0000318
319
320/*-----------------------------------------------------------------------
321 * FLASH organization
322 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max number of memory banks */
324#define CONFIG_SYS_MAX_FLASH_SECT 130 /* max number of sectors on one chip */
wdenkc6097192002-11-03 00:24:07 +0000325
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_EXTRA_FLASH_DEVICE DEVICE0 /* extra flash at device 0 */
327#define CONFIG_SYS_EXTRA_FLASH_WIDTH 2 /* 16 bit */
wdenkc6097192002-11-03 00:24:07 +0000328
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
330#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
331#define CONFIG_SYS_FLASH_CFI 1
wdenkc6097192002-11-03 00:24:07 +0000332
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200333#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200334#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
335#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
336#define CONFIG_ENV_ADDR (0xfff80000 - CONFIG_ENV_SECT_SIZE)
wdenkc6097192002-11-03 00:24:07 +0000337
338/*-----------------------------------------------------------------------
339 * Cache Configuration
340 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
Jon Loeligera5562902007-07-08 15:31:57 -0500342#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenkc6097192002-11-03 00:24:07 +0000344#endif
345
346/*-----------------------------------------------------------------------
347 * L2CR setup -- make sure this is right for your board!
wdenk1d0350e2002-11-11 21:14:20 +0000348 * look in include/74xx_7xx.h for the defines used here
wdenkc6097192002-11-03 00:24:07 +0000349 */
350
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define CONFIG_SYS_L2
wdenkc6097192002-11-03 00:24:07 +0000352
353#ifdef CONFIG_750CX
354#define L2_INIT 0
355#else
356#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
357 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
358#endif
359
360#define L2_ENABLE (L2_INIT | L2CR_L2E)
361
362/*------------------------------------------------------------------------
363 * Real time clock
364 */
365#define CONFIG_RTC_DS1302
366
367
368/*------------------------------------------------------------------------
369 * Galileo I2C driver
370 */
371#define CONFIG_GT_I2C
372
wdenkc6097192002-11-03 00:24:07 +0000373#endif /* __CONFIG_H */