blob: 9199f01b9bb2904b6daae770391f38f6d640bc33 [file] [log] [blame]
Kumar Gala5ba40ee2010-04-26 23:44:10 -05001/*
2 * Copyright 2010 Freescale Semiconductor, Inc.
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Kumar Gala5ba40ee2010-04-26 23:44:10 -05005 */
6
7#include <config.h>
8#include <common.h>
9#include <asm/io.h>
10#include <asm/immap_85xx.h>
11#include <asm/fsl_serdes.h>
12
13#define SRDS1_MAX_LANES 8
14
15static u32 serdes1_prtcl_map;
16
17static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
18 [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1},
19 [0x4] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1},
20 [0x5] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1},
21 [0x6] = {NONE, NONE, NONE, NONE, SRIO1, SRIO1, SRIO1, SRIO1},
22 [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1},
23};
24
25int is_serdes_configured(enum srds_prtcl prtcl)
26{
27 return (1 << prtcl) & serdes1_prtcl_map;
28}
29
30void fsl_serdes_init(void)
31{
32 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
33 u32 pordevsr = in_be32(&gur->pordevsr);
34 u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
35 MPC85xx_PORDEVSR_IO_SEL_SHIFT;
36 int lane;
37
38 debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
39
Axel Line51e47d2013-05-26 15:00:30 +080040 if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
Kumar Gala5ba40ee2010-04-26 23:44:10 -050041 printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
42 return;
43 }
44
45 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
46 enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
47 serdes1_prtcl_map |= (1 << lane_prtcl);
48 }
49}