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Michal Simekf7c8e492018-03-28 15:36:36 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP ZCU104
4 *
5 * (C) Copyright 2017 - 2018, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk-ccf.dtsi"
14#include <dt-bindings/gpio/gpio.h>
15#include <dt-bindings/phy/phy.h>
16
17/ {
18 model = "ZynqMP ZCU104 RevC";
19 compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
20
21 aliases {
22 ethernet0 = &gem3;
23 gpio0 = &gpio;
24 i2c0 = &i2c1;
25 mmc0 = &sdhci1;
26 rtc0 = &rtc;
27 serial0 = &uart0;
28 serial1 = &uart1;
29 serial2 = &dcc;
30 spi0 = &qspi;
31 usb0 = &usb0;
32 };
33
34 chosen {
35 bootargs = "earlycon";
36 stdout-path = "serial0:115200n8";
37 };
38
39 memory@0 {
40 device_type = "memory";
41 reg = <0x0 0x0 0x0 0x80000000>;
42 };
43};
44
45&can1 {
46 status = "okay";
47};
48
49&dcc {
50 status = "okay";
51};
52
53&gem3 {
54 status = "okay";
55 phy-handle = <&phy0>;
56 phy-mode = "rgmii-id";
57 phy0: phy@c {
58 reg = <0xc>;
59 ti,rx-internal-delay = <0x8>;
60 ti,tx-internal-delay = <0xa>;
61 ti,fifo-depth = <0x1>;
62 };
63};
64
65&gpio {
66 status = "okay";
67};
68
69&gpu {
70 status = "okay";
71};
72
73&i2c1 {
74 status = "okay";
75 clock-frequency = <400000>;
76
77 tca6416_u97: gpio@21 {
78 compatible = "ti,tca6416";
79 reg = <0x21>;
80 gpio-controller;
81 #gpio-cells = <2>;
82 /*
83 * IRQ not connected
84 * Lines:
85 * 0 - IRPS5401_ALERT_B
86 * 1 - HDMI_8T49N241_INT_ALM
87 * 2 - MAX6643_OT_B
88 * 3 - MAX6643_FANFAIL_B
89 * 5 - IIC_MUX_RESET_B
90 * 6 - GEM3_EXP_RESET_B
91 * 7 - FMC_LPC_PRSNT_M2C_B
92 * 4, 10 - 17 - not connected
93 */
94 };
95
96 /* Another connection to this bus via PL i2c via PCA9306 - u45 */
97 i2c-mux@74 { /* u34 */
98 compatible = "nxp,pca9548";
99 #address-cells = <1>;
100 #size-cells = <0>;
101 reg = <0x74>;
102 i2c@0 {
103 #address-cells = <1>;
104 #size-cells = <0>;
105 reg = <0>;
106 /*
107 * IIC_EEPROM 1kB memory which uses 256B blocks
108 * where every block has different address.
109 * 0 - 256B address 0x54
110 * 256B - 512B address 0x55
111 * 512B - 768B address 0x56
112 * 768B - 1024B address 0x57
113 */
114 eeprom: eeprom@54 { /* u23 */
115 compatible = "atmel,24c08";
116 reg = <0x54>;
117 #address-cells = <1>;
118 #size-cells = <1>;
119 };
120 };
121
122 i2c@1 {
123 #address-cells = <1>;
124 #size-cells = <0>;
125 reg = <1>;
126 clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */
127 compatible = "idt,8t49n287";
128 reg = <0x6c>;
129 };
130 };
131
132 i2c@2 {
133 #address-cells = <1>;
134 #size-cells = <0>;
135 reg = <2>;
136 irps5401_43: irps54012@43 { /* IRPS5401 - u175 */
137 #clock-cells = <0>;
138 compatible = "infineon,irps5401";
139 reg = <0x43>;
140 };
141 irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */
142 #clock-cells = <0>;
143 compatible = "infineon,irps5401";
144 reg = <0x4d>;
145 };
146 };
147
Michal Simek3705dae2018-05-29 14:45:13 +0200148 i2c@3 {
Michal Simekf7c8e492018-03-28 15:36:36 +0200149 #address-cells = <1>;
150 #size-cells = <0>;
Michal Simek3705dae2018-05-29 14:45:13 +0200151 reg = <3>;
152 ina226@40 { /* u183 */
153 compatible = "ti,ina226";
154 reg = <0x40>;
155 shunt-resistor = <5000>;
156 };
Michal Simekf7c8e492018-03-28 15:36:36 +0200157 };
158
159 i2c@5 {
160 #address-cells = <1>;
161 #size-cells = <0>;
162 reg = <5>;
163 };
164
165 i2c@7 {
166 #address-cells = <1>;
167 #size-cells = <0>;
168 reg = <7>;
169 };
170
Michal Simek3705dae2018-05-29 14:45:13 +0200171 /* 4, 6 not connected */
Michal Simekf7c8e492018-03-28 15:36:36 +0200172 };
173};
174
175&qspi {
176 status = "okay";
177 flash@0 {
178 compatible = "m25p80"; /* n25q512a 128MiB */
179 #address-cells = <1>;
180 #size-cells = <1>;
181 reg = <0x0>;
182 spi-tx-bus-width = <1>;
183 spi-rx-bus-width = <4>;
184 spi-max-frequency = <108000000>; /* Based on DC1 spec */
185 partition@qspi-fsbl-uboot { /* for testing purpose */
186 label = "qspi-fsbl-uboot";
187 reg = <0x0 0x100000>;
188 };
189 partition@qspi-linux { /* for testing purpose */
190 label = "qspi-linux";
191 reg = <0x100000 0x500000>;
192 };
193 partition@qspi-device-tree { /* for testing purpose */
194 label = "qspi-device-tree";
195 reg = <0x600000 0x20000>;
196 };
197 partition@qspi-rootfs { /* for testing purpose */
198 label = "qspi-rootfs";
199 reg = <0x620000 0x5E0000>;
200 };
201 };
202};
203
204&rtc {
205 status = "okay";
206};
207
208&sata {
209 status = "okay";
210 /* SATA OOB timing settings */
211 ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
212 ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
213 ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
214 ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
215 ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
216 ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
217 ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
218 ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
219 phy-names = "sata-phy";
220 phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
221};
222
223/* SD1 with level shifter */
224&sdhci1 {
225 status = "okay";
226 no-1-8-v;
227 xlnx,mio_bank = <1>;
228 disable-wp;
229};
230
231&serdes {
232 status = "okay";
233};
234
235&uart0 {
236 status = "okay";
237};
238
239&uart1 {
240 status = "okay";
241};
242
243/* ULPI SMSC USB3320 */
244&usb0 {
245 status = "okay";
246};
247
248&dwc3_0 {
249 status = "okay";
250 dr_mode = "host";
251 snps,usb3_lpm_capable;
252 phy-names = "usb3-phy";
253 phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
254 maximum-speed = "super-speed";
255};
256
257&watchdog0 {
258 status = "okay";
259};
260
261&xilinx_ams {
262 status = "okay";
263};
264
265&ams_ps {
266 status = "okay";
267};
268
269&ams_pl {
270 status = "okay";
271};