Stefan Roese | 58eb869 | 2010-07-21 19:06:10 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2010 |
| 3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | * |
| 23 | */ |
| 24 | |
| 25 | #include <common.h> |
Stefan Roese | b36df56 | 2010-09-09 19:18:00 +0200 | [diff] [blame] | 26 | #include <asm/ppc4xx.h> |
Stefan Roese | 58eb869 | 2010-07-21 19:06:10 +0200 | [diff] [blame] | 27 | #include <asm/processor.h> |
| 28 | #include <asm/io.h> |
| 29 | #include <asm/cache.h> |
| 30 | |
| 31 | #if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR) || \ |
| 32 | defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2) |
| 33 | #if defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) |
| 34 | |
| 35 | #if defined(CONFIG_405EX) |
| 36 | /* |
| 37 | * Currently only 405EX uses 16bit data bus width as an alternative |
| 38 | * option to 32bit data width (SDRAM0_MCOPT1_WDTH) |
| 39 | */ |
| 40 | #define SDRAM_DATA_ALT_WIDTH 2 |
| 41 | #else |
| 42 | #define SDRAM_DATA_ALT_WIDTH 8 |
| 43 | #endif |
| 44 | |
| 45 | #if defined(CONFIG_SYS_OCM_BASE) |
| 46 | #define CONFIG_FUNC_ISRAM_ADDR CONFIG_SYS_OCM_BASE |
| 47 | #endif |
| 48 | |
| 49 | #if defined(CONFIG_SYS_ISRAM_BASE) |
| 50 | #define CONFIG_FUNC_ISRAM_ADDR CONFIG_SYS_ISRAM_BASE |
| 51 | #endif |
| 52 | |
| 53 | #if !defined(CONFIG_FUNC_ISRAM_ADDR) |
| 54 | #error "No internal SRAM/OCM provided!" |
| 55 | #endif |
| 56 | |
| 57 | #define force_inline inline __attribute__ ((always_inline)) |
| 58 | |
| 59 | static inline void machine_check_disable(void) |
| 60 | { |
| 61 | mtmsr(mfmsr() & ~MSR_ME); |
| 62 | } |
| 63 | |
| 64 | static inline void machine_check_enable(void) |
| 65 | { |
| 66 | mtmsr(mfmsr() | MSR_ME); |
| 67 | } |
| 68 | |
| 69 | /* |
| 70 | * These helper functions need to be inlined, since they |
| 71 | * are called from the functions running from internal SRAM. |
| 72 | * SDRAM operation is forbidden at that time, so calling |
| 73 | * functions in SDRAM has to be avoided. |
| 74 | */ |
| 75 | static force_inline void wait_ddr_idle(void) |
| 76 | { |
| 77 | u32 val; |
| 78 | |
| 79 | do { |
| 80 | mfsdram(SDRAM_MCSTAT, val); |
| 81 | } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT); |
| 82 | } |
| 83 | |
| 84 | static force_inline void recalibrate_ddr(void) |
| 85 | { |
| 86 | u32 val; |
| 87 | |
| 88 | /* |
| 89 | * Rewrite RQDC & RFDC to calibrate again. If this is not |
| 90 | * done, the SDRAM controller is working correctly after |
| 91 | * changing the MCOPT1_MCHK bits. |
| 92 | */ |
| 93 | mfsdram(SDRAM_RQDC, val); |
| 94 | mtsdram(SDRAM_RQDC, val); |
| 95 | mfsdram(SDRAM_RFDC, val); |
| 96 | mtsdram(SDRAM_RFDC, val); |
| 97 | } |
| 98 | |
| 99 | static force_inline void set_mcopt1_mchk(u32 bits) |
| 100 | { |
| 101 | u32 val; |
| 102 | |
| 103 | wait_ddr_idle(); |
| 104 | mfsdram(SDRAM_MCOPT1, val); |
| 105 | mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) | bits); |
| 106 | recalibrate_ddr(); |
| 107 | } |
| 108 | |
| 109 | /* |
| 110 | * The next 2 functions are copied to internal SRAM/OCM and run |
| 111 | * there. No function calls allowed here. No SDRAM acitivity should |
| 112 | * be done here. |
| 113 | */ |
| 114 | static void inject_ecc_error(void *ptr, int par) |
| 115 | { |
Stefan Roese | 58eb869 | 2010-07-21 19:06:10 +0200 | [diff] [blame] | 116 | /* |
| 117 | * Taken from PPC460EX/EXr/GT users manual (Rev 1.21) |
| 118 | * 22.2.17.13 ECC Diagnostics |
| 119 | * |
| 120 | * Items 1 ... 5 are already done by now, running from RAM |
| 121 | * with ECC enabled |
| 122 | */ |
| 123 | |
| 124 | out_be32(ptr, 0x00000000); |
Stefan Roese | a6370da | 2011-11-15 08:02:18 +0000 | [diff] [blame] | 125 | in_be32(ptr); |
Stefan Roese | 58eb869 | 2010-07-21 19:06:10 +0200 | [diff] [blame] | 126 | |
| 127 | /* 6. Set memory controller to no error checking */ |
| 128 | set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_NON); |
| 129 | |
| 130 | /* 7. Modify one or two bits for error simulation */ |
| 131 | if (par == 1) |
| 132 | out_be32(ptr, in_be32(ptr) ^ 0x00000001); |
| 133 | else |
| 134 | out_be32(ptr, in_be32(ptr) ^ 0x00000003); |
| 135 | |
| 136 | /* 8. Wait for SDRAM idle */ |
Stefan Roese | a6370da | 2011-11-15 08:02:18 +0000 | [diff] [blame] | 137 | in_be32(ptr); |
Stefan Roese | 58eb869 | 2010-07-21 19:06:10 +0200 | [diff] [blame] | 138 | set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_CHK_REP); |
| 139 | |
| 140 | /* Wait for SDRAM idle */ |
| 141 | wait_ddr_idle(); |
| 142 | |
| 143 | /* Continue with 9. in calling function... */ |
| 144 | } |
| 145 | |
| 146 | static void rewrite_ecc_parity(void *ptr, int par) |
| 147 | { |
| 148 | u32 current_address = (u32)ptr; |
| 149 | u32 end_address; |
| 150 | u32 address_increment; |
| 151 | u32 mcopt1; |
Stefan Roese | 58eb869 | 2010-07-21 19:06:10 +0200 | [diff] [blame] | 152 | |
| 153 | /* |
| 154 | * Fill ECC parity byte again. Otherwise further accesses to |
| 155 | * the failure address will result in exceptions. |
| 156 | */ |
| 157 | |
| 158 | /* Wait for SDRAM idle */ |
Stefan Roese | a6370da | 2011-11-15 08:02:18 +0000 | [diff] [blame] | 159 | in_be32(0x00000000); |
Stefan Roese | 58eb869 | 2010-07-21 19:06:10 +0200 | [diff] [blame] | 160 | set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_GEN); |
| 161 | |
| 162 | /* ECC bit set method for non-cached memory */ |
| 163 | mfsdram(SDRAM_MCOPT1, mcopt1); |
| 164 | if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32) |
| 165 | address_increment = 4; |
| 166 | else |
| 167 | address_increment = SDRAM_DATA_ALT_WIDTH; |
| 168 | end_address = current_address + CONFIG_SYS_CACHELINE_SIZE; |
| 169 | |
| 170 | while (current_address < end_address) { |
| 171 | *((unsigned long *)current_address) = 0; |
| 172 | current_address += address_increment; |
| 173 | } |
| 174 | |
| 175 | set_mcopt1_mchk(SDRAM_MCOPT1_MCHK_CHK_REP); |
| 176 | |
| 177 | /* Wait for SDRAM idle */ |
| 178 | wait_ddr_idle(); |
| 179 | } |
| 180 | |
| 181 | static int do_ecctest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
| 182 | { |
| 183 | u32 old_val; |
| 184 | u32 val; |
| 185 | u32 *ptr; |
| 186 | void (*sram_func)(u32 *, int); |
| 187 | int error; |
| 188 | |
| 189 | if (argc < 3) { |
Thomas Weber | e03dabe | 2010-11-25 08:05:30 +0100 | [diff] [blame] | 190 | return cmd_usage(cmdtp); |
Stefan Roese | 58eb869 | 2010-07-21 19:06:10 +0200 | [diff] [blame] | 191 | } |
| 192 | |
| 193 | ptr = (u32 *)simple_strtoul(argv[1], NULL, 16); |
| 194 | error = simple_strtoul(argv[2], NULL, 16); |
| 195 | if ((error < 1) || (error > 2)) { |
Thomas Weber | e03dabe | 2010-11-25 08:05:30 +0100 | [diff] [blame] | 196 | return cmd_usage(cmdtp); |
Stefan Roese | 58eb869 | 2010-07-21 19:06:10 +0200 | [diff] [blame] | 197 | } |
| 198 | |
| 199 | printf("Using address %p for %d bit ECC error injection\n", |
| 200 | ptr, error); |
| 201 | |
| 202 | /* |
| 203 | * Save value to restore it later on |
| 204 | */ |
| 205 | old_val = in_be32(ptr); |
| 206 | |
| 207 | /* |
| 208 | * Copy ECC injection function into internal SRAM/OCM |
| 209 | */ |
| 210 | sram_func = (void *)CONFIG_FUNC_ISRAM_ADDR; |
| 211 | memcpy((void *)CONFIG_FUNC_ISRAM_ADDR, inject_ecc_error, 0x10000); |
| 212 | |
| 213 | /* |
| 214 | * Disable interrupts and exceptions before calling this |
| 215 | * function in internal SRAM/OCM |
| 216 | */ |
| 217 | disable_interrupts(); |
| 218 | machine_check_disable(); |
| 219 | eieio(); |
| 220 | |
| 221 | /* |
| 222 | * Jump to ECC simulation function in internal SRAM/OCM |
| 223 | */ |
| 224 | (*sram_func)(ptr, error); |
| 225 | |
| 226 | /* 10. Read the corresponding address */ |
| 227 | val = in_be32(ptr); |
| 228 | |
| 229 | /* |
| 230 | * Read and print ECC status register/info: |
| 231 | * The faulting address is only known upon uncorrectable ECC |
| 232 | * errors. |
| 233 | */ |
| 234 | mfsdram(SDRAM_ECCES, val); |
| 235 | if (val & SDRAM_ECCES_CE) |
| 236 | printf("ECC: Correctable error\n"); |
| 237 | if (val & SDRAM_ECCES_UE) { |
| 238 | printf("ECC: Uncorrectable error at 0x%02x%08x\n", |
| 239 | mfdcr(SDRAM_ERRADDULL), mfdcr(SDRAM_ERRADDLLL)); |
| 240 | } |
| 241 | |
| 242 | /* |
| 243 | * Clear pending interrupts/exceptions |
| 244 | */ |
| 245 | mtsdram(SDRAM_ECCES, 0xffffffff); |
| 246 | mtdcr(SDRAM_ERRSTATLL, 0xff000000); |
| 247 | set_mcsr(get_mcsr()); |
| 248 | |
| 249 | /* Now enable interrupts and exceptions again */ |
| 250 | eieio(); |
| 251 | machine_check_enable(); |
| 252 | enable_interrupts(); |
| 253 | |
| 254 | /* |
| 255 | * The ECC parity byte need to be re-written for the |
| 256 | * corresponding address. Otherwise future accesses to it |
| 257 | * will result in exceptions. |
| 258 | * |
| 259 | * Jump to ECC parity generation function |
| 260 | */ |
| 261 | memcpy((void *)CONFIG_FUNC_ISRAM_ADDR, rewrite_ecc_parity, 0x10000); |
| 262 | (*sram_func)(ptr, 0); |
| 263 | |
| 264 | /* |
| 265 | * Restore value in corresponding address |
| 266 | */ |
| 267 | out_be32(ptr, old_val); |
| 268 | |
| 269 | return 0; |
| 270 | } |
| 271 | |
| 272 | U_BOOT_CMD( |
| 273 | ecctest, 3, 0, do_ecctest, |
| 274 | "Test ECC by single and double error bit injection", |
| 275 | "address 1/2" |
| 276 | ); |
| 277 | |
| 278 | #endif /* defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) */ |
| 279 | #endif /* defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)... */ |